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3 results on '"Maneux, Cristell"'

1. Circuit Design Flow dedicated to 3D vertical nanowire FET

Author

Maneux, Cristell, Chhandak, Mukherjee, Deng, Marina, Neckel Wesling, Bruno, Réveil, Lucas, Stanojevic, Zlatan, Baumgartner, Oskar, O'Connor, Ian, Poittevin, Arnaud, Larrieu, Guilhem, Laboratoire de l'intégration, du matériau au système (IMS), Université Sciences et Technologies - Bordeaux 1 (UB)-Institut Polytechnique de Bordeaux-Centre National de la Recherche Scientifique (CNRS), Global TCAD Solutions, Institut des Nanotechnologies de Lyon (INL), École Centrale de Lyon (ECL), Université de Lyon-Université de Lyon-Université Claude Bernard Lyon 1 (UCBL), Université de Lyon-École Supérieure de Chimie Physique Électronique de Lyon (CPE)-Institut National des Sciences Appliquées de Lyon (INSA Lyon), Université de Lyon-Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Centre National de la Recherche Scientifique (CNRS), Équipe Matériaux et Procédés pour la Nanoélectronique (LAAS-MPN), Laboratoire d'analyse et d'architecture des systèmes (LAAS), Université Toulouse Capitole (UT Capitole), Université de Toulouse (UT)-Université de Toulouse (UT)-Institut National des Sciences Appliquées - Toulouse (INSA Toulouse), Institut National des Sciences Appliquées (INSA)-Université de Toulouse (UT)-Institut National des Sciences Appliquées (INSA)-Université Toulouse - Jean Jaurès (UT2J), Université de Toulouse (UT)-Université Toulouse III - Paul Sabatier (UT3), Université de Toulouse (UT)-Centre National de la Recherche Scientifique (CNRS)-Institut National Polytechnique (Toulouse) (Toulouse INP), Université de Toulouse (UT)-Université Toulouse Capitole (UT Capitole), Université de Toulouse (UT), and ANR-18-CE24-0005,LEGO,Portes logiques élémentaires empillées(2018)

Subjects
[SPI]Engineering Sciences [physics], [SPI.TRON]Engineering Sciences [physics]/Electronics
Abstract

International audience; To continue transistor downscaling beyond lateral 7nm devices, gate-all-around (GAA) junction-less vertical nanowire field effect transistors (VNWFET) represent a promising option. This invited paper presents the circuit design flow based on a vertical junctionless transistor technology. On the basis of state-of-the-art junctionless nanowire transistors (JLNT), DC characterization, compact modelling, EM simulation and parameter extraction are described in details. Using this circuit design flow, a set of innovative 3D circuit architectures are explored.

Published
2022
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2. Extraction of small-signal equivalent circuit for de-embedding of 3D vertical nanowire transistor

Author

Neckel Wesling, Bruno, Deng, Marina, Chhandak, Mukherjee, de Matos, Magali, Kumar, Abhishek, Larrieu, Guilhem, Trommer, Jens, Mikolajick, Thomas, Maneux, Cristell, Laboratoire de l'intégration, du matériau au système (IMS), Université Sciences et Technologies - Bordeaux 1 (UB)-Institut Polytechnique de Bordeaux-Centre National de la Recherche Scientifique (CNRS), Équipe Matériaux et Procédés pour la Nanoélectronique (LAAS-MPN), Laboratoire d'analyse et d'architecture des systèmes (LAAS), Université Toulouse Capitole (UT Capitole), Université de Toulouse (UT)-Université de Toulouse (UT)-Institut National des Sciences Appliquées - Toulouse (INSA Toulouse), Institut National des Sciences Appliquées (INSA)-Université de Toulouse (UT)-Institut National des Sciences Appliquées (INSA)-Université Toulouse - Jean Jaurès (UT2J), Université de Toulouse (UT)-Université Toulouse III - Paul Sabatier (UT3), Université de Toulouse (UT)-Centre National de la Recherche Scientifique (CNRS)-Institut National Polytechnique (Toulouse) (Toulouse INP), Université de Toulouse (UT)-Université Toulouse Capitole (UT Capitole), Université de Toulouse (UT), NaMLab gGmbH, and ANR-18-CE24-0005,LEGO,Portes logiques élémentaires empillées(2018)

Subjects
Equivalent circuit, Parasitic components, De-embedding, Hardware_INTEGRATEDCIRCUITS, Materials Chemistry, Hardware_PERFORMANCEANDRELIABILITY, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, Electrical and Electronic Engineering, RF measurements, Condensed Matter Physics, Test structure, Hardware_LOGICDESIGN, Electronic, Optical and Magnetic Materials
Abstract

International audience; In this paper, we present an improved methodology to extract the small-signal electrical equivalent circuit of the parasitic elements using RF test structures for a 3D vertical nanowire transistor technology. The methodology is based on the extraction of the distributed parasitic elements from an open structure for which on-wafer S-parameter measurements were carried out up to 40 GHz. The electrical equivalent circuit of the passive device was then used for de-embedding of the transistor S-parameters for extraction of intrinsic smallsignal parameters such as the gate capacitances.

Published
2022
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3. InP/GaAsSb/InP DHBT: Analysis of specific material parameters and high current effect by physical simulation

Author

Maneux, Cristell, Belhaj, Mohamed, Labat, Nathalie, Touboul, Andre, Riet, Muriel, Kahn, Myrtil L., Godin, Jean, Bove, Philippe, Laboratoire de l'intégration, du matériau au système (IMS), Université Sciences et Technologies - Bordeaux 1-Institut Polytechnique de Bordeaux-Centre National de la Recherche Scientifique (CNRS), and Import, Ims

Subjects
[SPI.NANO] Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, ING-INF/01 Elettronica, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics
Abstract

Although InP/GaAs0.51Sb0.49/InP DHBT has recently attracted much interest, some sensitive material parameters are still uncertain. We detailed the simulation methodology used to evaluate bandgap energy, minority carrier lifetime and band gap narrowing effect. Moreover, the high-injection effect is analysed as resulting from electron parasitic barrier formation at base-collector junction.

Published
2004
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