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A memory structure containing ultra-small 2-nm laser-synthesized silicon nanoparticles is demonstrated. The Si-nanoparticles are embedded between an atomic layer deposited high- dielectric Al2O3 layer and a sputtered SiO2 layer. A memory effect due to charging of the Si nanoparticles is observed using high frequency C-V measurements. The shift of the threshold voltage obtained from the hysteresis measurements is around 3.3V at 10/-10V gate voltage sweeping. The analysis of the energy band diagram of the memory structure and the negative shift of the programmed C-V curve indicate that holes are tunneling from p-type Si via Fowler-Nordheim tunneling and are being trapped in the Si nanoparticles. In addition, the structures show good endurance characteristic (>10(5)program/erase cycles) and long retention time (>10 years), which make them promising for applications in non-volatile memory devices.

In this work, the fabrication of charge trapping memory cells with laser-synthesized indium-nitride nanoparticles (InN-NPs) embedded in ZnO charge trapping layer is demonstrated. Atomic layer deposited Al2O3 layers are used as tunnel and blocking oxides. The gate contacts are sputtered using a shadow mask which eliminates the need for any lithography steps. High frequency C-V-gate measurements show that a memory effect is observed, due to the charging of the InN-NPs. With a low operating voltage of 4V, the memory shows a noticeable threshold voltage (V-iota) shift of 2V, which indicates that InN-NPs act as charge trapping centers. Without InN-NPs, the observed memory hysteresis is negligible. At higher programming voltages of 10 V, a memory window of 5V is achieved and the V-iota shift direction indicates that electrons tunnel from channel to charge storage layer. (C) 2014 AIP Publishing LLC.