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Wide-bandgap power devices have enabled singlephase totem-pole (TP) power factor correction (PFC) converter designs to be switched at several tens of kilohertz under hardswitching and hundreds of kilohertz under soft-switching. It is straightforward to analyze and compare the volume of boost inductor for TP PFC converters having multileg and multilevel configurations operating under continuous-conduction-mode (CCM) and critical-conduction-mode (CrM) at various switching frequencies; however, the impact of topology and switching frequency selections remains unchallenged for generated differential mode (DM) noise. This article proposes a unified and generalized DM noise estimation method for multileg, and multilevel TP PFC converters operated under both CCM and CrM operation modes. The method has been verified with simulation results obtained from various TP PFC topologies, as well as experimental results obtained from singleleg CCM and 4-Level CCM TP PFC converters. The empirically determined boxed sizes of DM filters have been compared among various TP PFC topologies, and the best switching frequency for each topology has been determined with the integration of boost inductor volume comparison.

Fault diagnosis and failure prognosis of power electronics systems are essential for various mission critical applications, where safety, continuity, and survivability of the system are of paramount importance. With the recent advances in power device failure precursor identification and lifetime estimation, it is possible to extend the lifetime of the power devices, and thereby converters through secondary control schemes. The essence of the lifetime extension strategies relies on either reducing the power loss on the degraded device(s) and shifting it to other parts, or decreasing the total power loss of the converter. As the power converters are optimized for efficiency and total harmonic distortion (THD) requirements, these secondary control strategies can result in operations above the design limits. This paper proposes a hybrid secondary lifetime extension control scheme for three-phase inverters based on the identified failure precursors, which dynamically changes the modulation scheme and adjusts the switching frequency. In the content of this paper, the tradeoff between the THD and achievable lifetime extension is addressed, and a control algorithm is proposed, which maximizes the lifetime with feasible lowest THD.

In this paper, a novel soft-switching secondary-side modulated dc–dc structure with extended zero voltage switching (ZVS) range is proposed. In a simple manner, this structure can be extended to provide isolated multioutputs with independent voltage regulation capability. Besides, the secondary side can be bidirectional to interface with energy storage elements such as batteries and ultracapacitors. The proposed topology is suitable for high voltage gain or high output dc-link voltage, low-power, and multioutput applications. The primary-side full-bridge switches operate complementarily to generate a two-level square wave. Therefore, the circulating energy is significantly smaller than conventional phase-modulated full-bridge converters. The output voltage is regulated by controlling the duty cycle of the auxiliary mosfet on the active/semiactive rectifier, which offers a simple control. Moreover, the ZVS operation range of full-bridge mosfet s is enhanced due to the volt-second balance of magnetizing inductance and the secondary-side control. All the secondary-side rectifying diodes turn off with limited di / dt. A 1-kW prototype generating two 390 V, 330–400 V outputs from a 130–180 V dc link is designed to serve as a proof of concept. The full-load efficiency is 95.6% at 100 kHz switching frequency.

EMI filters are traditionally designed to attenuate the low-frequency harmonics as the filter exhibits an insertion gain of -20 dB/decade per added filter component which inherently attenuates the high-frequency noise. However, the self-parasitics of EMI filter components and mutual couplings between the components and traces decrease the attenuation capability of the filter at higher frequencies. This paper model the filter components and traces in ANSYS high-frequency structure simulator (HFSS) tool and attempts to relate the couplings to the filter and trace placements. A single-stage differential mode (DM) filter has been analyzed and optimum component placement has been identified. It has been shown that on average 17 dB higher insertion gain can be achieved with layout optimization in comparison to commonly used component placement.

Discrete package insulated gate bipolar transistor (IGBT) devices are a popular choice for low-power converters. Although IGBT power modules used in high-power applications have recently been studied in the literature, there are major knowledge gaps regarding reliability and lifetime estimation of discrete devices. In this paper, on-state collector–emitter voltage drop $(V_{{\rm{ce}},{\rm{on}}})$ variations are characterized for discrete IGBT devices exposed to cyclic thermal stresses. Variations in $V_{{\rm{ce}},{\rm{on}}}$ are carefully identified and classified depending on different aging mechanisms, stress levels, and device structures. A probabilistic framework for remaining useful lifetime (RUL) estimation based on the knowledge obtained by accelerated aging experiments for real-time RUL estimation has been proposed. Specifically, the proposed model uses Gaussian process regression (GPR) for applying a Bayesian inference (BI) on RUL estimation of the device under test. Using BI reduces the uncertainty associated with RUL estimation and leads to more accurate results. This concept is also tested by comparing the classical maximum-likelihood estimation and GPR estimation results with the ones obtained by accelerated aging tests.

Reliability of power converters is crucial for mission critical systems. Among the components that are susceptible to failure, power semiconductor devices are one of the major causes of the power converter failures. This paper focuses on the remaining useful lifetime (RUL) estimation of degraded power MOSFETs, which are stressed by thermal cycling. The relative change in on-state resistance is identified as the fault signature. A data-driven RUL estimation algorithm based on a linear approximation model is proposed. The empirical coefficients are estimated by the classical least squares, where the outliers are removed by random sample consensus (RANSAC) algorithm. A sliding window approach is used to track the nonlinearities. The window size, threshold value, and number of samples used by RANSAC are optimized with the genetic algorithm. The accuracy of the proposed RUL estimation tool is verified on a number of thermally aged discrete power MOSFET data.

Thermal/power cycles are widely acknowledged methods to accelerate the package related failures. Many studies have focused on one particular aging precursor at a time and continuously monitored it using custom-built circuits. Due to the difficulties in taking sensitive measurements, the reported findings are more on the quantities requiring less sensitive measurements. In this paper, two custom-designed testbeds are used to age a number of power MOSFETs and insulated gate bipolar transistors. An automated curve tracer is utilized to capture parametric variations in I – V curves, parasitic capacitances, and gate charges at certain time intervals. The results suggest that the only viable aging precursors are the on-state voltage drop/on-state resistance, body diode voltage drop, parasitic capacitances, and gate threshold voltage for die attach solder and gate-oxide degradation mechanisms. Based on the experimental results, gate threshold voltage variation is empirically modeled to estimate the remaining useful lifetime of the switches experiencing gate oxide degradation. The model parameters are found by the least squares method applied to inliers determined by the random sample and consensus outlier removal algorithm.

In LLC-based onboard battery charging architectures used in plug-in electric vehicles (PEV), the dc link voltage can be actively regulated to follow the battery pack voltage so that the LLC converter can operate in proximity of resonant frequency and achieve high efficiencies over the wide range of battery pack voltage. However, conventional boost-type power factor correction (PFC) converters are unable to provide ultrawide dc link voltages since their output voltages should always be larger than their input voltages. This paper proposes a Silicon Carbide (SiC)-based onboard PEV charger using single-ended primary-inductor converter (SEPIC) PFC converter followed by an isolated LLC resonant converter. With the proposed charger architecture, the SEPIC PFC converter is able to provide an ultrawide range for dc link voltage, and consequently enhance the efficiency of the LLC stage by ensuring operation in proximity of resonant frequency. A 1-kW SiC-based prototype is designed to validate the proposed idea. The experimental result shows that the SEPIC PFC converter achieves unity power factor, 2.72% total harmonic distortion, and 95.3% peak conversion efficiency. The LLC converter achieves 97.1% peak efficiency and always demonstrates a very high efficiency across the ultrawide dc-link voltage range. The overall efficiency of the charger is 88.5% to 93.5% from 20% of the rated load to full load.

The efforts for more reliable power conversion systems have been gaining momentum in recent years. The majority of the studies concerning reliability of power switches focus on the package-related failures, mainly caused by the cyclic thermal stress. The basic failure precursor for this type of stress has been identified as increased on-state resistance for power MOSFETs in the recent literature. On-state resistance monitoring during converter operation is a challenging and costly task as it requires current and voltage sensing circuits, which can block the high voltage across the switch during off-state to protect the measurement or control unit. This paper proposes a software frequency response analysis method to determine the health status of high-voltage power MOSFETs with high on-state resistance. This is achieved by analyzing and evaluating the variation in the plant model at double pole frequency using the same DSP that is used for control purposes. The proposed concept is analyzed for boost converter; however, it can be used to detect the on-state resistance variation in other types of converters operating in continuous condition mode (CCM). The proposed algorithm is embedded in a low cost DSP and experimentally verified on a dc/dc boost converter.

The research on noninvasive incipient fault diagnosis of power converters is very critical to avoid strenuous periodic checkups and costly interruptions. In many of the research studies, on-state resistance of power MOSFETs is identified as the fault precursor, and suggested to be monitored online for prognosis. In this paper, a condition monitoring algorithm is proposed for power MOSFETs of interleaved converters and integrated with the conventional current loops. The proposed technique utilizes on-state resistance information of the switches to adjust the current reference of each interleaving leg. In addition, a pulse-width adjustment method is proposed to avoid one current sensor and current-control loop. With the proposed scheme, the thermal stress on the aged device can be reduced, and the overall lifetime of the converter can be extended. The proposed approach is verified on two-leg interleaved converters both in simulation and experimentally.

The research on noninvasive incipient fault diagnosis of power converters is very critical to avoid strenuous periodic check-ups and costly interruptions. Thermal cycling is one of the main techniques to accelerate the package-related failure progress. In this paper, first, a custom designed accelerated aging platform that can expose multiple discrete power MOSFETs to thermal stress simultaneously is introduced. Based on the collected experimental data, the variation of the on -state resistance is identified as the failure precursor, and an exponential degradation model that fits successfully with the experimental data are developed. The remaining useful lifetime (RUL) of degraded power MOSFETs is estimated through classical least-squares algorithm run on experimental data filtered by Kalman Filter which deals with the measurement noise and model uncertainties. The essential advantage of the proposed method is that it does not require junction temperature information. The RUL estimation with limited field data is demonstrated on a number of experimental results.

This paper presents a new space vector pulsewidth modulation scheme to reconstruct phase currents using neutral-point current sensing in three-level T-type converters (TLTTCs). For this purpose, zero vector and offset vectors are replaced with complementary active vectors. These active vectors do not affect the resultant output voltage and the voltage balance at the neutral point of TLTTCs. Hence, the pulsewidths of corresponding active vectors can be adjusted even at low speeds without much additional switching losses and low-frequency noise in the inverter. The modified switching patterns can easily be generated without significant computational complexity. The proposed method is experimentally verified using Texas Instruments TMS320F28335 and Spartan 6 controllers, on a custom designed T-type converter based on Fuji IGBT modules.

Power electronics solutions based on multiple converter configurations offer cost-effective solutions by integrating a number of components at input or output power stages. This paper proposes a new multiinput isolated three-level converter for renewable and sustainable energy systems adopting high dc link voltage. Multiple dc sources are integrated to the three-level dc/dc converter before the isolation stage, resulting in reduced part-count, determining dc link voltage level and allowing flexibility in transformer design. The proposed architecture eliminates two boost switches which are present in the two-stage counterpart. The input inductors are operated in discontinuous conduction mode; thus, power can be shared between input sources through proper selection of input inductors. A low voltage prototype has been designed to serve as a proof of concept.

Multilevel converters have been well studied for high-voltage high-power renewable energy applications. Owing to the multibranch structure, these converters can be operated under fault conditions in case of a loss of a branch or voltage cell. In this regard, this paper proposes a new active fault-tolerant space vector pulsewidth modulation strategy for single-phase faults in three-phase multilevel converters. The proposed modulation strategy treats the multilevel converter as a two-level converter by introducing an offset vector. A generalized approach is proposed to search for the offset vector and to adjust the modulation of the converter online under different fault operation conditions. Several short- and open-circuit faults have been demonstrated on a seven-level hybrid input-switched converter to prove the effectiveness of the proposed fault-tolerant scheme.

A three-level (TL) bidirectional dc/dc converter is a suitable choice for power electronic systems with a high-voltage dc link, as the voltage stress on the switches is half and inductor current ripple frequency is twice the converter's switching frequency. This study proposes a zero-voltage transition (ZVT) TL dc/dc converter to enable operation with higher switching frequency in order to achieve higher power density and enhance efficiency. Two identical ZVT cells, each one composed of two resonant inductors, a capacitor, and an auxiliary switch, are integrated with the conventional TL topology to enable soft switching in all four switches in both buck and boost operation modes. In addition, a variable dead-time control is proposed to increase the effective duty ratio at heavy loads. The proposed soft-switching feature has been demonstrated under different loading conditions. A 650-W prototype is designed and fabricated, which exhibits 95.5% at full load.

In battery/ultracapacitor electric vehicles, a bidirectional dc/dc converter is employed to process the power according to the power references obtained from the energy management controller. The selection of this converter is of critical importance for the overall system efficiency and size. This study proposes using a three-level dc/dc converter and provides a comprehensive comparison with the conventional two-level and interleaved bidirectional buck/boost converters in terms of magnetic component size/weight and overall efficiency. Unlike the comparative studies presented in the literature, where the efficiency comparison of converters is conducted based on given fixed input and output parameters, power references obtained from a wavelet-transform-based energy management strategy with varying energy source voltages and traction power are considered in this paper. The results of the analyses show that a three-level converter exhibits higher overall efficiency and has smaller size inductor. A 1-kW bidirectional three-level dc/dc converter is designed as a proof of concept, which exhibits 93.2% peak efficiency at 200-kHz switching frequency.

For low-cost isolated ac/dc power converters adopting high-voltage dc-link, research efforts focus on single-stage multilevel topologies. This paper proposes a new single-stage three-level isolated ac/dc PFC converter for high dc-link voltage low-power applications, achieved through an effective integration of ac/dc and dc/dc stages, where all of the switches are shared between two operations. With the proposed converter and switching scheme, input current shaping and output voltage regulation can be achieved simultaneously without introducing additional switches or switching actions. In addition, the middle two switches are turned on under zero current in discontinuous conduction mode operation, and the upper and bottom switches are turned on under zero voltage. Due to the flexible dc-link voltage structure, high power factor can be achieved at high line voltage. A 500 W/48 V prototype is designed to serve as the proof of concept, which exhibits 90.8% peak efficiency at low input line voltage.

Negative rail current sensing with the conventional space vector pulsewidth modulation (SVPWM) scheme imposes several challenges, particularly at low speeds and sector boundaries, where the pulsewidths of active vectors become narrow while the dc negative rail current becomes zero in null vectors (111) or (000). This paper presents a new SVPWM scheme by replacing null vectors with complementary active vectors such that the added vectors effectively cancel out each other, and the applied resultant voltage remains the same as in the conventional SVPWM. Hence, the pulsewidths of active vectors can be increased at low speeds without introducing additional switching losses, adding switching complexity, or introducing low frequency noise to the waveforms. Moreover, the proposed scheme reduces the system error caused by the deadtime of the switches with enlarged pulsewidths, enabling low-speed drive. The proposed technique is experimentally verified using a TMS320F28035 (Piccolo) microcontroller.

This paper proposes a new space vector pulsewidth modulation (SVPWM) strategy for a hybrid input switched multilevel converter for photovoltaic energy generation systems. The converter topology is a cascaded connection of input switched and H-bridge converters, which can provide 2N + 1 voltage levels for each phase. The proposed SVPWM strategy treats the multilevel converter as a two-level converter by introducing an offset vector. With a generated switching pattern, it is possible to obtain minimum number of switching-state transitions and switch the H-bridge close to line frequency; thus, the switching losses can be significantly reduced. The proposed SVPWM strategy has been realized on a seven-level converter to demonstrate the principle of operation. The advantages of the proposed scheme and architecture are verified by both simulation and experimental results.

Stringent requirements on higher power density and efficiency for power electronics converters in applications such as server/telecom power systems and industrial motor drives necessitate transformative changes in power electronic architecture as well as replacement of Si based FETs with wide bandgap devices. For power-factor-correction (PFC) circuits, the path for greater power density necessitates the transition from Si based dual-boost to GaN based totem pole (TP) structure, which enables designers to reach over 99% efficiency at twice the power density of Si based converters. This paper compares GaN based TP PFC with conventional Si based topologies, and details design steps for above 99% efficiency and 155W/in3 power density in the switching network.

The demand for more reliable power conversion is ever increasing. This necessitates smart gate drivers or smart system controllers that monitor the components that are susceptible to failure. Together with the electrolytic capacitors, power semiconductor devices are among the weakest components in a power converter. In an effort to predict power MOSFET aging, this paper proposes an remaining useful lifetime (RUL) estimation algorithm for degraded power MOSFETs, which are exposed to high amplitude thermal cycles. The relative change in on-state resistance is identified as the fault signature. A data-driven RUL estimation algorithm based on a linear model approximation is proposed. The outliers present particularly in the beginning part of the data decrease the accuracy of the estimation with classical least-squares method. In this paper, a Bayesian Interference estimator is proposed to improve the accuracy through incorporating prior knowledge to estimation. The accuracy of the proposed RUL estimation tool is verified on the collected experimental data of thermally aged discrete power MOSFETs.

In this paper, a variable dc link technique is proposed to track the maximum efficiency point of the $LLC$ converter for plug-in electric vehicle battery-charging applications over a wide battery state-of-charge (SOC) range. With the proposed variable dc link control approach, the dc link voltage follows the battery pack voltage. The operating point of the $LLC$ converter is always constrained to the proximity of the primary resonant frequency so that the circulating current in the magnetizing inductor and the turning-off currents of MOSFETs are minimized. In comparison with conventional approaches, the proposed variable dc link voltage methodology demonstrates efficiency improvement across the wide SOC range. Efficiency improvements of 2.1% at the heaviest load condition and 9.1% at the lightest load condition are demonstrated.

Electric vehicle (EV) batteries tend to have accelerated degradation due to high peak power and harsh charging/ discharging cycles during acceleration and deceleration periods, particularly in Urban driving conditions. Oversized energy storage system (ESS) meets the high power demand; however, in tradeoff with increased ESS size, volume, and cost. In order to reduce overall ESS size and extend battery cycle life, battery/ultracapacitor (UC) hybrid ESS (HESS) has been considered as a solution in which UCs act as a power buffer to charging/discharging peak power. In this paper, a multiobjective optimization problem is formulated to minimize the overall ESS size, while maximizing the battery cycle life according to the assigned penalty functions. An integrated framework for HESS sizing and battery cycle life optimization applied in a midsize EV, using an Autonomie simulation model, is described and illustrated in this paper. This multidimensional optimization is realized by a sample-based global search oriented DIviding RECTangles (DIRECT) algorithm. The optimization results under Urban Dynamometer Driving Schedule (UDDS) are compared with the battery-only ESS results, which demonstrate significant battery cycle life extension of 76% achieved by the optimized HESS with 72 UC cells.

The interleaved PFC topologies have been widely used since they allow for smaller components, improved thermal performance, better transients, and reduced current ripple. In this letter, conventional two-phase interleaved universal input PFC topology is modified to obtain dual independent outputs for server applications, which minimizes the transient effects of interleaving legs on each other through two split dc buses. A new digital control method using only one current sensor located on the negative dc rail is proposed to control the dual-output interleaved PFC converter. Double-loop digital control of two interleaving stages is implemented using a single low-cost microcontroller (TMS320F28027-PiccoloA). In the proposed control technique, the control circuitry, input voltage, and current sensing circuits are shared between two PFC power stages, which minimize the size and the cost of the design significantly.

Electrification of performance vehicles brings several challenges, such as the necessity of high-power sources, which can satisfy the power requirements during acceleration and efficiently retrieve energy during deceleration without performance and life cycle deterioration of such sources. In addition, the limited space under the hood for these vehicles eliminates the possibility of utilizing large volume high-power propulsion machines. This paper proposes a fuzzy logic supervisory wavelet-transform frequency decoupling-based energy management strategy implemented on a new powertrain deploying two propulsion machines rated at different powers with a hybrid battery/ultracapacitor (UC) energy storage system (ESS). The proposed control and energy management strategy guarantees that battery and UC provide the base and transient-free powers, respectively, while state of charge (SOC) of UC is maintained at an optimal value. The torque demand is split among the propulsion machines by solving the formulated unconstrained optimization problem. With the proposed hybrid ESS and energy/power decoupling strategy, power density of the ESS can be increased, vehicle performance can be improved, and battery lifetime can be prolonged.

In this paper, a two-stage onboard battery charger is analyzed for plug-in electric vehicles (PEVs). An interleaved boost topology is employed in the first stage for power factor correction (PFC) and to reduce total harmonic distortion (THD). In the second stage, a full-bridge LLC-based multiresonant converter is adopted for galvanic isolation and dc/dc conversion. Design considerations are discussed, focusing on reducing the charger volume and optimizing the conversion efficiency over the wide battery-pack voltage range. A detailed design procedure is provided for a 1-kW prototype, charging the battery with an output voltage range of 320–420 V from 110-V 60-Hz single-phase grid. Experimental results show that the first-stage PFC converter achieves THD of less than 4% and a power factor higher than 0.99, and the second-stage LLC converter operates with 95.4% peak efficiency and good overall efficiency over wide output voltage ranges.

The current research trend to increase the power density of power electronics interfaces in automotive applications is the cost-effective integration of power converters. This paper proposes a reduced-part integrated power electronics interface that is capable of charging the battery and adjusting the voltage levels of a battery and a dc link during propulsion and regenerative braking. In the proposed topology, one inductor is shared between a dc/dc converter and a charger, eliminating the need for an additional magnetic component for the charging stage. A charge nonlinear-carrier control (NLC) method, which reduces the feedback circuitry, is adopted, and different nonlinear reference voltage waveforms are generated for each half-cycle of the grid to ensure a unity power factor and stable operation. To verify the concept, a 750-W prototype has been built and tested for each operation mode.

The basic power electronic interfaces rendering volume and weight of electric and plug-in hybrid electric vehicles are an inverter, an on-board charger, and a bidirectional dc/dc converter. This paper proposes an innovative integrated bidirectional converter with a single-stage on-board charger to reduce the number of switches, size, and weight of the power electronic interfaces. The analyses show that 266 cm 3 and 1.1 kg can be saved due to the elimination of the inductor core used for power factor correction in charging mode, in addition to the reduction achieved through removal of inductor winding, power switches, diodes, and additional heat sink of the conventional structures. A proof-of-concept prototype with power limits of 8.4 kW in charging and 20 kW in propulsion modes has been designed and validated at various power levels. The peak efficiencies for propulsion and regenerative braking operations are measured as 96.6% and 94.1%, respectively. The power factor is recorded as 0.995 at 1.8 kW charging power, where crest factor and peak efficiency are recorded as 1.49 and 91.6%, respectively.

Identification of power device failure precursors is essential for condition monitoring, fault severity assessment and lifetime estimation. These tools constitute the fundamental elements to achieve highly reliable power converters with self-diagnosis capability, which can report incipient faults at very early stage. In this paper, several discrete IGBTs are thermally aged on a custom-built modular test-bed. I-V characteristics are monitored periodically using an automated curve tracer throughout the aging, and the fault/aging related patterns are comprehensively analyzed. The variations in saturation voltage, gate threshold voltage, transfer capacitances, and gate charge, which are the potential candidates for aging precursors, are analyzed in detail. The experimental and failure analysis results suggest that on-state voltage drop and gate threshold voltage are the two essential aging precursors for monitoring die-attach solder and gate oxide degradations.

Discrete package Insulated Gate Bipolar Transistor (IGBT) devices are a popular choice for low-medium power converters. Although IGBT power modules have been extensively studied in literature, there exists a major gap for reliability study particularly for discrete devices. Current failure diagnostic tools are not mature enough for failure diagnosis and prognosis in real-time operation based on system condition monitoring. In order to move power conversion technologies forward reliably, this paper investigates the changes in on-state collector-emitter voltage drop (V ce , on ) of discrete IGBT devices exposed to thermal cyclic stress. Depending on the dominant aging mechanisms and device structure, V ce , on variation trend is different. In this paper, V ce , on variations of three different IGBT device types, namely, punch through, non-punch through and field stop, are continuously monitored during accelerated aging tests, and their relations to aging mechanisms are identified.

This paper focuses on the remaining useful lifetime (RUL) estimation of power MOSFETs, which are stressed by thermal cycling. The relative change in on-state resistance is identified as the aging precursor for die attach solder degradation after exhaustive experiments. A data-driven RUL estimation algorithm based on a linear approximation model is proposed. The empirical coefficients are estimated by the classical least squares method. However, the initial part of the data contains a significant number of outliers, which decreases the estimation accuracy. In order to remove the outlier effect and make the estimation robust, least-squares method is applied to only inliers that are determined by random sample consensus (RANSAC) algorithm. With the exclusion of outliers, the RUL estimation is improved for the ones that contain outliers. The accuracy of the proposed RUL estimation tool is verified on a number of thermally aged discrete power MOSFET data.

The recent advances and reports on failure precursors of power switches have led to estimation of lifetime as well as developing secondary control schemes to increase the lifetime of the converters. In this study, a secondary control scheme to extend the lifetime of the converter based on the identified failure precursors such as the on-state resistance variation for power MOSFETs and collector emitter voltage variation for IGBTs is proposed for three-phase converters. The controller switches the modulation scheme from SVPWM to discontinuous PWM, and adjusts the switching frequency, once the tracked failure precursor reaches to the defined threshold value. The tradeoff between the total harmonic distortion and lifetime extension at different modulation techniques and switching frequencies are addressed.

The efforts on more reliable power conversion systems are gaining momentum in the recent years. Majority of the studies concerning reliability of power switches focus on the package related failures, mainly caused by the thermal stress. The basic failure precursor for this type of stress has been identified as increased on-state resistance for power MOSFETs in recent literature. However, calculation of on-state resistance requires a voltage sensing circuit which can block the high voltage across the switch during off-state not to damage the measurement or control unit. This also limits the implementation as it requires additional hardware. This paper proposes a software frequency response analyzing algorithm to determine the health status of the power MOSFETs through evaluating the variation in the plant model using the same DSP that is used for control purposes. The proposed concept has been analyzed for basic single-switch converters, and experimentally verified on a dc/dc boost converter.

Thermal/power cycles are widely acknowledged methods to accelerate the package related extrinsic failures. Many studies have focused on particular failure precursor at a time and continuously monitored it using custom-built circuits. Due to the difficulties in taking sensitive measurements, the reported findings are more on the quantities requiring less sensitive measurements such as on-state resistance. In this paper, a custom-designed test bed is used to age a number of power MOSFETs and an automated curve tracer is utilized to capture parametric variations in I–V curves, transfer capacitances and gate charges at certain time intervals throughout the aging. The results suggest that the failure precursors which exhibit continuously increasing trend are the on-state resistance, body diode voltage drop, parasitic capacitances and threshold voltage. Based on the results, an exponential empirical model for the gate threshold voltage that fits successfully with the experimental data is proposed. Furthermore, Kalman Filter is employed to filter out the measurement noise and model uncertainties, which is also used to estimate the remaining useful lifetime of the degraded switches.

The impending global energy crisis has opened up new opportunities for the automotive industry to meet the ever-increasing demand for cleaner and fuel-efficient vehicles. This has necessitated the development of drivetrains that are either fully or partially electrified in the form of electric and plug-in hybrid electric vehicles (EVs and HEVs), respectively, which are collectively addressed as plug-in EVs (PEVs). PEVs in general are equipped with larger on-board storage and power electronics for charging or discharging the battery, in comparison with HEVs. The extent to which PEVs are adopted significantly depends on the nature of the charging solution utilized. In this paper, a comprehensive topological survey of the currently available PEV charging solutions is presented. PEV chargers based on the nature of charging (conductive or inductive), stages of conversion (integrated single stage or two stages), power level (level 1, 2, or 3), and type of semiconductor devices utilized (silicon, silicon carbide, or gallium nitride) are thoroughly reviewed in this paper.

Lately, interest in renewable sources, especially wind and solar energy, has shown a significant increase in all over the world that mostly depends on climate-threatening conventional fossil fuels. Besides, hybrid use of these power sources with suitable back-up units provides many advantages compared to sole use of these sources. In this regard, a hybrid system consisting of a wind turbine for utilizing the wind energy, photovoltaic panels for solar energy, fuel cell for providing back-up power and a battery unit for storing the possible excess energy production and supplying the transient load is considered in this study. Experimental assessment of this system in different case studies including the real time measured dynamic power demand of an office block is realized. The collaborative actions of the proposed hybrid system with a fuzzy logic based energy management strategy during fluctuations of renewable-based power production are investigated. Thus, results of this study may be valuable for evaluating the feasibility of stand-alone hybrid renewable energy units for future power systems.

An energy storage system with sufficient power capacity should be incorporated with fuel cells (FCs) to compensate the slow dynamics of FCs. Ultra-capacitors (UCs) are potential candidates for a solution in this aspect. A test bench of such an FC/UC hybrid configuration that can emulate the dynamics of vehicular systems is presented in this paper. Namely, the test bench performance verification of wavelet transform and fuzzy logic based energy management strategy that was discussed in earlier simulation-based studies of the authors is investigated. Of equal importance is the comparison of the cascade wavelet-fuzzy logic based strategy with the case of using only fuzzy logic in the energy management is presented. Experimental results with small-scale devices, a PEMFC (5 kW, 48 V) manufactured by Plug Power (R) Company, and a UC bank composed of 430 F, 16 V and 165 F, 48 V UC modules manufactured by Maxwell Technologies (R) Company, illustrate the successful performance analysis of employed energy management schemes during similar motor cycles. (C) 2010 Professor T. Nejat Veziroglu. Published by Elsevier Ltd. All rights reserved.

The research on non-invasive incipient fault diagnosis of power converters is very critical to avoid strenuous periodic check-ups and costly interruptions. In many of the research studies, on-state resistance of power MOSFETs is identified as the fault precursor, and suggested to be monitored online for prognosis. In this paper, a condition monitoring algorithm is proposed for power MOSFETs of interleaved converters and integrated with the conventional current loops. The proposed technique utilizes on-state resistance information of the switches to adjust the current reference of each interleaving leg. Thus, the thermal stress on the aged device can be reduced and the overall lifetime of the converter can be extended. The proposed approach is verified on two-leg interleaved dc/dc and ac/dc converters.

Power semiconductor devices are the major cause of the power converter failures together with the electrolytic dc bus capacitors. In harsh operating environments, the power devices are subjected to various mechanical and electrical stresses, wear, and vibration that contribute to increased equipment failure rate, where a failed component can cause unexpected interruptions, serious safety issues, or easily account for millions of dollars in repair costs. Developing prognosis tools is vital for the reliability of these systems. This paper focuses on the remaining useful lifetime (RUL) estimation of degraded power MOSFETs which are stressed by thermal cycling. The relative change in on-state resistance is identified as the fault signature. A multiple device ageing platform is designed and built to collect experimental data. An exponential degradation model that fits successfully with the experimental data is developed. The experimental data is processed with Kalman Filter, and RUL estimation with limited field data is demonstrated.

Thermal cycling is one of the main techniques to accelerate the package related failure progress. In this paper, a custom designed accelerated ageing platform that can expose multiple discrete power MOSFETs to thermal stress simultaneously, is introduced. Active heating, without using external loads, is used to increase the junction temperatures of the devices from a single current source, where temperature swing for each device can be controlled independently. The issues during the measurements such as high off-state drain- to-source voltage, and transients during turning on instants are addressed. The variation of the on-state resistance is identified as the failure precursor. It is observed that on-state resistance increases by 10%–17% of its initial value before it completely fails. Based on the collected field data, an exponential degradation model that fits successfully with the experimental data is developed.

This paper proposes a new multi-input isolated three-level converter for renewable and sustainable energy systems. Multiple dc sources are integrated to the three-level dc/dc converter, resulting in reduced part-count and allowing flexibility in transformer design and dc link voltage selection. The proposed architecture eliminates two boost switches which are present in the two-stage counterpart, and enables utilizing low voltage switches. The input inductors are operated in DCM sharing the same duty cycle. Thus, power can be shared between input sources with proper selection of input inductors. A low voltage prototype has been designed to serve as a proof of concept.

This paper presents a new space vector pulse width modulation(SVPWM) scheme to reconstruct phase currents using neutral point current sensing in three level T-type converters. For this purpose, zero vectors and offset vectors are replaced with complementary active vectors. These active vectors do not affect the resultant output voltage and the voltage balance at the neutral point of three-level T-type converters. Hence, the pulse widths of corresponding active vectors can be adjusted even at low speeds without additional switching losses and low frequency noise in the inverter. The modified switching patterns can easily be created without significant computational complexity. The proposed method is experimentally verified using Fuji T type IGBT modules, Texas Instruments TMS320F28335 and Spartan 6 systems.

This paper proposes a new vector based dead time compensation method for a three-level T-type converter. The origin of the dead time voltage error is analyzed in detail under different switch commutation processes and load conditions. Based on the dead time voltage error for each phase, an error voltage vector is defined to indicate the effect of the dead time on the reference voltage vector from vector synthesis point of view. To cancel the dead time error voltage vector, the reference voltage vector is adjusted accordingly based on load current directions. Different from the studies presented in literature, the operation of the proposed dead time compensation method can be extended to over modulation region. The effectiveness and the advantages of the proposed vector based dead time compensation method are verified by both simulation and experimental results.

Fault tolerant and survivable operation schemes for multi-level converters, that interface the grid and critical loads, have been gathering attention for enhanced reliability. In case short-circuit or open-circuit faults occur in one or multiple voltage cells, the space vector pulse width modulation (SVPWM) control algorithm has to be modified according to the available voltage vectors for survivable operation. This paper proposes a new fault tolerant SVPWM strategy based on offset vector insertion, which allows controlling the multilevel converter as a two-level converter. A robust offset vector locating algorithm, which finds the feasible offset vector in case of short-circuit and open-circuit conditions, is presented. A single voltage cell short circuit fault is demonstrated on a seven-level hybrid input-switched multi-level converter to prove the effectiveness of the proposed survivable scheme.

The selection of a bidirectional non-isolated dc-dc converter interfacing the battery and ultracapacitor (UC) in electric vehicles (EVs) is of critical importance for the overall system efficiency. Generally, efficiency comparison of converters is conducted based on given fixed input and output parameters. Such a comparison may not provide fair results for EV applications since energy source voltages and traction power vary dynamically depending on the driving conditions. This paper provides a comprehensive efficiency comparison of three-level, two-level and interleaved bidirectional buck/boost converters through developed loss models considering the dynamic variables in a drive cycle. The results of the analyses show that three-level converter exhibits higher overall efficiency. A 1kW prototype has been designed and developed to serve as a proof of concept.

To reduce the cost of the conventional two-stage power factor correction (PFC) converters, single-stage PFC (SSPFC) converters have been studied in literature. Most commonly, the SSPFC converters are operated at DCM mode due to the simplicity of the control, non-existence of the reverse recovery losses. For ac/dc converters supporting universal input voltage range, DCM operation with relatively low dc link voltage results in highly distorted input current. In multi-level SSPFC converters, the dc link voltage can be adjusted in a larger window between 400V-800V thanks to the reduced voltage stresses on the switches. Thus, with an integrated controller adjusting dc link voltage with respect to line voltage, power factor at high line voltage can be improved. However, in DCM mode, the efficiency of the converter slightly decreases at high dc link voltage. In this paper, the tradeoff between the efficiency and the input factor is analyzed in a new integrated three-level PFC converter.

In this paper, a plug-in electric vehicle battery charger is proposed based on SEPIC PFC and LLC topologies. In addition, a new approach in introduced to actively control the dc link voltage and track the maximum efficiency point of a LLC converter over the wide voltage range of the high voltage battery pack. Comprehensive circuit modeling and loss analysis at maximum efficiency point of LLC converter are carried out. A 3.3 kW charger, charging the Li-ion battery with an output voltage range of 100 V to 420 V from variable dc link voltage, is designed and simulated. In comparison to conventional approaches, the LLC stage demonstrates 4.4% efficiency improvement at the heaviest load condition and 16.5% efficiency improvement in the lightest load condition.