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In the process of the optical interconnection module soldering assembly, the mismatch of the thermal expansion coefficient between the substrate and printed circuit board would result in the production of alignment offset between light source devices and light-coupled devices, which would lead to light power loss. It is of great significance to study the optical interconnect module alignment offset in the assembly process to improve the optical interconnect module coupling efficiency. In this paper, an optical interconnection module key position postsoldering shift offset measurement system was established, and an optical interconnection module experimental sample was prepared. The key position postsoldering shift in the $x$ - and $y$ -directions was measured. The 3-D finite-element analysis model of a typical optical interconnect module was established, and postsoldering shift offsets were calculated after the finite-element analysis of the optical interconnect module under reflow soldering temperature load. The coupling efficiency simulation model of the optical interconnection module was established using the ZEMAX software, and the coupling efficiency was calculated according to the alignment offset measured in the experiment. The results revealed the following: the postsoldering alignment offsets in the $x$ - and $y$ - directions were 0.316 and 0.422 $\mu \text{m}$ , respectively, and the synthetic alignment offset was $0.527~\mu \text{m}$ . The postsoldering alignment offset calculated using the finite-element simulation model was $0.436~\mu \text{m}$ , and its error was 17.2%, when compared with the measured value. The coupling efficiency of the optical interconnection module was 85.804% when the postsoldering alignment offset was $0.527~\mu \text{m}$ .

The 3D finite element analysis model of flip stacked AU bumps was developed, its stress and strain distribution under random vibration load were analyzed by ANSYS the finite element analysis software. Solder joint height, solder maximum radial size, solider distribution were selected as four key configuration parameters, their impacts on the models' stress and strain distribution were also studied, the results showed that: under random vibration load, the bumps array maximum stress and strain appeared on the farthest position away from the center of the array of bumps, with the increase of the bump height/diameter in distribution, the maximum stress and strain decrease gradually.

The simulation model of embedded capacitor radiation was established based on HFSS (High Frequency Simulator Structure) software in this paper. Radiation problem of the embedded capacitor at high frequency was studied by the model. Its near-field radiant power gain was obtained and the effects of the variations of the signal frequency, capacitance plate radius and dielectric thickness on radiation power gain were analyzed. The analysis results are shown as follows:near-field radiation power gain of embedded capacitor changes accordingly with the change of the signal frequency; within a certain range of electrode plate radius, radiation power increases with the increase of electrode plate radius; and in a certain range of dielectric thickness, near-field radiation power decreases with the increase of dielectric thickness.

The 3D finite element analysis model of chip scale package solder joints with compliant layer was established, the thermal-structure finite element analysis of the model was performed, the stress and strain distribution of the solder joints with complaint layer was obtained under the condition of thermal-structure, the influences of the height of solder joints with complaint layer structure were studied. Results shows that the compliant layer structure can reduce the stress and strain of solder joints effectively. With the increase height of solder joints with complaint layer, the maximum stress and strain of the solder joints decrease.