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Extensive research efforts are being carried out to evaluate and improve the reliability of computing devices, either through beam experiments or simulation-based fault injection. Unfortunately, it is still largely unclear to which extend fault injection can provide an accurate error rate estimation at early stages and if beam experiments can be used to identify the weakest resources in a device. The challenges associated with reliability evaluation grow with the increase of complexity of the hardware and the software. In this paper, we combine and analyze data gathered with extensive beam experiments (on the final physical CPU hardware) and microarchitectural fault injections (on early microarchitectural CPU models). We target a standalone Arm Cortex-A5 and an Arm Cortex-A9 integrated in an SoC and evaluate their reliability in bare-metal and Linux-based configurations. We find that both the SoC integration and the OS presence increase the system DUEs (Detected Unrecoverable Errors) rate (for different reasons) but do not significantly impact the SDCs (Silent Data Corruptions) rate which is solely attributed to the CPU core. Our reliability analysis demonstrates that, even considering SoC integration and OS inclusion, early, pre-silicon microarchitecture-level fault injection delivers accurate SDC rates estimations and lower bounds for the DUE rates.

As the safety-critical applications (e.g. automotive and medical electronics) emerge, various techniques of radiation hardening by design (RHBD) are proposed to deal with soft errors. Among all RHBD techniques, Built-In Soft-Error Resilience (BISER) is the first one to apply the delayed latching to separate input signals on all flip-flops for error detection. However, the delay values induced by BISER extend the setup time of all flip-flops, and may fail to meet the timing specification of the design. For minimizing such delay impact on the setup time of each flip-flop, we propose the Automated Latching-Delay Assignment (ALDA) to transfer partial values to the CK-Q delay. Later, Time-Borrowable D-Flip-Flop (TBD-FF) as well as a modified design flow is also proposed to realize the delay assignment by ALDA and to complete the design hardening. Experiments show that ALDA together with TBD-FF effectively protects four benchmark circuits against soft errors, and optimally avoids the timing violations caused by the prior delayed-latching solutions.

Deep neural networks (DNNs) are being incorporated in resource-constrained IoT devices, which typically rely on reduced memory footprint and low-performance processors. While DNNs’ precision and performance can vary and are essential, it is also vital to deploy trained models that provide high reliability at low cost. To achieve an unyielding reliability and safety level, it is imperative to provide electronic computing systems with appropriate mechanisms to tackle soft errors. This paper, therefore, investigates the relationship between soft errors and model accuracy. In this regard, an extensive soft error assessment of the MobileNet model is conducted considering precision bitwidth variations (2, 4, and 8 bits) running on an Arm Cortex-M processor. In addition, this work promotes the use of a register allocation technique (RAT) that allocates the critical DNN function/layer to a pool of specific general-purpose processor registers. Results obtained from more than 4.5 million fault injections show that RAT gives the best relative performance, memory utilization, and soft error reliability trade-offs w.r.t. a more traditional replication-based approach. Results also show that the MobileNet soft error reliability varies depending on the precision bitwidth of its convolutional layers.

In advanced technology nodes, SRAM cells, used in the aerospace industry, have become highly susceptible to soft-error. In this brief, a Soft-Error-Aware Read-Decoupled 14T (SAR14T) SRAM cell is proposed for aerospace applications. To assess the performance of the proposed cell, it is compared with other soft-error-aware SRAM cells, like WE-QUATRO, QUCCE12T, RHD12T, RSP14T and RHBD14T. Simulation results show that all the sensitive nodes of SAR14T can reattain their initial states after being impacted by soft-error. Furthermore, the cell is capable of recovering from multi-node upset induced at its internal node-pair. Due to the employment of the read-decoupling technique, SAR14T shows the highest read stability compared to its peers. The proposed cell also proves to be the superior SRAM in terms of write ability and write delay. All these improvements are accomplished at the expense of a slightly longer read delay.

High-energy particles in the space can easily cause soft error in register file (RF). As a critical structure in a processor, RF often stores data for long periods of time and is read frequently, resulting in a higher probability of spreading corrupted data to other parts of the processor. The triple modular redundancy (TMR) is a common and effective fault tolerance method that enables multi-bit error correction. Designing full TMR for all the registers could cause excessive area and power overheads. However, some registers in RF have less impact on processor reliability. Therefore, there is no need to design TMR for them. This paper designs an efficient strategy which can rate the registers in RF based on their vulnerability. Based on the proposed strategy, a new RF fault tolerance method named Partial-TMR formulates in this paper, which selectively protects more vulnerable registers against multi-bit error, and improves fault tolerance efficiency. For integer RF, Partial-TMR improves its soft error correction capability by 24.5% relative to the baseline system and 3% relative to ParShield, while for floating-point RF, the improvement comes to 5.17% and 0.58% respectively. The soft error correction capability of Partial-TMR is slightly lower than that of full TMR by 1% to 3%, but Partial-TMR significantly cuts the area and power overheads. Compared with full TMR, Partial-TMR decreases the area and power overheads by 71.6% and 64.9%, respectively. It also has little impact on the performance. Partial-TMR is a more cost-effective fault tolerance method compared with ParShield and full TMR.

Safety-critical embedded systems may either use specialized hardware or rely on Software-Implemented Hardware Fault Tolerance (SIHFT) to meet soft error resilience requirements. SIHFT has the advantage that it can be used with low-cost, off-the-shelf components such as standard Micro-Controller Units. For this, SIHFT methods apply redundancy in software computation and special checker codes to detect transient errors, so called soft errors, that either corrupt the data flow or the control flow of the software and may lead to Silent Data Corruption (SDC). So far, this is done by applying separate SIHFT methods for the data and control flow protection, which leads to large overheads in computation time. This work in contrast presents REPAIR, a method that exploits the checks of the SIHFT data flow protection to also detect control flow errors as well, thereby, yielding higher SDC resilience with less computational overhead. For this, the data flow protection methods entail duplicating the computation with subsequent checks placed strategically throughout the program. These checks assure that the two redundant computation paths, which work on two different parts of the register file, yield the same result. By updating the pairing between the registers used in the primary computation path and the registers in the duplicated computation path using the REPAIR method, these checks also fail with high coverage when a control flow error, which leads to an illegal jumps, occurs. Extensive RTL fault injection simulations are carried out to accurately quantify soft error resilience while evaluating Mibench programs along with an embedded case-study running on an OpenRISC processor. Our method performs slightly better on average in terms of soft error resilience compared to the best state-of-the-art method but requiring significantly lower overheads. These results show that REPAIR is a valuable addition to the set of known SIHFT methods.

The wide use of GPUs for general-purpose computations as well as graphics programs makes soft errors a critical concern. Evaluating the soft error vulnerability of GPGPU programs and employing efficient fault tolerance techniques for more reliable execution become more important. Protecting only the most error-sensitive program regions maintains an acceptable reliability level by eliminating the large performance overheads due to redundant operations. Therefore, fine-grained regional soft error vulnerability analysis is crucial for the systems targeting both performance and reliability. In this work, we present a regional fault injection framework and perform a detailed error propagation analysis to evaluate the soft error vulnerability of GPGPU applications. We evaluate both intra-kernel and inter-kernel vulnerabilities for a set of programs and quantify the severity of the data corruptions by considering metrics other than SDC rates. Our experimental study demonstrates that the code regions inside GPGPU programs exhibit different characteristics in terms of soft error vulnerability and the soft errors corrupting the variables propagate into the program output in several ways. We present the potential impact of our analysis by discussing the usage scenarios after we compile our observations acquired from our empirical work.

CMOS circuits based on scaled transistors are typically more susceptible to soft errors caused by energetic particles in the radiation environment than circuits employing their large-area counterparts. In this paper, a soft error tolerant latch built on a Schmitt trigger, which is entirely realized with NMOS transistors with an additional voltage booster, which we refer to as NST-VB, is proposed. To evaluate the circuits’ radiation resilience, we identify the most sensitive nodes by analyzing the critical charges at the various latches’ internal sensitive nodes. We also examine the linear energy transfer (LET) of the essential latches and observe that the NST-VB latch has an improved LET of $$0.386~\mathrm {MeV~cm^2/mg}$$ as compared to $$0.231~\mathrm {MeV~cm^2/mg}$$ and $$0.365~\mathrm {MeV~cm^2/mg}$$ for unhardened latch and ST latch, respectively. For the process variation analysis, we further examined 5k Monte Carlo simulations to analyze the impact of device variability on our design and observe that the proposed NST-VB latch has $$1.96\times $$ less variability critical voltage concerning the ST latch. Further, the logic flipping probability for NST-VB latch is 48.32% compared to 53.04% for ST latch. Also, the critical charge to power delay area product ratio (QPAR) is calculated and evaluated for the proposed latch’s effectiveness compared to other considered latches.

International audience; To meet the requirements of both costeffectiveness and high reliability for low-orbit aerospace applications, this paper first presents a radiation hardened latch design, namely HLCRT. The latch mainly consists of a single-node-upset self-recoverable cell, a 3input C-element, and an inverter. If any two inputs of the C-element suffer from a double-node-upset (DNU), or if one node inside the cell together with another node outside the cell suffer from a DNU, the latch still has a correct value on its output node, i.e., the latch is effectively DNU hardened. Based on the latch, this paper also presents a flip-flop, namely HLCRT-FF that can tolerate SNUs and DNUs. Simulation results demonstrate the SNU/DNU tolerance capability of the proposed HLCRT latch and HLCRT-FF. Moreover, due to the use of a few transistors, clock gating technologies, and high-speed paths, the proposed HLCRT latch and HLCRT-FF approximately save 61% and 92% of delay, 45% and 55% of power, 28% and 28% of area, and 84% and 97% of delay-power-area product on average, compared to state-of-the-art DNU hardened latch/flip-flop designs, respectively.

With aggressive scaling of transistor size and supply voltage, the critical charge of the sensitive nodes is reducing rapidly. As a result, when these deep submicron devices are used in memory cells in the space environment, single-event upsets (SEUs), also known as soft-errors, pose a great threat to the reliability of the cells. To mitigate the effects of SEUs, we propose a soft-error-immune read-stability-improved (SIRI) SRAM cell. To assess the performance of the proposed cell, it is compared with other soft-error-immune SRAM cells, namely, QUCCE12T, WE-QUATRO, RHPD12T, RHBD14T and RSP14T. Simulation results confirm that the detrimental effects of SEUs do not alter the state of SIRI as all the sensitive nodes can reattain their initial states after being impacted by an SEU. The cell can also recover from single-event multi-node upsets (SEMNUs) that occur at its storage node-pair. Moreover, the storage nodes of the proposed cell are isolated from the bitlines during read operation. Hence, it exhibits the highest read stability. The write ability and write delay of SIRI are also superior to those of the majority of the comparison cells, and it consumes much lower hold power than many of the conventional SRAM cells. All these improvements are brought about only at the expense of a slightly longer read delay.

Computational capabilities of the largest high performance computing systems have increased by more than 100 folds in the last 10 years and keep increasing substantially every year. This increase is made possible mostly by multi-core technology besides the increase in clock speed of CPUs. Nowadays, there are systems with more than 100 thousand cores installed and available for processing simultaneously. Computational simulation tools are always in need of more than available computational sources. This is the case for especially complex, large scale flow problems. For these large scale problems, the soft error tolerance of the simulation codes should also be encountered where it is not an issue in relatively small scale problems due to the low occurrence probabilities. In this study, we analyzed the reaction of an incompressible flow solver to randomly generated soft errors at several levels of computation. Soft errors are induced into the final global assembly matrix of the solver by manipulating predetermined bit-flip operations. Behaviour of the computational fluid dynamics (CFD) solver is observed after iterative matrix solver, flow convergence and CFD iterations. Results show that the iterative solvers of CFD matrices are highly sensitive to customized soft errors while the final solutions seem more intact to bit-flip operations. But, the solutions might still differ from the real physical results depending on the bit-flip location and iteration number. So, the next generation computing platforms and codes should be designed to be able to detect bit-flip operations and be designed bit-flip resistant. WOS:000673091000001 Q2

With the continuous scaling-down of transistors, the soft error issue of the combinational circuit becomes more serious. Triple Modular Redundancy (TMR) and Gate-Sizing (GS) are commonly used hardening methods for combinational circuits. However, the traditional TMR method is often applied at the module level, causing a large area overhead. Therefore, to explore the feasibility of refined and more general TMR, a General Efficient TMR (GE-TMR) method is proposed in this paper. Furthermore, since the hardening process is a multi-objective optimization problem, a Solution Distribution Optimized NSGA-II (SDON) algorithm is proposed. It features a trade-off between Soft Error Rate (SER), delay, and area. Based on the SDON, we systematically characterized and compared the three hardening methods, which are GE-TMR, GS, and MIX (a hybrid application of GE-TMR and GS). The experimental results show that GE-TMR can provide lower SER solutions (SER reduction >88%) than GS (SER reduction >85%) when the area overhead >200%. By combining GE-TMR and GS, in the interval of 100% 81%) than the two hardening methods optimized separately (SER reduction of 64% and 80% for GE-TMR and GS, respectively).

As the demand of safety-critical applications (e.g., automobile electronics) increases, various radiation-hardened flip-flops are proposed for enhancing design reliability. Among all flip-flops, Delay-Adjustable D-Flip-Flop (DAD-FF) is specialized in arbitrarily adjusting delay in the design to tolerate soft errors induced by different energy levels. However, due to a lack of testability on DAD-FF, its soft-error tolerability is not yet verified, leading to uncertain design reliability. Therefore, this work proposes Delay-Adjustable, Self-Testable Flip-Flop (DAST-FF), built on top of DAD-FF with two extra MUXs (one for scan test and the other for latching-delay verification) to achieve both soft-error tolerability and testability. Meanwhile, a built-in self-test method is also developed on DAST-FFs to verify the cumulative latching delay before operation. The experimental result shows that for a design with 8,802 DAST-FFs, the built-in self-test method only takes 946 ns to ensure the soft-error tolerability. As to the testability, the enhanced scan capability can be enabled by inserting one extra transmission gate into DAST-FF with only 4.5 area overhead.

Advent and rapid development of on-chip computation in applications based on internet of things has opened space for integration of human life processes with technology. Wireless sensor node is a crucial component of this integration and SRAM employed in these nodes is under renovation phase. In this work, a novel single ended, bit-line powered 10T static random-access memory cell is proposed which improves access time, dissipates low power and supports bit-interleaving. The performance metrics of proposed design are compared with conventional 6T (conv.6T), tunable 8T(TUA8T), transmission gate based 9T(TRD9T), PPN10T(P10T), Schmitt-trigger based 10T (STR10T), loop cutting 10T (LC10T), and data dependent 11T(DD11T) cell to affirm the novelty of observed results. The reduction of soft error in proposed 10T cell is indicated by 1.22 $$\times$$ /1.13 $$\times$$ /1.13 $$\times$$ /0.91 $$\times$$ /1.49 $$\times$$ /1.12 $$\times$$ improvement in critical charge in comparison to conv.6T/TUA8T/TRD9T/STR10T/P10T/LC10T cell respectively. The read and write delay of proposed cell is improved by 1.56 $$\times$$ /1.04 $$\times$$ //1.04 $$\times$$ /1.57 $$\times$$ /1.14 $$\times$$ /1.12 $$\times$$ /1.05 $$\times$$ and 3.29 $$\times$$ /2.29 $$\times$$ /2.49 $$\times$$ /7.94 $$\times$$ /7.15 $$\times$$ /3.38 $$\times$$ /2.32 $$\times$$ respectively compared to conv.6T/TUA8T/TRD9T/STR10T/P10T/DD11T/LC10T cell. Additionally, read and write static noise margin of proposed 10T cell is improved by 2.22 $$\times$$ /2.04 $$\times$$ /1 $$\times$$ /1.67 $$\times$$ /1.06 $$\times$$ /1.75 $$\times$$ /1 $$\times$$ and 1.18 $$\times$$ /1.22 $$\times$$ /0.89 $$\times$$ /0.93 $$\times$$ /1.23 $$\times$$ /1.33 $$\times$$ /0.98 $$\times$$ respectively in comparison to conv. 6T/TUA8T/TRD9T/STR10T/P10T/DD11T/ LC10T cell. This article further demonstrates 1.88 $$\times$$ and 1.26 $$\times$$ tighter disperse in read power variability and read current variability respectively as compared with that of conv. 6T SRAM cell. The reduced cell density due to more number of transistors is compensated by improved $$I_{on}$$ / $$I_{off}$$ ratio.

Multicores increasingly deploy safety-critical parallel applications that demand resiliency against soft-errors to satisfy the safety standards. However, protection against these errors is challenging due to complex communication and data access protocols that aggressively share on-chip hardware resources. Research has explored various temporal and spatial redundancy-based resiliency schemes that provide multicores with high soft-error coverage. However, redundant execution incurs performance overheads due to interference effects induced by aggressive resource sharing. Moreover, these schemes require intrusive hardware modifications and fall short in providing efficient system availability guarantees. This article proposes PRISM, a resilient multicore architecture that incorporates strong hardware isolation to form redundant clusters of cores, ensuring a non-interference-based redundant execution environment. A soft error in one cluster does not effect the execution of the other cluster, resulting in high system availability. Implementing strong isolation for shared hardware resources, such as queues, caches, and networks requires logic for partitioning. However, it is less intrusive as complex hardware modifications to protocols, such as hardware cache coherence, are avoided. The PRISM approach is prototyped on a real Tilera Tile-Gx72 processor that enables primitives to implement the proposed cluster-level hardware resource isolation. The evaluation shows performance benefits from avoiding destructive hardware interference effects with redundant execution, while delivering superior system availability.

To achieve improved speed of operation, a higher integration density and lower power dissipation, transistors are being scaled aggressively. This trend has reduced the critical charge of sensitive nodes. As a result, SRAM cells used in the high radiation environment of aerospace have become highly vulnerable to soft errors. In this paper, we propose a soft-error-aware 14T (SEA14T) SRAM cell for aerospace applications. The performance of the proposed cell is assessed by comparing it with other radiation-hardened SRAM cells like QUCCE12T, WE-QUATRO, RHM12T, RHD12T, RSP14T and RHBD14T. The proposed cell can fully recover from a single-event upset, of any strength and polarity, induced at all the sensitive nodes. Simulation results also show that SEA14T can fully recover from a multi-node upset induced at the internal node-pair. The proposed cell exhibits $1.06\times / 1.08\times / 1.36\times $ shorter read delay than QUCCE12T/ WE-QUATRO/ RHBD14T and $1.03\times / 1.09\times / 1.12\times / 1.15\times / 1.17\times $ shorter write delay than RHM12T/ WE-QUATRO/ QUCCE12T/ RSP14T/ RHD12T. It also shows $1.33\times / 1.6\times / 2.4\times $ higher read stability than QUCCE12T/ WE-QUATRO/ RHBD14T and $1.13\times / 1.32\times / 1.37\times / 1.42\times / 1.5\times $ higher write ability than RHM12T/ WE-QUATRO/ QUCCE12T/ RSP14T/ RHD12T. Furthermore, the proposed cell consumes $2.31\times / 2.42\times / 2.55\times / 3.04\times $ lower hold power than RHD12T/ RSP14T/ WE-QUATRO/ QUCCE12T @ ${V} _{\text {DD}}$ = 1 V. All these improvements are achieved at the cost of a slightly larger area overhead.

Radiation vulnerability and high power density are critical challenges in modern CMOS processors. Spin-based devices like magnetic tunnel junction (MTJ) are among the promising alternatives for addressing these challenges thanks to their fascinating properties such as radiation immunity, non-volatility, high endurance, and compatibility with the CMOS fabrication process. Utilizing the fascinating non-volatile property of the MTJ device, a high-performance, and energy-efficient soft error immune retention latch, and a high-reliable non-volatile flip-flop (FF) are proposed in this paper. Thanks to the single event upset (SEU) immunity, the proposed circuits are applicable in designing highly reliable processors, especially in applications like aerospace systems, where immunity to radiation induced soft errors is very critical. Because of the innovative design of the proposed approach, the MTJ switching delay does not affect the performance of the proposed latch. The simulation results indicate that the proposed latch offers lower delay, power consumption, and power delay product (PDP) than the state-of-the-art designs. The results of the comprehensive Monte-Carlo simulations also demonstrate that the proposed approach is more robust to process, voltage, and temperature variations as compared to their previous counterparts. This is because our designs do not use a pre-charge sense amplifier (PCSA) to read the data stored in the MTJs, and hence, the proposed designs have lower error rates. Furthermore, the transient impact of the particle strikes on the internal nodes is not transferred to the output node of the proposed circuits. The proposed design also has a significantly shorter output recovery time compared to its state-of-the-art counterparts.

Recent advances in CMOS scaling have made circuits more and more sensitive to errors and dysfunction caused by ionizing radiation, even at ground level, requiring accurate modeling of such effects. Besides generation, transport, and collection of radiation-induced excess carriers, another phenomenon, called funneling, has to be modeled for an accurate prediction of soft errors. The funneling effect occurs when the radiation track crosses a space charge region and generates excess carriers with a density higher than the doping close to it. These carriers distort the electric field of the space charge region, deeply changing the transport mechanism, from diffusion in a field-free semiconductor to drift. The objective of this work is to include funneling as part of the generalized lumped devices model in order to obtain a complete tool for SPICE-compatible simulations of single-event effects (SEEs). The latter approach has been recently proposed to simulate radiation-induced charges in the silicon substrate and is based on the so-called generalized lumped devices that simulate charge generation, propagation, and collection using standard circuit simulators. The generalized devices are here extended to include funneling and used to simulate an alpha particle impinging on the bulk of nMOS and pMOS transistors. The results obtained are validated with TCAD numerical simulations. Finally, an static random-access memory (SRAM) struck by an alpha particle is analyzed. The model predicts that the occurrence of a soft error, i.e., flipping of memory state, may depend on whether or not there is funneling. This justifies the need for accurate modeling of funneling phenomena to predict SEEs in ICs.

The adder is an essential component of data paths, and as a result of the shrinking size of electronic devices, it is becoming more susceptible to manufacturing defects and soft errors. Thus, the design of fault-tolerant adders is crucial to the correct operation of arithmetic circuits. In this paper, we propose different fault-tolerant carry look-ahead adder designs against single-bit soft errors based on double modular redundancy DMR and hybrid fault-tolerant schemes. In DMR-based design, we combine a partial hardware redundancy scheme with a protected C-element to achieve full soft error masking, while in the hybrid design, we employ a partial hardware redundancy combined with a parity prediction scheme to improve fault tolerance capability of the adder while reducing area overhead. We use two different voter circuits for merging the partial hardware redundancy into the carry generation logic and to achieve higher fault masking rate and lower area overhead in comparison with existing approaches. Simulation results show that the proposed design schemes take precedence over other schemes in terms of failure rate, area overhead and delay overhead.

The system-on-chip (SoC) designs for future Internet of Things (IoT) systems, spanning client platforms to cloud datacenters, need to deliver uncompromising and scalable performance with extreme energy efficiency for diverse workloads and applications, while satisfying a wide range of energy budgets, as well as platform cooling and power delivery constraints. Low-latency, burst-mode responsiveness, and scalable high-throughput performance must be delivered on demand for a range of thread-parallel, task-parallel, and data-parallel workloads covering traditional and emerging applications. This article discusses the challenges and opportunities for many-core SoC design in scaled CMOS process operating over a wide voltage-frequency range including near-threshold-voltage (NTV) that can meet the compute demands of the future at scale, flexibly, and efficiently. This article covers: 1) circuit design techniques for NTV cores; 2) mitigation techniques for within-die parameter variations via multivoltage frequency schemes; 3) digital integrated voltage regulators (VRs) for fine-grain and wide-range voltage modulation; and 4) radiation-induced soft error rate (SER) characterization and mitigation techniques to enable reliable operation at NTV. Silicon prototype examples will be used to illustrate the different techniques and highlight future research directions.

In this paper, we propose an efficient and promising soft error tolerance approach for arithmetic circuits with high performance and low area overhead. The technique is applied for designing soft error tolerant adders and is based on the use of a fault tolerant C-element connecting a given adder output to one input of the C-element while connecting a delayed version of that output to the second input. It exploits the variability of the delay of the adder output bits, in which the most significant bits (MSBs) have longer delay than the least significant bits (LSBs), by adding larger delay to the LSBs and smaller delay to the MSBs to guarantee full fault tolerance against the largest pulse width of transient error (soft error) for the available technology with minimum impact on performance. To guarantee fault protections for transistors feeding outputs with smaller added delay, the technique utilizes transistor scaling to ensure that the injected fault pulse width is less than the added delay of the second output of the C-element. Simulation results reveal that the proposed technique takes precedence over other techniques in terms of failure rate, area overhead, and delay overhead. The evaluation experiments have been done based on simulations at the transistor level using HSPICE to take care of temporal masking combined with electrical masking. In comparison to TMR, the technique achieves 100% reliability with 31% reduction in area overhead without impacting performance in the case of a 32-bit adder, and 42% reduction in area overhead and 5% reduction in performance overhead in the case of a 64-bit adder. While our proposed technique achieves area reduction of 4.95% and 9.23% in comparison to CE-based DMR and Feedback-based DMR techniques in the case of a 32-bit adder, it achieves area reduction of 19.58% and 23.24% in the case of a 64-bit adder.

Triple modular redundancy (TMR) is a single-event upset (SEU)-mitigation technique that uses three circuit copies to mask a failure in any one copy. It improves the soft error reliability of designs implemented on SRAM-based field-programmable gate arrays (FPGAs) by masking the effects of upsets in the configuration memory. Although TMR is most effective when applied to an entire FPGA design, a reduction in the sensitive cross section of an FPGA design can be obtained by applying TMR selectively. This article explores several approaches for selecting components to triplicate. The benefit is a reduction in the neutron cross section for any output error as a percentage compared to that of a non-triplicated design. The cost is the percentage of components triplicated. The goal is to maximize the benefit–cost ratio. Twenty-five different selections are tested on a benchmark design. Some selections increase the cross section; others decrease the cross section significantly.

In this article, we present Tool suIte for rAdiation Reliability Assessment (TIARA), an industrial version of a Monte Carlo single-event simulation platform, enabling fast and accurate soft error rate (SER) estimations. This tool is capable of simulating logic cells manufactured in several technologies such as fully depleted silicon on insulator (FD-SOI), FinFET, and planar bulk CMOS. Moreover, TIARA is able to handle many different types of radiations including by-products of neutron or proton spallation, heavy ions and alpha particles, representative of terrestrial and space environments. Three use cases are shown in this article to illustrate TIARA capabilities. The first one compares the error rate in Geostationary Earth Orbit (GEO) orbit of all flip-flop variants from a 28-nm FD-SOI library. Second one evaluates multiple-cell upsets as a function of simulated array size for static random access memory (SRAM) cells manufactured in a 40-nm bulk technology. The last one shows alpha and neutron SER results for SRAM designed in a bulk-FinFET technology.

Space consists of high-energy particles and high-temperature fluctuations, which causes single event upsets (SEUs). Conventional 6T static random access memory (SRAM) is unable to tolerate this harsh environment in space. Therefore, it is necessary to design an SRAM, which can withstand this harsh environment. In order to mitigate SEUs, a radiation-hardened SRAM cell, named soft-error resilient read decoupled 12T (SRRD12T), is presented in this article. To estimate the relative performance of the proposed cell, it is compared with other contemporary designs, such as RHMN12T, RHMP12T, RHD12T, QUCCE12T, and QUATRO12T, over various important design metrics. SRRD12T can not only recover from SEU induced at any of its sensitive nodes but also from single event multi-node upsets (SEMNUs) induced at its storage node pair. Furthermore, due to the read decoupled design of SRRD12T, it exhibits the highest read stability. In addition to these, SRRD12T shows $1.14\times /1.17\times $ shorter write delay than RHD12T/RHMP12T. Moreover, SRRD12T consumes lower hold power and exhibits higher write ability than most of the comparison cells. However, these advantages are obtained by exhibiting a slightly longer read delay.

This work evaluates the Soft Error sensitivity of the complete SRAM architecture using the 16 nm Bulk CMOS technology model. The paper investigated the fault propagation in cells and bitlines during the Hold, Read, Write operations, and the half-selection situation. The 6T, 8T, 9T, 8TSER, and DICE SRAM cells are compared not only about the radiation effects but also observing the timing, power, and static noise margin outcomes. DICE cell presents the highest robustness to the radiation effects. The 8T-SER presented the best stability results. The half-selection situation shows the potential to increase the cell sensitivity by $$\approx$$ 50 $$\%$$ compared to the Hold perspective.

Convolutional neural networks (CNNs) are quickly becoming an attractive solution for autonomous vehicles, military weapons, and space exploration. Thanks to their reconfiguration ability, design flexibility, and low power consumption, field-programmable gate arrays (FPGAs) have become a promising candidate for CNN accelerators. However, FPGAs have been proven to be susceptible to radiation-induced single-event upsets (SEUs). One goal of this article is to analyze the impact of quantization on the reliability of CNNs in FPGAs. Therefore, we performed quantization on ZynqNet without affecting its classification accuracy. Meanwhile, we implemented the triple modular redundancy (TMR) version of ZynqNet and we also evaluated the effects of SEUs on these CNNs through both fault injections and neutron exposures. Fault injection results show that TMRed ZynqNet reduces the soft error rate (SER) by 33.59% with a circuit area increase of 111.92% when compared with the standard ZynqNet. The experimental results demonstrate that the quantized ZynqNet reduces the SER by 71.36% with a circuit area reduction of 44.76% when compared with the standard ZynqNet. These results confirm that quantization does contribute to SER reduction of the neural networks. In addition, the operating system on the processing system (PS) side was also found to be highly sensitive to SEUs, and, thus, mitigation techniques should be applied.

With the widespread use of the multicore systems having smaller transistor sizes, soft errors become an important issue for parallel program execution. Fault injection is a prevalent method to quantify the soft error rates of the applications. However, it is very time consuming to perform detailed fault injection experiments. Therefore, prediction-based techniques have been proposed to evaluate the soft error vulnerability in a faster way. In this work, we present a soft error vulnerability prediction approach for parallel applications using machine learning algorithms. We define a set of features including thread communication, data sharing, parallel programming, and performance characteristics; and train our models based on three ML algorithms. This study uses the parallel programming features, as well as the combination of all features for the first time in vulnerability prediction of parallel programs. We propose two models for the soft error vulnerability prediction: (1) A regression model with rigorous feature selection analysis that estimates correct execution rates, (2) A novel classification model that predicts the vulnerability level of the target programs. We get maximum prediction accuracy rate of 73.2% for the regression-based model, and achieve 89% F-score for our classification model.

A new dynamic random access memory (DRAM) memory cell transistor is fabricated, and its soft-error immunity and rowhammer tolerance are studied. The vertical channel is formed by selective epitaxial growth of silicon pillar, and the surround gate forms a fully depleted (FD) channel, which can suppress floating-body effects, such as hysteresis. A TCAD simulation study compares this device and conventional bulk saddle FinFET in terms of soft error immunity and rowhammer tolerance. The confined channel limits soft error because of its thin channel volume for charge generation due to alpha and neutron particles. The surround gate device is inherently free from rowhammer attack as each silicon body of any memory cell transistor is fully isolated from neighboring word lines.

In aerospace applications, the conventional Static Random Access Memories (SRAMs) are facing high soft error problems like a single event upset. Several radiation-hardened based design (RHBD) like twelve-transistor (12T) Dice, 12T We-Quatro SRAM cells, etc., had been developed to address the soft error problems. But they all are consuming comparatively more total and static power with more delay and area. The 10T SRAM cell had been developed to reduce the power dissipation and area overhead. But the analysis of 10T cell shows a write failure at high-frequency. An RHBD 12T SRAM cell has been proposed in this paper. The proposed 12T SRAM cell consumes less total, and static power dissipation compared to 12T We-Quatro and 12T Dice cell, respectively. The critical charge and hold noise margin of the proposed SRAM cell have been improved compared to We-Quatro and Dice cell. The simulated result shows that the proposed SRAM cell has provided the less and comparable area, high write speed, and good writability under process variations. Finally, the Monte Carlo Simulation of SRAM cells under 45 nm CMOS technology validates the efficiency of the 12T proposed cell.

Automotive systems are integrating artificial intelligence and complex software stacks aiming to interpret the real world, make decisions, and perform actions without human input. The occurrence of soft errors in such systems can lead to wrong decisions, which might ultimately incur in life losses. This brief focuses on the soft error susceptibility assessment of a real automotive application running on top of unmodified Linux kernels, and considering two commercially available processors, and three cross-compilers. Results collected from more than 29 thousand simulation hours show that the occurrence of faults in critical functions may cause $2.16\times $ more failures on the system.

This paper presents two novel low cost, double-and-triple-node-upset tolerant latch designs. First, a novel low cost and double-node-upset (DNU) completely tolerant (LCDNUT) latch design is proposed. The latch mainly comprises a storage module (SM) feeding back to a 3-input C-element. The SM mainly consists of eight input-split inverters. Since the inputs of the C-element cannot be simultaneously flipped, the latch tolerates any DNU in the SM. When a single node in the SM and the output node are affected, the latch can self-recover from the DNU. Second, to completely tolerate any triple-node-upset (TNU), by replacing the C-element in the LCDNUT latch with a two-level error-interceptive module constructed from triple C-elements, a novel low cost and TNU completely tolerant (LCTNUT) latch design is proposed. Simulation results demonstrate the robustness of the proposed latches. Furthermore, due to the use of a high-speed transmission path, the clock-gating technology and fewer transistors, the proposed LCTNUT latch reduces the delay-power-area product by approximately 99.39 percent and has a low sensitivity to the process-voltage-and-temperature variation effects, compared with currently the only TNU completely tolerant latch design.

Deep neural networks (DNNs) have been successfully deployed in widespread domains, including healthcare applications. DenseNet201 is a new DNN architecture used in healthcare systems (i.e., presence detection of the surgical tool). Specialized accelerators such as GPUs have been used to speed up the execution of DNNs. Nevertheless, GPUs are prone to transient effects and other reliability threats, which can impact DNN models’ reliability. Safety-critical systems, such as healthcare applications, must be highly reliable because minor errors might lead to severe injury or death. In this paper, we propose a selective mitigation technique that relies on in-depth analysis. First, we inject the DenseNet201 model implemented on a GPU via NVIDIA’s SASSIFI fault injector. Second, we perform a comprehensive analysis from the perspective of kernel and layer to identify the most vulnerable portions of the injected model. Finally, we validate our technique by applying it to the top-vulnerable kernels to selectively protect the only sensitive portions of the model to avoid unnecessary overheads. Our experiments demonstrate that our mitigation technique achieves a significant reduction in the percentage of errors that cause malfunction (errors that lead to misclassification) from 6.463% to 0.21%. Moreover, the performance overhead (the execution time) of our technique is compared with the well-known protection techniques: Algorithm-Based Fault Tolerance (ABFT), Double Modular Redundancy (DMR), and Triple Modular Redundancy (TMR). The proposed solution shows only 0.3035% overhead compared to these techniques while correcting up 84.8% of the SDC errors in DenseNet201, remarkably improving the healthcare domain’s model reliability.

Soft error resilience is an increasingly important requirement of integrated circuits realized in CMOS nanometer technologies. Among the several approaches, Bulk Built-in Current Sensors (BBICS) offer a promising solution as they are able to detect particle strikes immediately after its occurrence. Based on this idea we demonstrate a novel modular BBICS (mBBICS) that tackles the main problems of these integrated sensors – area, leakage, and robustness. Simulations based on a predictive nanometer technology indicate competitive response times for high performance applications at the cost of 25 % area overhead and very low power penalty. Thereby, all simulated particle strikes that lead to transient faults could be detected. Additionally, reliability analysis proved the robustness of the proposed mBBICS against wide variations of temperature and process parameters.

Negative bias temperature instability (NBTI) is the major reliability issue which affects many parameters such as threshold voltage, mobility, and leakage current. The threshold voltage of the PMOS transistor increases due to NBTI with stress time, which degrades the circuit performance. In this article, we have proposed a novel reliable data-dependent low power 10T SRAM cell, which is highly stable and free from half select issues. We investigated all the circuit simulations using 65nm CMOS technology. The proposed 10T cell has a higher critical charge and lower soft error rate (SER) as compared to other SRAM cells. To better assess, we introduced a bit read failure (BRF) at read operation and observed that the BRF of the proposed 10T cell is significantly reduced as compared to the other considered SRAM cells at 0.15V supply. The leakage power, write power-delay-product, and read power-delay-product of the proposed 10T cell is $0.1\times $ , $0.21\times $ , and $3.13\times $ , respectively as compared to the conventional 6T cell at 0.4V supply. The proposed cell offers $4\times $ , $1.15\times $ and $1.66\times $ higher read, hold and write margin, respectively, as compared to 6T cell at 0.4V supply voltage. The simulation result shows that the HSNM, WSNM, and RSNM are decreased by 0.31%, 0.13%, and 0.08%, respectively, with the proposed 10T cell while 6T cell reduces 3.21%, 0.43%, and 8.62%, respectively, after 10 years of stress time. We have also introduced an on-chip adaptive VDD scaled reconfigurable architecture compared to the conventional array architecture design to reduce 97.04% and 92.17% hold power of unselected cells during read and write operation of the selected cell, respectively for the proposed 10T cell.

The work proposes an 11T SRAM cell which confirms its reliability for Internet of Things (IoT) based health monitoring system. The cell executes improved write and read ability using data-dependent feedback cutting and read decoupled access path mechanism respectively. The write and read stabilities of proposed cell are $$2.67\times$$ and $$1.98\times$$ higher than the conventional 6T cell with $$1.53\times$$ area overhead. Moreover, the improved soft error tolerance and better reliability against negative bias temperature instability (NBTI) of proposed 11T SRAM cell as compared to other considered cells make it suitable for the bio medical implant. A low-power double adjacent bit error detection and correction (DAEDC) scheme is proposed to further improve the robustness of designed 1 Kb bit-interleaved memory against the soft error occurrence. The leakage power of proposed cell is controlled by the stacking devices used in its cross-coupled inverter pair and the column based read ground signal (RGND) further controls the unnecessary bit line switching power of the array.

The SRAM-based field-programmable gate array (FPGA) is extremely susceptible to single event upsets (SEUs) on configuration memory which can lead to soft error and malfunction of the circuit. Facing the ever-growing number of configuration bits in modern FPGAs, traditional scrubbing is getting harder to find errors in time, resulting in mismatching between the SEU sensitivity and scrubbing performance. This article proposes a hierarchical scrubbing technique that makes full use of the SEU sensitivity based on the adaptive mean time to detect (MTTD) for each frame. It distinguishes the configuration frames with multipriority and uses different scrubbing methods for different priorities. Also, a model has been built for solving the MTTD allocating problem and enabling an effective scrubbing when SEU occurrence. Moreover, the corresponding hardware architecture is supported and the fault injection-based evaluation on a Xilinx Kintex-7 FPGA is done. The result shows that it can improve mean upsets to failure from $1.56 \times $ to $146.93 \times $ , which is proportional to the mean time to failure (MTTF) improvement.

This study seeks to understand the soft error vulnerability of asynchronous iterative methods, with a focus on stationary iterative solvers such as Jacobi. A theoretical investigation into the performance of the asynchronous iterative methods is presented and used to motivate several fault recovery methods for asynchronous linear solvers. The numerical experiments utilize a hybrid-parallel implementation where the computational work is distributed over multiple nodes using MPI and parallelized on each node using OpenMP, and a series of runs are conducted to measure both the impact of soft faults and the effectiveness of the recovery methods. Trials are run to compare two models for simulating the occurrence of a fault as well as techniques for recovering from the effects of a fault. The results show that the proposed strategies can effectively recover from the impact of a fault and that the numerical model for simulating soft faults consistently produces fault effects that enable the investigation and tuning of recovery techniques in action.

With the scaling limitations and increasing leakage power of the existing charge-based memories, next-generation memory technologies to overcome the issues are in development. Among the various emerging memories, phase change memory (PCM) is considered as a promising candidate due to its scalability potential and negligible leakage power. For enhanced storage density, the multilevel cell (MLC) operation has been proposed for PCM. This, however, comes at cost of poor reliability, write energy increase and performance degradation. Unlike DRAM, the MLC PCM has a much higher soft error rate due to the resistance drift phenomenon. Error correction code (ECC) schemes can be utilized to improve the MLC PCM reliability, however, this would lead to a lower storage density and an increase in write energy and latency. The iterative programming required for the MLC PCM also degrades its energy efficiency and performance. This paper introduces a simple yet effective encoding scheme to mitigate the problems of the MLC PCM. By using a simple XOR-based encoding, the proposed architecture minimizes the most drift-prone state in the data. The method divides the original data into several encoding blocks and analyzes initial pattern frequencies for each 2-bit pattern. Based on the initial pattern frequencies, the inputs for the XOR encoding are selected that result in minimal frequency of the drift-prone state. This considerably enhances the MLC PCM reliability, leading to a high storage density with a reduced ECC overhead. The energy efficiency and performance are also improved due to reduction in iterative current pulses and ECC overhead. The simulation results show a reduction of about $10^{5}$ X in soft error rate. The improvements in energy efficiency and performance over the conventional 4-level cell (4LC) PCM are 11.5% and 31.9%, respectively.

At the Korea Multi-purpose Accelerator Complex (KOMAC), a 100-MeV high-power proton linac has been used for proton-beam irradiation services for various applications and research programs, including material science, bio-medical science, semiconductor applications, as well as nuclear physics and basic science, since commissioning of the machine in 2013. Recently, demands for fast neutrons from users in the semiconductor industries are increasing to test the semiconductor device SER (soft error rate) or SEE (single event effect). At present, we provide pilot services to users with pulsed white-spectrum neutrons (max. neutron energy ∼100 MeV) generated at the beam dump, which is made of copper. However, the neutron energy should be increased at least to 200 MeV to meet international standards such as ISO26262 or JEDEC89A. For the upgrade of the linac energy to 200 MeV, we conducted a preliminary design study, including superconducting radio-frequency (SRF) based linac structure, a neutron generation target and a neutron utilization facility. The upgrade plan for the KOMAC linac, along with the preliminary results of the design study on the superconducting linac and neutron generation facility, will be given in this paper.

As General-Purpose Graphics Processing Units (GPGPUs) become pervasive for the High-Performance Computing (HPC), ensuring that programs can be protected from soft errors has become increasingly important. Soft errors may cause Silent Data Corruptions (SDCs), which produces erroneous execution results silently. Due to the massive parallelism of GPGPUs, fully protecting them against soft errors introduces nontrivial overhead. Fortunately, imprecise execution outcomes are inherently tolerable for some HPC programs due to the nature of these applications. Leveraging the feature, selective soft error protection can be applied to reduce energy consumptions. In this work, we first propose a GPGPU-based Soft-Error aware APproximation analysis framework (G-SEAP) to characterize the approximation characteristics of soft errors. Based on G-SEAP, we perform an exhaustive analysis for 17 representative HPC benchmarks and observe 72.7% of SDCs on average are approximable. We also observe that the dataflow of application, kernel function reliability requirement, instruction-type, and data bit-location are all important factors for program’s correctness. Lastly, according to the observations, we further design an approximate Error Correction Codes (ECCs) mechanism and an approximate instruction duplication technique to illustrate how G-SEAP provides useful guidance for energy-efficient soft-error elimination in GPGPUs.

Radiation-induced single transient faults (STFs) are expected to evolve into multiple transient faults (MTFs) at nanoscale CMOS technology nodes. For this reason, the reliability evaluation of logic circuits in the presence of MTFs is becoming an important aspect of the design process of deep submicron and nanoscale systems. However, an accurate evaluation of the reliability of large-scale and very large-scale circuits is both very complex and time-consuming. Accordingly, this paper presents a novel soft error reliability calculation approach for logic circuits based on a probability distribution model. The correctness or incorrectness of individual logic elements are regarded as random events obeying Bernoulli distribution. Subsequently, logic element conversion-based fault simulation experiments are conducted to analyze the logical masking effects of the circuit when one logic element fails or when two elements fail simultaneously. On this basis, the reliability boundaries of the logic circuits can efficiently be calculated using the proposed probability model and fault simulation results. The proposed solution can obtain an accurate reliability range through single fault and double faults simulations with small sample sizes, and also scales well with the variation of the error rate of the circuit element. To validate the proposed approach, we have calculated the reliability boundaries of ISCAS’85, ISCAS’89, and ITC’99 benchmark circuits. Statistical analysis and experimental results demonstrate that our method is effective and scalable, while also maintaining sufficiently close accuracy.

Soft error protection is a paramount requirement for memories exposed to radiation environment. To satisfy the demand, a radiation-hardened new-quatro 10T memory cell is proposed in this brief, which is immune to single-node upset and also has high resilience to multinode upset while features read-disturbance-free benefiting from its internal quad-node interlocked feedback mechanism. Simulation results show that it provides ample radiation robustness to single event and gives $1.75\times $ improvements in multinode upset tolerance when compared with the previous 12T dual-interlocked storage cell (DICE-12T) bitcell, signifying the higher fault tolerance capability. In addition, the proposed design also achieves $6.48\times $ enhancement in read noise margin when compared with the DICE-12T bitcell while compromising only $2.1\times $ larger area than a reference 6T cell based on a 65-nm logic design rule, exhibiting the superiority in read stability.

International audience; In addition to high-energy hadrons, which include neutrons, protons, and pions above 20 MeV, thermal neutrons (ThNs) are a major concern in terms of soft error rate (SER) for electronics operating in the large hadron collider (LHC) accelerator at the European Organization for Nuclear Research (CERN). Most of the electronic devices still contain Boron-10 inside their structure, which makes them sensitive to ThNs. The LHC radiation environment in different tunnel and shielded areas is analyzed through measurements and FLUKA simulations, showing that the ThN fluence can be considerably higher than the high-energy one, up to a factor of 50. State-of-the-art commercial-off-the-shelf (COTS) components such as SRAM, field-programmable gate arrays (FPGA), and Flash memories of different technologies are studied to derive the expected single-event upset (SEU) rate due to ThNs, relative to the high-energy hadron contribution. We find that for the studied parts and most of the accelerator applications, ThNs are the dominating source of upsets with respect to the high energy particles yielding even to neglect the latter in some cases. Indeed, they can induce, in electronics, up to more than 90% of the total upsets. The estimation is performed also for ground-level and avionic applications, and although in general, ThNs are not the main source of SER, in Flash memories they can play the same role as high energy neutrons. Related radiation hardness assurance (RHA) considerations for the qualification of components and systems against ThNs are presented.

We evaluated soft-error tolerance by neutrons and heavy ions on four types of flip flops (FFs) called D-type flip flop (DFF), guard-gate FF (GGFF), feedback recovery FF (FRFF), and dual FRFF (DFRFF) in a 65-nm thin buried oxide (BOX) fully depleted silicon on insulator (FDSOI). FRFF has a guard-gate structure only in the master latch. GGFF and DFRFF have the guard-gate structure in both master and slave latches. The guard-gate structure resolves a single-event transient (SET) pulse by delaying it through the guard gate. FRFF and DFRFF have smaller area and shorter delay overheads than GGFF. We revealed that the guard-gate structure has high soft-error tolerance by low-linear energy transfer (LET) heavy ions, but the larger-LET ions over 40 MeV-cm2/mg cause upset even in the guard-gate structures. We revealed that longer delay in the guard-gate can resolve these issues by circuit simulations.

As the process feature size continues to scale down, the susceptibility of logic circuits to radiation induced error has increased. This trend has led to the increase in sensitivity of circuits to multi-node upsets. Previously, work has been done to harden latches against single event upsets (SEU). Currently, there has been a concerted effort to design latches that are tolerant to double node upsets (DNU) and triple node upsets (TNU). In this paper, we first propose a novel DNU tolerant latch design. The latch is designed specifically to provide additional reliability when clock gating is used. Through experimentation, it is shown that the DNU tolerant latch is 11.3 percent more power efficient than existing latch designs suited for clock gating. In addition to the DNU tolerant design, we propose the first TNU tolerant latch. The TNU tolerant latch is shown to provide superior soft error resiliency while incurring a 40 percent overhead compared to DNU tolerant designs.