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Additional file 1. Identification of candidate disease gene for the consanguineous family with dilated cardiomyopathy.

In recent years, rare plants on the earth have gradually disappeared, so it is urgent to inspect and protect their health. A rare tree monitoring system compatible with NB-IOT (Narrow Band Internet of Things) is designed based on the low-power data transmission technology of LoRa (Long Range Radio). The system takes stm32f103c8t6 as the core of the controller, collects information through temperature and humidity sensor, attitude sensor, infrared pyroelectric sensor and sound sensor, builds a server to store the information and data back to the server, uses the terminal to access the server, and reminds the operator when the amount of information exceeds a certain threshold, Finally, the real-time monitoring of rare trees in the field is realized.

A closed-loop self-excitation/detection application specific integrated-circuit (ASIC) based on the phase-locked loop (PLL) used for micro-resonant infrared detector is designed to improve the measurement accuracy, miniaturization and integration. A switched capacitor array is proposed and used in the VCO to meet the requirements of the system. The VCO was implemented by $0.18 \mu \mathrm{m}$ CMOS technology, the chip area is 1.1*0.9 mm2. The proposed VCO can be operated at 2.603.38 GHz, the measured phase noise are -125.9 dBc/Hz@1MHz at 2.60 GHz and -123.3 dBc/Hz@1MHz at 3.38GHz respectively. The VCO draws 3.06 mW power consumption from a 1.8 V supply.

A 4 GHz PLL (phase-locked loop)-type frequency synthesizer has been implemented in the standard 0.18μm mixed-signal and RF 1P6M CMOS technology. It integrates a VCO, a dual-modulus prescaler, PFD, a charge pump, a control logic, various digital counters and digital registers onto a single chip. With the help of the linear model of the loop, the design and optimization of the loop parameters are discussed in detailed. The measured results show that the locked range was 4096-4288 MHz and the phase noise could reach -117 dBc/Hz at 1MHz offset from the carrier 4.154 GHz, the output power is about -3 dBm. The chip area is 0.675 mm×0.700 mm. The DC power consumption of the core part is about 24 mW under 1.8 V supply. DOI: http://dx.doi.org/10.11591/telkomnika.v11i2.2003

Based on the transceiver architecture of WLAN 802.11a, the frequency plan of the RF transceiver is accomplished. A PLL (phase-locked loop)-type frequency synthesizer used for the system has been implemented in the standard 0.18-µm mixed-signal and RF 1P6M CMOS technology of SMIC. It integrates a VCO, a dual-modulus prescaler, PFD, a charge pump, a control logic, various digital counters and digital registers onto a single chip. With the help of the linear model of the loop, the design and optimization of the loop parameters are discussed in detailed. The measured results show that the locked range was 4096–4288 MHz and the phase noise could reach −117.3 dBc/Hz at 1 MHz offset from the carrier 4.154 GHz, the output power is about −3 dBm. The chip area is 0.675 mm×0.700 mm. The DC power consumption of the core part is about 24 mW under one 1.8-V supply.

A PLL (phase-locked loop)-type 2.4GHz frequency synthesizer is designed in the standard 0.18µm mixed-signal and RF 1P6M CMOS technology of SMIC. It integrates a VCO, a dual-modulus prescaler, PFD, a charge pump, a control logic, various digital counters and digital registers onto a single chip. With the help of the linear model of the loop, the design and optimization of the loop parameters are discussed in detailed. The VCO is implemented in the CMOS technology of SMIC. The measured phase noise is −125.3 dBc/Hz at offset frequency 1 MHz from the carrier of 2.466 GHz while the VCO core circuit draws only 720 µW from a 0.4 V supply. The designed VCO can cover the frequency range from 2.28 to 2.48 GHz. The simulated results of the PLL show that frequency synthesizer can be in the locked-state quickly. The layout area is 0.675 mm×0.750 mm. The DC power consumption of the core part is about 20 mW under 1.8 V supply.

A 4 GHz quadrature voltage-controlled oscillator (QVCO) topology is proposed where a planar spiral transformer is used as coupling terminals. Two identical LC oscillators are cross-coupled by the transformer to generate the quadrature outputs. The transformer also serves as filtering network for the oscillators to improve the phase noise performance. The quadrature oscillator based on the proposed topology with additional design ideas has been implemented in a 0.18 um mixed-signal 1P6M CMOS technology for 4 GHz-band operation. The simulation gave a phase noise of -122 dBc/Hz at 1 MHz offset with an output power of 1 dBm, while dissipating 7.8 mA under a 1.8 V supply.

Objectives Prolongation of the QRS duration (≥ 120 ms) has been suggested to be an independent risk factor for mortality in patients with heart failure. The purpose of this study was to examine the clinical baseline variables correlated with the QRS duration and the association between the QRS duration and survival in patients with dilated cardiomyopathy (DCM). Methods A retrospective observational cohort study was undertaken in 1119 patients with DCM and a median follow-up of 3.5 years. Standard demographics, transthoracic echocardiography, and routine blood tests were obtained shortly after admission. All patients were subsequently divided into the following groups: QRS > 150 ms, QRS = 120-150 ms, and QRS Results Of the 1108 patient with DCM, 19.3% (n = 216) had QRS > 150 ms, 23.0% (n = 257) had QRS = 120-150 ms, and 57.7% (n = 646) had QRS 150 ms (33.3%), intermediate in those with QRS = 120-150 ms (33.1%), and lowest in those with QRS 2 = 42.811, P Conclusions The QRS duration was correlated with age, LVEF, left ventricle diameter, left atrium diameter, right ventricle diameter and disease course. In addition, QRS prolongation is an independent predictor of increased all-cause mortality in patients with DCM.

A fully integrated cross-coupled LC tank voltage-controlled oscillator (LC-VCO) using transformer feedback is proposed to achieve a low phase noise and ultra-low-power design even at a supply below the threshold voltage. The ultra-low-power VCO is implemented in the mixed-signal and RF 1P6M 0.18-μm CMOS technology of SMIC. The measured phase noise is −125.3 dBc/Hz at an offset frequency of 1 MHz from a carrier of 2.433 GHz, while the VCO core circuit draws only 640 μW from a 0.4-V supply. The designed VCO can cover a frequency range from 2.28 to 2.48 GHz. The tuning range of the circuit is 200 MHz (8.7%) and the FOM is −195.7 dB, which is suitable for an IEEE 802.11b receiver.