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In seismic exploration, seismic data usually contain anomalous amplitude noise whose high energy may affect the results of subsequent processing steps. In industry, this kind of noise is generally suppressed using the anomalous amplitude attenuation (AAA) method. The AAA method essentially suppresses abnormal amplitude noise using a median filter in the time-frequency domain. This makes its performance heavily dependent on the parameters, especially the window width of the median filter. Thus, we propose an improved anomalous amplitude attenuation (IAAA) method based on deep neural networks. The IAAA method contains two steps. In the first step, deep neural networks are used to detect the locations and the widths of noise regions. In the second step, the noise information (locations and widths) obtained at the previous step is exploited to apply the AAA method with more appropriate parameters to each noisy region. Compared with the conventional AAA method, the IAAA method can suppress the noise more effectively and preserve signals better. The experiments on both synthetic data and field data demonstrate that our method outperforms the conventional AAA method.

Stencil computation is one of the fundamental computing patterns in many application domains such as scientific computing and image processing. While there are promising studies that accelerate stencils on FPGAs, there lacks an automated acceleration framework to systematically explore both spatial and temporal parallelisms for iterative stencils that could be either computation-bound or memory-bound. In this article, we present SASA, a scalable and automatic stencil acceleration framework on modern HBM-based FPGAs. SASA takes the high-level stencil DSL and FPGA platform as inputs, automatically exploits the best spatial and temporal parallelism configuration based on our accurate analytical model, and generates the optimized FPGA design with the best parallelism configuration in TAPA high-level synthesis C++ as well as its corresponding host code. Compared to state-of-the-art automatic stencil acceleration framework SODA that only exploits temporal parallelism, SASA achieves an average speedup of 3.41× and up to 15.73× speedup on the HBM-based Xilinx Alveo U280 FPGA board for a wide range of stencil kernels.

In this paper, we propose TAPA, an end-to-end framework that compiles a C++ task-parallel dataflow program into a high-frequency FPGA accelerator. Compared to existing solutions, TAPA has two major advantages. First, TAPA provides a set of convenient APIs that allow users to easily express flexible and complex inter-task communication structures. Second, TAPA adopts a coarse-grained floorplanning step during HLS compilation for accurate pipelining of potential critical paths. In addition, TAPA implements several optimization techniques specifically tailored for modern HBM-based FPGAs. In our experiments with a total of 43 designs, we improve the average frequency from 147 MHz to 297 MHz (a 102% improvement) with no loss of throughput and a negligible change in resource utilization. Notably, in 16 experiments we make the originally unroutable designs achieve 274 MHz on average. The framework is available at https://github.com/UCLA-VAST/tapa and the core floorplan module is available at https://github.com/UCLA-VAST/AutoBridge.

An improved key expansion method is proposed to improve the security performance in AES key expansion. There is large difference of operation time between Mixcolumns and Inverse Mixcolumns, we propose the simplest form of MixColumn and InvMixColumn operation on finite field \(GF(2^{N})\) which consumes same computing resources in the process of encryption and decryption. In terms of the defection of RSA operation efficiency, traditional double prime number is replaced by four prime number, Chinese remainder theorem combined with Montgomery modular multiplication is also presented to optimize modular exponentiation. On this basis, we adopt message digest, digital signature, digital envelope and other technologies to build a mixed encryption system which encompasses convenient key management and high-efficiency encryption and decryption, combined with the advantages of AES and RSA. The experimental results show that optimized algorithm has high speed and feasibility.

Due to the rapid development of the Internet, the network video surveillance technology has been widely implemented to overcome the geographical constraints in the network by monitoring the target in any place. There may be some problems when the Internet providing convenience because it’s available to global users. For example, video reveal may happen in some situations, which is a threaten to government and national security. So encryption network video surveillance research is imperative. The purpose of this paper is to protect the security of network video surveillance information, and to prevent the useful information from being intercepted and stolen by criminals.