Search

To minimize the average latency of users to complete tasks, this letter jointly optimizes offloading decision, computation and bandwidth resource allocation for Mobile Edge Computing (MEC) networks via partial offloading. Since the considered problem is strongly non-convex with coupled variables, we decompose the original problem into two subproblems: (1) offloading decision; (2) communication bandwidth and computation resources allocation, and further employ Block Coordinate Descent (BCD) method to tackle them sequentially with linear computation complexity. Simulation results demonstrate that the proposed algorithm can achieve better performance on the average latency, and converge speedily.

NAND flash-based solid-state drives (SSDs) have been widely used in consumer electronic products such as smartphones, digital video recorders, and laptops. The flash translation layer (FTL) is crucial to the performance of SSDs. In this article, an on-demand FTL, briefly as HDFTL, is proposed for hybrid SSDs built with SLC+MLC flash memory. HDFTL divides the SLC into data blocks and translation blocks and uses all MLC as data blocks. All mapping items are stored in the translation block of the SLC, and partial mapping items are loaded into the cached mapping table of the FTL as needed. The contributions of HDFTL are as follows: (1) Unify the address mapping method of SLC and MLC areas to simplify the FTL design of hybrid SSDs; (2) Split the cached mapping table into a hot-write mapping table and a normal mapping table and use time locality to solve hot-write identification problem in hybrid SSDs; (3) According to the relative wear rate of SLC and MLC areas, adaptively adjust the size of the hot-write mapping table and the normal mapping table. Experimental results show that the performance of HDFTL is better than that of the existing FTLs for hybrid SSDs.

Because of the excellent performance and decreasing price of NAND flash, NAND flash-based solid-state drive (SSD) has been widely used as a storage system in consumer electronics. Moreover, modern consumer SSDs usually adopt a multichannel parallel structure. Thus, how to fully utilize the internal parallelism through IO scheduling is a key problem. The existing IO schedulers fail to solve the following: 1) the utilization of flash translation layer information to optimize the internal parallelism is not sufficient; 2) the wear of flash memory is not considered when allocating write requests. This article proposes a Wear-aware Out-of-order Dynamic Scheduling Algorithm (WODSA). First, according to the information of the flash translation layer, the max-parallel-based scheduling strategy is proposed to schedule the read requests to maximize read parallelism. Second, the wear-aware dynamic write allocation strategy is proposed based on the idle/busy state and wear degree of channels and chips. WODSA allocates write requests to channels and chips with less wear preferentially in a maximized parallel manner to achieve write parallelism and active dynamic wear-leveling. Experimental results show that compared with existing IO schedulers and dynamic wear-leveling algorithms, WODSA can improve both the average response time and wear-leveling in block-level and channel-level.

Interference alignment (IA) is one of the most promising techniques to eliminate interference in multiuser multiantenna systems. Simultaneous wireless information and power transfer (SWIPT) technology is applied to harvest energy from radio frequency signals in green communications, while interference signal is assumed to be utilized as energy supply source in SWIPT. In this paper, an enhanced maximum signal to interference plus noise ratio (MAX-SINR) strategy with interference leakage power constraint is proposed, which realizes a tradeoff between information transmission and interference leakage in multiuser multiantenna SWIPT systems. Optimization problem is formulated and a three-step optimization solution is proposed. Finally, the problem can be transformed to a standard semi-definite programming (SDP) to obtain optimal power splitting factor and system sum-rate (spectral efficiency). Simulation results are presented to show that system sum-rate performance is enhanced with the increasing of receiving antenna numbers. The tradeoff between sum-rate and the harvested energy can be realized via the proposed IA strategy.

As an infrastructure-free positioning and navigation method, pedestrian dead reckoning (PDR) is still a research hotspot in the field of indoor localization. Step detection (SD) and stride length estimation (SLE) are two key components of PDR, and it is a challenging problem to apply SD and SLE to different walking patterns. Focusing on this problem, this paper proposes a robust SD and SLE method based on recognizing three walking patterns (i.e., Normal Walk, March in Place, and Quick Walk) using a smartphone. First, we propose a dynamic time warping–based peak prediction with zero-crossing detection to improve the SD accuracy. In particular, the proposed SD can accurately identify the starting and ending points of each step in the three walking patterns. Second, according to the extracted features of each step, a random forest algorithm with classification proofreading is used to recognize the three walking patterns. Finally, an improved SLE model is proposed for the different walking patterns to achieve a higher SLE accuracy. The experimental results show that, on average, the SD accuracy is about 97.9%, the recognition accuracy is about 98.4%, and the relative error of the estimated walking distance is about 3.0%, which outperforms those of the existing commonly used SD and SLE methods.

Non-orthogonal multiple access (NOMA) is a promising spectrally-efficient technology to satisfy the massive data requirement of the next-generation wireless communication networks. In this paper, we consider cooperative non-orthogonal multiple access (CNOMA) networks with relaying user selection, where a two-stage user selection scheme is adopted to optimize the received signal-to-noise ratio (SNR) of the weak user. We derive analytical expressions of the outage probability of the CNOMA users under two different types of channel estimation errors. Afterwards, we investigate the asymptotic characteristics the outage probability of the CNOMA systems in the high SNR regimes. Our results show that for the case of constant variance of the channel estimation error, the outage probability of each user is saturated and cannot be improved by increasing the transmit power of the access point. In contrast, there is no performance bottleneck of the outage probability for all the users when the variance of the channel estimation errors decease with SNR, whilst fully diversity gain is achieved by the weak user.

The classic demand-based flash translation layer (DFTL) algorithm is well-known since it can solve the contradiction between mapping flexibility and the size of mapping cache by dynamically loading mapping entries. However, DFTL failed to utilize the spatial locality and hot-cold characteristics of the request and had an inefficient mapping entry eviction scheme. This paper proposes an adaptive read-write partitioning flash translation layer algorithm (ARWFTL). First, the cache mapping table (CMT) is divided into the read CMT and the write CMT. The size of the two can be adaptively adjusted by sensing the characteristics of the upper workload and the read-write latency of the underlying flash page. Second, a priority eviction window is set at the tail of the write CMT to evict the clean mapping entry firstly. When there is no clean mapping entry in the priority eviction window, the tail mapping entry and other mapping entries that belong to the same translation page are clustered to write back into the translation page. Then, other written back mapping entries are set to be clean and the tail mapping entry is evicted. Third, a hot data window is set at the head of the write CMT to recognize the hot and cold data of write requests. Then, the hot and cold data are stored in different data blocks of flash to avoid hot and cold data entanglement and reduce valid page migrations in garbage collection. Experimental results show that, compared with DFTL, ARWFTL can reduce the translation page write counts, the valid page migration counts, the block erase counts, and the average response time by 92.8%, 47.7%, 31.7%, and 31.4%, respectively. In addition, ARWFTL is also superior to the other recent DFTL-based improved algorithms, and even exceeds the pure page-level FTL in some indicators.

The newly published High Efficiency Video Coding (HEVC) Standard has greatly enhanced the coding performance in comparison to its predecessors. However, HEVC also has high computational complexity, which limits its application. In this paper, we propose a fast Bayesian Decision based Block Partitioning (BDBP) algorithm for HEVC encoder. Firstly, the scene change detection based on average grey difference is used to divide the video sequence into the online learning phase and the fast partitioning phase. Secondly, in the online learning phase, the statistical parameters are extracted from coding units (CUs) in every depth to establish the Gaussian mixture models which are resolved by expectation maximization algorithm; in the fast partitioning phase, the conditional probabilities for CU to decide partitioning and non-partitioning are calculated. Finally, the minimum risk Bayesian decision rule is used to choose the decision with smaller risk, and the decision is regarded as the judgment of the current CU. Experimental results show that the proposed algorithm reduces the computational complexity of HM13.0 to 54.1% in encoding time with 0.92% increase in the BD-Rate and 0.05dB decrease in the BD-PSNR. Moreover, the proposed algorithm also demonstrates better performance over other state-of-the-art work.

Traditional distance-based location verification system (LVS) is ineffective for some attacks in sparse mobile ad hoc networks, e.g., the similar distance-based malicious (SDM) attack. In this letter, we propose to exploit radio irregularity to build a novel LVS. Our system detects attack based on the estimated difference of radio irregularity coefficients and the claimed locations of the malicious node and an assistant node. To the best of our knowledge, our system is the first-of-its-kind that can detect SDM attack and pollution attack with only the received signal strength indicator information transmitted by a detecting node to the suspicious malicious node and an assistant node. Simulation results demonstrate that our proposed system can detect the attacks that cannot be detected by traditional distance-based methods.

In the fog network with multiple terminals and fog nodes, how to make a tradeoff between energy consumption fairness among fog nodes (FNs) and task processing delay of terminal nodes (TNs) is still a challenging problem. To solve this problem, this paper proposes a Kuhn-Munkres (KM) based Fair Task Offloading (KFTO) scheme, which includes two optimization models: FN selection model and task offloading decision model. FN selection model employs the KM algorithm to obtain the optimal matching scheme between TNs and FNs that maximizes the total network potential. The second model is used to obtain the task size offloaded to FN that minimizes the task processing delay of TN while satisfying the energy consumption constraint. Numerical simulation results reveal that the proposed KFTO scheme achieves a satisfactory tradeoff between the energy fairness among FNs and the task processing delay of TNs.

Aiming at improving the firmware performance of NAND flash based solid-state drives, this paper proposes a hot data identification algorithm by fusing bloom filter and temporal locality, briefly as B2L, whose main contribution of B2L is to use cascade structure to make it have both advantages. Specifically. Firstly, the bloom filter is used to filter the real cold data, so that the probability of the remaining data being hot data becomes higher. Secondly, a temporal locality based two-level least recently used (T-LRU) lists is used to identify the true hot data. That is to say, the data hit in the hot list of T-LRU are identified as the true hot data. B2L can avoid the high false positive ratio problem of the bloom filter and effectively reduce the false positive ratio of T-LRU and the false negative ratio caused by false positives. Hence, B2L can improve the accuracy of hot data identification. The experimental result shows that in the case of using the direct address method as the baseline, compared with the state-of-the- art identification algorithms, B2L improves the accuracy of hot data identification by 60.4% on average.

As the newest video coding standard, High Efficiency Video Coding (HEVC) greatly enhances the encoding performance of H.264/AVC. However, HEVC also has high computational complexity, which limits application of this new standard. In this paper, we propose a fast DEA-based intra-coding algorithm, including block partitioning; prediction mode selection and edge offset (EO) class decision algorithms. The idea behind the proposed algorithm is to utilize the texture characteristics of the encoding image, which are quantified by dominant edge assent (DEA) and its distribution, to reduce the decision space. Specifically, for block partitioning, we propose the most possible depth range (MPDR) and employ DEA to determine whether the current coding block can use the MPDR to predict the partitioning depth or not; for intra-prediction mode selection, we use DEA and its distribution to reduce the range of prediction direction; for the EO class decision, we use DEA to determine the EO class of the sample adaptive offset. We integrate the proposed algorithm into the test model HM 13.0 and present a detailed comparative analysis. Experimental results show that the proposed fast DEA-based intra-coding algorithm reduces the computational complexity of HM 13.0 to about 46% in encoding time with 2.08% increases in the Biontegaard-Delta bitrate (BD-rate). Moreover, the proposed algorithm also demonstrates better performance over other state-of-the-art work.

Localization problem is an important and challenging topic in today's wireless sensor networks. In this paper, a novel localization refinement algorithm for LAEP, which is a range-free localization algorithm by using expected hop progress, has been put forward. The proposed localization refinement algorithm, called as CVLR, is based on position correction vectors and can resolve the LAEP's hop-distance ambiguity problem, which can lead to adjacent unknown nodes localized at the same or very close positions. CVLR can make full use of the relative position relationship of 1-hop neighboring nodes (called as CVLR1), or 1-hop and 2-hop neighboring nodes (called as CVLR2), to iteratively refine their localization positions. Furthermore, from localization accuracy and energy dissipation perspective, we optimize the communication process of CVLR2 and propose an energy-efficient improved CVLR. Simulation results show that the localization accuracy of CVLR1, CVLR2, and the improved CVLR are obviously higher than that of LAEP and DV-RND.

Node localization is one of the key technologies of WSN applications. In this paper, we propose a distributed weighted search-based localization algorithm (WSLA) and its refinement algorithm (WSRA) for wireless sensor network (WSN). In real applications, WSLA?+?WSRA need to run iteratively to achieve localization and position refinement of nodes. In each iteration of WSLA, every node obtains the coordinate and distance information of its 1-hop neighbors, and then employs weighted two-dimensional logarithmic search to compute its best estimated position; finally, every node estimates its coordinate and type according to the distribution of its best estimated positions. By analyzing experiment results of WSLA, we found some errors, and eventually propose WSRA that is based on geometrical relationship of neighbors. Finally, we compare the localization performance and complexity of WSLA?+?WSRA with those of MLE, RSOCP?+?NCSG and PSO, which are three state-of-the-art range-based localization algorithms, in different network scenarios (e.g., uniform topology, irregular C-shaped network and fading environment). The simulation results show that WSLA?+?WSRA have relatively high localization accuracy and low computational complexity compared with MLE, RSOCP?+?NCSG and PSO.

As the latest video coding standard, high efficiency video coding (HEVC) is a successor to H.264/AVC. To improve the coding efficiency of intra coding, HEVC employs a flexible quad-tree coding block partitioning structure and 35 intra prediction modes. The optimal prediction mode is selected through rough mode decision (RMD) and rate distortion optimisation (RDO) process. Due to the huge search space of all of the possible depth levels (CU sizes) and intra prediction modes, intra coding of HEVC is a very time-consuming and complicated process, which limits the application of HEVC. In order to reduce the intra coding complexity, we propose a fast mode decision algorithm for HEVC intra prediction which is based on dominant edge assent (DEA) and its distribution. The four DEAs in the directions of degree 0, 45, 90 and 135 are computed first; then, the dominant edge is decided according to the minimum DEA. Next, a subset of prediction modes in accordance with the dominant edge is chosen for the RMD process. The rule is as follows: When the standard deviation of DEA is distinctly small, we skip the RMD process and take the direct current (DC) mode and planar modes as the candidate modes for the RDO process; when the minimum DEA is distinctly small, we select seven modes as the candidate modes for the RMD process; otherwise, we select 11 modes for the RMD process. Lastly, the prediction unit (PU) size-based number of RDO candidate modes (3 for PU size 4?×?4 and 8?×?8 and 1 for the other PU sizes) is modified according to experimental analysis. Compared with HM 9.1, Shen's proposal and da Silva's proposal, which are two state-of-the-art fast intra mode decision algorithms, the experimental results reveal that the proposed algorithm can save 36.26, 13.85 and 20.81 % coding time on average with a negligible loss of coding efficiency, respectively.

This paper proposes an object oriented model scheduling for parallel computing in media MultiProcessors System on Chip (MPSoC). Firstly, the Coarse Grain Data Flow Graph (CGDFG) parallel programming model is used in this approach. Secondly, this approach has the feature of unified abstraction for software objects implementing in processor and hardware objects implementing in ASICs, easy for mapping CGDFG programming on MPSoC. This approach cuts down the kernel overhead and reduces the code size effectively. The principle of the oriented object model, the method of scheduling, and how to map a parallel programming through CGDFG to the MPSoC are analyzed in this approach. This approach also compares the code size and execution cycles with conventional control flow scheduling, and presents respective management overhead for one application in media-SoC.

It is necessary for stereoscopic video with vast data to be coded at low bit-rate to satisfy the constrained bandwidth. In this paper, a new coding method for stereoscopic video has been proposed to accomplish low bit-rate compression. Different from the common method that the resolution is reduced and magnified for depth video only, the proposed coding with asymmetric resolution is applied for both texture video and depth video. Conforming to the 3D extended standard of high efficiency video coding, the base view is coded at the full resolution but the dependant views are coded at the low resolution in this paper. The mean diversity based median filtering is proposed to decrease the video resolution while the interpolation filtering is utilized to restore the video from low resolution to high resolution. The experimental results demonstrate that the proposed method can obtain better coding performance including bit-rate reduction and rate distortion improvement than the anchor.

This paper proposes general software optimization techniques for embedded systems based on processors, which mainly include general optimization methods in high language and software and hardware co-optimization in assembly language. Then these techniques are applied to optimize our MP3 decoder, which is based on RISC32, a RISC core compatible with MIPSI instruction set. The last optimization decoder requires 48 MIPS and 49 Kbytes memory space to decode 128 Kbps, 44.1 KHz joint stereo MP3 in real time with CPI 1.15, and we have achieved performance increase of 46.7% and memory space decrease of 38.8% over the original decoding software.

With the rapid development of integrated circuit design technology and the processed tasks and data volumes growing, MPSoC is becoming increasingly popular in a variety of applications. In MPSoC design, parallelism is a very important issue, for example, how to realize task parallelism and data parallelism. Focusing on this issue, this paper analyzes the role of DMA and presents an ILP-Based DMA data transmission optimization algorithm to reduce the pipeline time when employing multi-stage pipeline scheduling method to solve task parallelism and data parallelism. The proposed ILP model integrates task allocation/schedule and data transmission and thus realizes the optimal parallelism of data transmission and data processing. In addition, we divide data transmission of ILP model into four cases: (1) DMA0, do not use DMA to optimize data transmission; (2) DMA1, use DMA to transmit data between SPM and off-chip memory; (3) DMA2, use DMA to transmit data between SPM and SPM, SPM and off-chip memory; (4) DMA3, use DMA to transmit and prefetch all data. Simulation results show that the ILP model with DMA3 can reduce the pipeline time 17.8% compared with that of the ILP model with DMA0.

Data allocation of on-chip scratch-pad memory is a key problem for the performance of embedded system employing SPM as on-chip data memory. Based on the solution to knapsack problem, we propose its knapsack model then employ dynamic planning method to give its optimal algorithm with the complexity of O(nC). Experiment results show that the method proposed in this paper can obtain the optimal result during static or dynamic data allocation of SPM.

This paper proposed a new bit-allocation algorithm based on linear prediction for AAC (advanced audio coding) audio encoder. Initial value of bit-allocation information of current audio frame is calculated by linear prediction algorithm using the information of previous two audio frames. Because the number of iteration for bit-allocation module is high correlated with initial value of bit-allocation information, the number of iteration can be decreased by properly setting initial value of bit allocation information such as global scale factor. Therefore it has improved audio encoding performance while decreasing computational complexity of bit-allocation module. Implementation results show that our approach has decreased the number of iteration and increased AAC encoding speed.

In many multimedia SOC (System on Chip), application software and data are stored either in on-chip memory or in Cache for efficient execution. Therefore, large amounts of on-chip memory increase the area and power dissipation of the whole chip. In order to reduce memory size and its power dissipation, parts of programs and data are stored in off-chip memory, and are loaded into on-chip memory while being used, which will increase the memory access time. So how to use the on-chip memory efficiently is a main problem in hardware and software co-design. This paper proposes approaches to memory optimization in SOC by using audio decoding program employed by MPEG-2 decoding chip as an example.

RISC-based processors have been extended into almost all kinds of embedded applications. These applications have different features thus require different processor architectures. Thus, we have developed a dual-core/dual-issue mixed micro-architecture processor named as RISC3202 which is based on two simple RISC cores. On the one hand, RISC3202 is an in-order dual-issue superscalar processor for single-thread applications. On the other hand, RISC3202 is a shared-memory dual-core processor for multiple-thread applications. The work mode of RISC3202 is configurable during running programs. Therefore, RISC3202 fits well for different features of target applications and its hardware usage rate is always high.

By using the media kernel algorithms to evaluate the performance of MDS-I, the first generation media extension set of RISC3200, we have found that MDS-I set has powerful media data processing ability but awkward media data providing ability. Then, focusing on this problem, we have proposed new media instructions, called as MDS-II, for high efficiency media data provision. The experiment results show MDS set of RISC3200, including MDS-I and MDS-II, can achieve about 2-5 speedups for media kernel algorithms compared with its MDF set. Therefore, we can conclude that the instructions for media data processing and for media data provision have the same position during designing the new media extension instruction set.

This paper presents an ISA model-based pseudorandom program generator, called as VirgoASM, for functional verification of RISC3200 processor. The kernel parts of VirgoASM are instruction generating models and test templates. In order to ensure the complete instruction generating space and the legality and validity of generated single instruction, instruction opcode and operand sets are built according to the function, syntax format and semantic requirements of instructions. Then 17 instruction generating models are constructed based on the Cartesian product of instruction opcode and operand sets. According to instruction generating models and verification plans, various types of test templates are created to guarantee the quality requirement of generated instruction sequences. At last, we demonstrate that how to use VirgoASM to generate test programs.

In MPEG2 MP@HL decoding chip, RISC core is used as both audio decoding and system decoding. In the paper, AC3 decoding is used to research the hardware/software co-design method. A new hardware/software co-design method is proposed. After running AC3 program on RISC core and getting the profile information of each function, the key operation is extracted and models are set up to extract special instructions. Finally, implementation of some special instruction is given. Results shows that the method have achieved performance increase and memory space decrease.

This paper describes instruction set extensions for accelerating audio processing on RISC-based core. Our former designed processor VIRGO is a 32-bit RISC-based processor. We have extended its instruction sets and designed its new version RISC3200. The extension instruction sets include: 1 sub-word parallelism arithmetic instructions, providing a form of SIMD parallel processing; 2 special arithmetic instructions for substituting frequently encountered fundamental RISC instruction sequences; 3 ancillary instructions aiming to efficient data preparation for 64-bit media register file. We have evaluated the performance of extension instruction sets by using kernel algorithms in MPEG-1/2 layer3 (MP3), MPEG-2/4 advanced audio coding (AAC), Dolby AC-3. The evaluation results show that the processor with extension instruction sets is capable of achieving from 1.8 to 3.6 speedups over the processor with basic RISC instruction sets for these audio kernel algorithms.

In order to solve the node localization problem in wireless sensor networks, we propose a novel distributed weighted search localization algorithm (WSLA) in this paper. The WSLA adopts a modified received signal strength indicator-based range model to estimate the distances between nodes, utilizes the results of a centroid localization algorithm as the search initial point, and employs a new weighted search method to compute the positions of nodes in a distributed and recursive manner. The key ideas of the WSLA include a node localization precision classification scheme, a processing scheme for special nodes, and weight-based searches. Compared with three state-of-art localization algorithms—namely, maximum likelihood estimation (MLE), edge-based second-order cone programming + nonconvex sequential greedy (ESOCP + NCSG), and particle swarm optimization (PSO)—the simulation results show that localization performance of the WSLA is superior to that of MLE, ESOCP + NCSG, and PSO.

The MediaSoC322IA consists of two fully programmable processor cores and integrates digital video encoder. The programmable cores toward a particular class of algorithms: the MediaDSP3200 for RISC/DSP oriented functions and multimedia processing, and the RISC3200 for bit stream processing and control function. Dedicated interface units for DRAM, SDRAM, Flash, SRAM, on screen display and the digital video encoder are connected via a 32-bit system bus with tie processor cores. The MediaSoC3221A is fabricated in a 0.18/spl mu/m 6LM standard-cell SMIC CMOS technology, occupies about 20 mm/sup 2/, and operates at 180 MHz. The MeidaSoC3221A are used to audio/video decoder for embedded multimedia application.