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An adaptive two-phase read strategy is proposed that allows reliable reads under high variability at a substantially lower energy, utilizing the idea of the conditional use of energy-costly variation-tolerance read. The proposed variation-tolerant design technique is developed for dealing with spatial variability while maintaining low read energy by using the conventional read with two-levels of reference voltages and the variation-tolerance read if a bit is not read out correctly by the conventional read. To achieve a two-phase read strategy, a sense amplifier (SA) is designed that performs both the energy-saving conventional read and the energy-costly variation-tolerant read. The energy overhead is significantly reduced by decreasing the use of variation-tolerant read, and the area overhead is minimized by reusing the conventional SA for the variation-tolerant read. The proposed circuit is evaluated using a compact spin-transfer torque magnetic RAM model, targeting an implementation in a 10-nm technology node. Results indicate that the proposed design strategy reduces read energy by 28.6% compared to the best-known variation-tolerant design with 3.7% area overhead assuming that a 1-bit cell is 20 $F^{2}$ and the number of rows is 1024.

As this research is a personal achievement with no company-related information, and there is no financial support for this paper from Qualcomm Technologies Inc [...]

Three-feature based automatic lane detection algorithm (TFALDA) is a new lane detection algorithm which is simple, robust, and efficient, thus suitable for real-time processing in cluttered road environments without a priori knowledge on them. Three features of a lane boundary - starting position, direction (or orientation), and its gray-level intensity features comprising a lane vector are obtained via simple image processing. Out of the many possible lane boundary candidates, the best one is then chosen as the one at a minimum distance from the previous lane vector according to a weighted distance metric in which each feature is assigned a different weight. An evolutionary algorithm then finds the optimal weights for combination of the three features that minimize the rate of detection error. The proposed algorithm was successfully applied to a series of actual road following experiments using the PRV (POSTECH research vehicle) II both on campus roads and nearby highways.

HYPRES is developing a prototype digital system comprising a Nb RSFQ analog-to-digital converter (ADC) and SiGe amplifiers on a commercial two-stage cryocooler. This involves the detailed thermal, electrical, and mechanical design of the ADC chip mount, input/output (I/O) cables, and electromagnetic shielding. Our objective is to minimize the heat load on the second (4 K) stage of the cryocooler, in order to ensure stable ADC operation. The design incorporates thermal radiation shields and magnetic shielding for the RSFQ circuit. For the I/O cables, the thermal design must be balanced against the acceptable attenuation of RF lines and resistance of DC bias lines. SiGe heterojunction bipolar transistor (HBT) signal conditioning circuits, placed on the first (60 K) stage of the cryocooler, will amplify the mV-level ADC outputs to V-level (e.g., ECL) outputs for seamless transition to room-temperature electronics. Cooling these HBT circuits lowers noise and improves their high-frequency performance. Demonstration of this prototype should lead the way to commercialization of high-speed digital superconducting systems, for such applications as wireless communication, radars, and switching networks.

An 8-phase 20 GHz PLL has been designed for a serial transceiver. The PLL has a wide locking range from 10 GHz to 20 GHz with a phase noise of -112 dBc/Hz at 10 kHz offset. The PLL uses a four-stage ring oscillator that has a wide tuning range with a feedforward interpolation topology for coarse frequency tuning and a varactor diode load capacitance variation for fine frequency tuning. The PLL is fabricated in 0.13-mum SiGe BiCMOS technology.

This paper presents the design of a voltage-controlled ring oscillator that has ultra wide tuning range of 12 to 23 GHz with hybrid control schemes. The voltage-controlled oscillator (VCO) uses a feedforward interpolation topology scheme and a varactor diode load capacitance variation scheme to control the oscillation. The measurement result of the VCO shows good linearity in frequency-voltage characteristics over the ultra wide tuning range.

A52-Gb/s 16:1 quarter-rate clocking transmitter for high-speed serial data transmission is designed to utilise 0.13-mum SiGe bipolar complementary metal-oxide-semiconductor (BiCMOS) technology. The quarter-rate transmitter consists of a 16:1 multiplexer (MUX), a voltage-controlled ring oscillator, a phase-locked loop (PLL), a pseudorandom data generator and an output amplifier. The voltage-controlled ring oscillator has a wide tuning range from 11 to 22 GHz with feedforward loop and delay interpolation. A continuous model of a third-order PLL is developed and used to optimise loop filter parameters and to estimate the PLL performance in a simulation. The PLL achieves a low phase noise of -124.6 dBc/Hz at 1 MHz offset. The 16:1 MUX features quarter-rate clock multiplexing with multi-phase voltage-controlled oscillator clocks. In the design of a 16:1 MUX, an edge-channelling 4:1 MUX is used to alleviate a duty cycle and a jitter problem.