1. The ASIC Design and Verification Based on Verilog HDL
- Author
-
Yong Gang Luo and Yu Ying Yuan
- Subjects
Computer science ,Formal equivalence checking ,General Engineering ,Logic synthesis ,Application-specific integrated circuit ,Computer architecture ,Netlist ,Verilog ,Design process ,Hardware_ARITHMETICANDLOGICSTRUCTURES ,Engineering design process ,Hardware_REGISTER-TRANSFER-LEVELIMPLEMENTATION ,computer ,Hardware_LOGICDESIGN ,computer.programming_language ,Register-transfer level - Abstract
Logic design and verification is the frontend of ASIC (Application Specific Integrated Circuit), and is a very important design part during the design process of ASIC. A Verilog HDL design case-2×2 SDH digital cross-connect matrix is provided to illustrate the entire design process including logic-level description, verification and synthesis based on the frontend tools of Synopsys. After that a gate-level netlist conforming to the design requirements can be obtained.
- Published
- 2012
- Full Text
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