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Sub-threshold characteristics of the dual material gate 4H-SiC MESFET (DMGFET) are investigated and the analytical models to describe the drain-induced barrier lowering (DIBL) effect are derived by solving one- and two-dimensional Poisson's equations. Using these models, we calculate the bottom potential of the channel and the threshold voltage shift, which characterize the drain-induced barrier lowering (DIBL) effect. The calculated results reveal that the dual material gate (DMG) structure alleviates the deterioration of the threshold voltage and thus suppresses the DIBL effect due to the introduced step function, which originates from the work function difference of the two gate materials when compared with the conventional single material gate metal—semiconductor field-effect transistor (SMGFET).

A lower doped layer is inserted between the gate and channel layer and its effect on the performance of a 4H-SiC Schottky barrier field-effect transistor (MESFET) is investigated. The dependences of the drain current and small signal parameters on this inserted gate-buffer layer are obtained by solving one-dimensional (1-D) and two-dimensional (2-D) Poisson's equations. The drain current and small signal parameters of the 4H-SiC MESFET with a gate-buffer layer thickness of 0.15 μm are calculated and the breakdown characteristics are simulated. The results show that the current is increased by increasing the thickness of the gate-buffer layer; the breakdown voltage is 160 V, compared with 125 V for the conventional 4H-SiC MESFET; the cutoff frequency is 27 GHz, which is higher than 20 GHz of the conventional structure due to the lower doped gate-buffer layer.

A new analytical model to describe the drain-induced barrier lowering (DIBL) effect has been obtained by solving the two-dimensional (2D) Poisson's equation for the dual-channel 4H-SiC MESFET (DCFET). Using this analytical model, we calculate the threshold voltage shift and the sub-threshold slope factor of the DCFET, which characterize the DIBL effect. The results show that they are significantly dependent on the drain bias, gate length as well as the thickness and doping concentration of the two channel layers. Based on this analytical model, the structure parameters of the DCFET have been optimized in order to suppress the DIBL effect and improve the performance.

An improved structure of silicon carbide metal—semiconductor field-effect transistors (MESFET) is proposed for high power microwave applications. Numerical models for the physical and electrical mechanisms of the device are presented, and the static and dynamic electrical performances are analysed. By comparison with the conventional structure, the proposed structure exhibits a superior frequency response while possessing better DC characteristics. A p-type spacer layer, inserted between the oxide and the channel, is shown to suppress the surface trap effect and improve the distribution of the electric field at the gate edge. Meanwhile, a lightly doped n-type buffer layer under the gate reduces depletion in the channel, resulting in an increase in the output current and a reduction in the gate-capacitance. The structural parameter dependences of the device performance are discussed, and an optimized design is obtained. The results show that the maximum saturation current density of 325 mA/mm is yielded, compared with 182 mA/mm for conventional MESFETs under the condition that the breakdown voltage of the proposed MESFET is larger than that of the conventional MESFET, leading to an increase of 79% in the output power density. In addition, improvements of 27% cut-off frequency and 28% maximum oscillation frequency are achieved compared with a conventional MESFET, respectively.

A novel structure of 4H-SiC MESFETs is proposed that focuses on surface trap suppression. Characteristics of the device have been investigated based on physical models for material properties and improved trap models. By comparing with the performance of the well-utilized buried-gate incorporated with a field-plate (BG-FP) structure, it is shown that the proposed structure improves device properties in comprehensive aspects. A p-type spacer layer introduced in the channel layer suppresses the surface trap effect and reduces the gate-drain capacitance (Cgd) under a large drain voltage. A p-type spacer layer incorporated with a field-plate improves the electric field distribution on the gate edge while the spacer layer induces less Cgd than a conventional FP. For microwave applications, 4H-SiC MESFET for the proposed structure has a larger gate-lag ratio in the saturation region due to better surface trap isolation from the conductive channel. For high power applications, the proposed structure is able to endure higher operating voltage as well. The maximum saturation current density of 460 mA/mm is yielded. Also, the gate-lag ratio under a drain voltage of 20 V is close to 90%. In addition, 5% and 17.8% improvements in fT and fmax are obtained compared with a BG-FP MESFET in AC simulation, respectively. Parameters and dimensions of the proposed structure are optimized to make the best of the device for microwave applications and to provide a reference for device design.