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In this paper, we investigate the relationship between size, shape, and the performance of the voltage-controlled magnetic anisotropy (VCMA)-based magnetic tunnel junctions (MTJs) suitable for gigabit scale MRAMs with 10 years of retention time. A Fokker–Planck simulation framework is developed to model the magnetization dynamics in the presence of thermal noise. Here, we numerically show that the optimization of the MTJ geometry can significantly improve the performance of the VCMA-based MTJs. Using an elliptical MTJ with aspect ratio (AR) of 3 reduces the required supply voltage and energy consumption by 80.7% and 92%, respectively, compared to a circular MTJ when the minimum feature size is 50 nm. The design requirements on the VCMA coefficient, ${\xi }$ , are also reduced by 67%. However, the influence of AR is observed to diminish with reduction in the minimum feature size of the MTJ. For instance, when the minimum feature size is 20 nm, the required supply voltage and energy consumption reduce only by 60.29% and 65.30%, respectively. We, then, perform a comprehensive scaling analysis on the VCMA-based MTJs by varying size, geometry, and ${\xi }$ of the MTJs. The predicted scaling trends are then compared with those of the STT MTJs. [ABSTRACT FROM AUTHOR]

Resistive random access memory (ReRAM), a new emerging nonvolatile memory technology based on changes in electrical resistivity of a dielectric film, offers promising advantages such as scalability, fast switching, and low operation voltage. However, for ReRAM to become a successful technology, it is necessary to accurately control the stochastic nature of the conductive nanoscale filaments (CNFs) that governs the resistive switching (RS) behavior of the device and limits its long-term stability and reliability. In this paper, we developed a highly scalable nanostructured/textured electrode that is composed of an array of Al nanotips based on an anodic aluminum oxide template. The nanotips improve the RS characteristics by intensifying the electric field at the apex of each nanotip which is demonstrated using numerical simulations. The localized electric field induces the repetitive nucleation/ formation/rupture of the CNFs in a more controlled fashion compared to a flat Al electrode. As a result, the nanotip sample exhibits uniform and reduced forming/reset voltages as low as 4.70 ± 0.98V/1.00 ± 0.19 V, stable endurance, and long-term retention. As a result, we were able to achieve ultralow-power and error-free operation of 100 cells covering a large area, significantly demonstrating improved uniformity and reliability compared to devices made using flat Al electrodes. This universal bottom-up strategy of self-organized nanostructured-electrodes provides a pathway toward large-scale, highly reliable, and RS memory devices. [ABSTRACT FROM AUTHOR]

The voltage ratings for dc transmission and distribution are not currently standardized because cable technology is advancing rapidly and therefore a low step-ratio dc–dc converter at multi-megawatt scale is a crucial technology for combining point-to-point dc links into multi-terminal networks. This paper presents a modular multilevel dc–dc converter configuration with only a single stack of half-bridge sub-modules (SM) and a resonant tank. The power processed through the stack is a small fraction of the throughput power if the step ratio is small ($1 - {\boldsymbol{v}_{\boldsymbol{L}}}/{\boldsymbol{v}_{\boldsymbol{H}}}$). Detailed analysis shows the required semiconductor ratings are much smaller compared to the front-to-front MMC and modular converters derived from standard dc–dc topologies. Further, the requirement for SM capacitive energy storage is also significantly less than those converters. The theoretical analysis and the operating principles have been verified by full-scale simulation examples and experiments with a down-scaled prototype. The SMs are operated with an adjustable phase shift to create a high frequency excitation across the resonant tank for further volume reduction. The SM capacitors self-balance without the need for switching pattern adjustments and the resonant operation provides soft switching for all power switches to increase efficiency. [ABSTRACT FROM AUTHOR]

This paper presents an accurate steady-state initialization method for electromagnetic transient (EMT) models of modular multilevel converters (MMCs). The proposed method uses steady-state arm voltages and currents to initialize internal electrical variables and control systems of the converter, including capacitor voltage and gating signals of each sub-module. In addition to typical voltage source converter upper level control, MMC specific controls are also considered, including circulating current control, dc ripple control, and capacitor voltage balancing algorithm. EMT simulations on 101-level and 401-level MMC-HVDC systems confirm the accuracy of the proposed method. [ABSTRACT FROM AUTHOR]

This paper discusses the sensitivity of programmable logic controllers (PLCs) to voltage sags based on mechanistic analysis and numerous tests. First, the sag sensitivity caused by different values of rated working voltage is shown through an analysis of the power supply and discrete input/output modules of PLCs. Second, a detailed sag-tolerance experimental scheme is proposed, and PLC sensitivity curves that differ from early curves are established through several experimental tests. Experiments are conducted with nine typical PLCs. The sensitivity of the power supply and discrete input modules are researched first, and then, the effect of the key characteristics of voltage sag, namely, magnitude, duration, points-on-wave of sag initiation, odd harmonics, multiple sags, and continuous sags, is tested. The uncertain area of the PLC sag tolerance is identified after intensively processing the extensive experimental data and curve fitting. A more accurate sag influence assessment for PLCs can be made with the given curves compared to the early curves. Furthermore, experiments have revealed that certain PLCs may work in an uncertain status during voltage sags. The reason and the method of elimination with the proper choice of dc bus capacitance for PLCs are also analyzed. [ABSTRACT FROM AUTHOR]

This paper proposes and describes in detail a new approach to the design of very compact active microwave compressors capable of providing rectangular pulses of up to 100 ns. The approach consists in using a storage cavity, which comprises linear waveguide sections connected by tees such that the cavity geometry can be 2-D or 3-D or can be variable to allow direct space-saving integration of a compressor into a microwave source. Also presented are the scattering matrix data on uniform wave propagation along the storage cavity with little reflection and on conditions necessary for such uniformity. The S-band experiments demonstrate the capability of storage cavities with two and three parallel waveguide sections of about 1 m long to produce rectangular pulses of duration 5, 15, and 25 ns with a power gain and output power of about 16 dB, 80 MW; 15 dB, 60 MW; and 13 dB, 40 MW, respectively. Our estimates suggest that 12 waveguide sections can provide a rectangular pulse of 100 ns with a power gain 10 dB. [ABSTRACT FROM AUTHOR]

In this paper, a high-voltage unipolar pulse power generator is introduced for electroporation applications. Operating principle of the proposed structure is based on the buck–boost (BB) converter. The generator is comprised of parallel modules connected to the converter through an SCR and is supplied by a low-voltage dc source. Each module consists of an insulated gate bipolar transistor (IGBT), two diodes, and a capacitor. In fact, the proposed topology is a combination of the Marx generator and BB (MG-BB) converter. In comparison with other modular MG-BB structures, the proposed topology achieves interesting advantages including simpler structure, reduction of IGBTs voltage rating, and reducing number of components (inductors and switches). In order to clarify the features of the proposed structure, it has been compared with other unipolar MGs considering different aspects including the number of circuit components, number of required input supplies, amplitude of the output pulse, and the maximum voltage across switches and diodes. To validate the effectiveness of the structure, simulation and experimental results are presented. The results confirm that the proposed topology is capable of generating unipolar pulses with desirable amplitude and repetition frequency using a low-voltage dc supply. [ABSTRACT FROM AUTHOR]

The switched shunting resistor circuit is a classical and practical passive equalization scheme that nevertheless suffers from the voltage imbalance after the charging process. It results from the discrepancy of the shunting resistor and the physical characteristics of supercapacitor (SC) cells. In this paper, the distributed voltage equalization control strategies with the proportional-integral (PI) observer for the switched shunting resistor circuit are analyzed and compared. First, the charging and equalizing system is modeled as the switched system and the system observability is proved. The decentralized control and consensus control are analyzed and their shortages are presented. Then, the leader–follower cooperative control is proposed to improve the charging time while keeping the equalization performance. Meanwhile, the PI observer is designed to estimate the internal capacitance voltage of an SC precisely to avoid the effect of equal series resistance. The control convergence is proved by using the Lyapunov stability and switched system theory. The experimental results show that the proposed method has much superiority and wide applicability than the existing methods for equalizing voltages of SCs. [ABSTRACT FROM AUTHOR]

This paper presents a new islanding detection method for synchronous distributed generation (DG). The proposed method is developed based on the combination of rate of change of exciter voltage (RCEV) and open–close circuit breaker (OCCB) at a DG connection point. Whenever the RCEV parameter is not sufficient enough to detect an islanding condition efficiently and correctly, the OCCB strategy will be triggered. The proposed OCCB strategy sends a switching command to one phase of the three-phase circuit breaker (CB), which connects the DG to the grid. In this way, the CB will be immediately opened and then closed. This switching condition will cause a variation in the value of RCEV. This variation is small for the conditions when DG operates in parallel with the main grid, whereas it will be large during the occurrence of islanding. The implementation of the proposed strategy is cost-effective because it only uses the CB at the DG output and does not require any extra equipment. The proposed approach is tested on two different systems including a hypothetical power system and the IEEE 33-bus test system in MATLAB/Simulink environment. The simulation results show that the proposed method eliminates the nondetection zone and also reveals high accuracy compared with previously introduced methods. Moreover, it has been proved that the performance of the proposed approach is not affected by DG capacity, DG location, the number of DG units, as well as network configuration. [ABSTRACT FROM AUTHOR]

In this paper, performances on two kinds of aggregated flyback microinverters are compared in aspect of harmonic resonances, which are controlled by current feedback control and peak current control. Based on the Norton models of flyback microinverters obtained by a small-signal modeling approach, potential harmonic resonances with the grid are analyzed. Following that, an impedance-based stability criterion is proposed, where the resonance frequency can be calculated and predicted based on the derived Norton models and the system admittance matrix of aggregated microinverters. After comprehensive analysis and comparisons, it is found that the peak-current-control-based flyback microinverters has better performance on damping the harmonic resonances than the current feedback controlled one. Simulations and experiments are carried out for verifying the effectiveness of the presented models and the correctness of the analysis results. [ABSTRACT FROM AUTHOR]

This paper presents a hybrid supply modulator (SM) including a buck-boost (BB) converter, which has wide battery operating range for cellular envelope tracking (ET) applications. The proposed SM supports both ET and average power tracking (APT) mode depending on the power amplifier (PA) output power level. The output voltage swing of SM is boosted up to 4.5 V by the integrated BB converter as a supply of a linear amplifier. The dynamic-controlled BB output increases ET operating range, whose efficiency is higher than that of APT, by scaling down the supply voltage of the linear amplifier according to the PA output power level. A selective supply voltage of a switching amplifier and a reverse current sensing circuit are employed to prevent the reverse current through the power inductor of the switching amplifier. The proposed automatic current ratio controller between the linear amplifier and the switching amplifier provides the robust performance against the battery voltage variation of 3.2–4.6 V. A programmable bias current of the class-AB output buffer and a programmable hysteretic comparator are employed to achieve the optimum efficiency and bandwidth depending on the operating signal bandwidth. Optimal control for low signal bandwidth applications such as voice over Long-Term Evolution (LTE) with the selective notch filter provides the maximum efficiency of 88.2% with −135 dBm/Hz output noise. The proposed SM supports the LTE 20-MHz envelope signal with 78% efficiency at 800-mW output. Adapting the designed SM to frequency-division duplex Band3 radio frequency PA, the implemented ET-PA achieves the power added efficiency of 41.6% at 27-dBm PA output power while achieving −40 dBc of E-UTRA ACLR and −137 dBm/Hz of receiver band noise. The chip is implemented in the 0.13- $\mu \text{m}$ CMOS process, and the die size is 5 mm2. [ABSTRACT FROM AUTHOR]

In this paper, a novel space-vector pulsewidth modulation technique for a five-level active neutral-point clamped (5L-ANPC) inverter is proposed to eliminate the common-mode voltage (CMV). For the 5L-ANPC inverter, which produces a good output voltage performance and lowdv/dt, the total 125 voltage vectors can be generated, among which the proposed scheme employs only 19 voltage vectors producing a zero CMV. Due to the limitation of voltage vectors selected, the dc-link capacitor voltages of the 5L-ANPC inverter cannot be balanced by themselves. Therefore, the capacitor voltages of the inverter should be controlled by choosing the redundant switching states appropriately. The validity of the proposed modulation scheme has been verified by simulation and experimental results. [ABSTRACT FROM AUTHOR]

High step-down voltage conversion is necessary to bridge the voltage gap between main power converters and low-voltage auxiliary electronics in power conversion systems. Switched capacitor converters (SCCs) are an attractive candidate as a high step-down converter, but their poor voltage regulation capability may limit their applications. Pulsewidth modulation (PWM) SCCs with adjustable high step-down voltage conversion are proposed in this paper. The proposed PWM SCCs can be derived from traditional SCCs by replacing an energy transfer capacitor with a switched-capacitor-inductor (SCL) cell that comprises inductors, capacitors, and diodes to realize PWM-controllable voltage conversion. The voltage step-down ratio of the proposed PWM SCCs is not only PWM controllable but also adjustable with structures of SCCs and SCL cells. Two representative PWM SCCs were taken as examples to perform the operational analysis. The prototypes of both representative PWM SCCs were built and tested to demonstrate the proposed concept. [ABSTRACT FROM AUTHOR]

Common-mode voltage (CMV) is known as a major cause of premature motor failures. The form and amplitude of the CMV generated by any converter depends on both the circuit topology and modulation technique. Among single stage ac–ac converters employed in drive applications, the Z-source ultra sparse matrix converter (ZSUSMC) is a desirable choice due to reduced number of switches in its structure and voltage boosting capability. Based on these considerations, this paper aims to: 1) theoretically determine and compare the CMV of the ZSUSMC with four well-known impedance networks, namely, cascaded, switched-inductor, quasi, and series, in its structure and 2) propose modulation techniques for CMV reduction in the ZSUSMCs. To this end, first, it is shown that the ZSUSMC, depending on the impedance network used in its structure, provides more freedom to choose from redundant switching states compared to the ultra sparse matrix converter. Then, by taking advantage of this feature, novel modulation strategies that attenuate the CMV without affecting the boosting capability are developed. The proposed modulation schemes are based on avoiding the switching states most contributing to the CMV during a switching period. Through hardware-in-the-loop studies, the effectiveness of the proposed modulation strategies in reducing the CMV of the ZSUSMCs is verified. [ABSTRACT FROM AUTHOR]

In voltage-source inverters (VSIs), dead time is used to prevent shoot-through over switching devices. However, the existence of the dead time will distort the output phase current, which degrades the performance of the inverter as well as influences the common-mode voltage (CMV), particularly in CMV elimination relevant modulation schemes, such as zero-common-mode (CM) pulsewidth modulation (PWM)-based paralleled inverters. In the light of the situation that the normal sampling-based dead-time compensation (DTC) methods are often disturbed by the current ripple, this paper introduces a novel DTC method for the VSI, which can mitigate the impact of the current ripple and improve the accuracy of DTC. The proposed method deduces the real-time current ripple, which can reconstruct the actual trajectory of phase-leg currents, and the peak values corresponding to rising and falling edges for PWM signals can be predicted. In this way, DTC can be implemented based on the direction of relevant instantaneous switching currents and finally improves the accuracy. Especially, the current-ripple-prediction-based DTC can help to improve the CMV distortion caused by the dead time for paralleled inverters with zero-CM PWM. Simulation and experimental results are provided to validate that the proposed method can be applied to different topologies and modulation schemes with good performance. [ABSTRACT FROM AUTHOR]

This paper proposes a Class-DEMtuned power amplifier. The proposed amplifier achieves zero-voltage switching (ZVS), zero-voltage derivative switching (ZVDS), and zero-current switching (ZCS) at turning-on, and ZVS, ZVDS, ZCS, and zero-current derivative switching at turning-off. Therefore, the switching losses are extremely low, which is suitable for high-frequency operation. Moreover, the switch voltage stress is low, which is no more than its input voltage. A proposed amplifier was designed, built, and tested. The measured power conversion efficiency was 93.2% under the condition of the main input voltage of 46.8 V, the operating frequency of 1 MHz, and the output power of 4.87 W. [ABSTRACT FROM AUTHOR]

The power conditioning interface circuit plays a crucial role in the energy harvesting (EH) capability enhancement in piezoelectric EH (PEH) systems. The principle of most existing synchronized switch circuits for PEH enhancement was summarized under the recently introduced synchronized multiple bias-flip (SMBF) model. The optimal bias-flip strategy derived from SMBF provides valuable insights for future circuit development. Based on such theoretical foundation, this paper implements a new interface circuit called theparallel synchronized triple bias-flip(P-S3BF) for further boosting the harvesting capability beyond the state-of-the-art solutions. By sophisticatedly allocating more bias-flip actions, it makes the best compromise between higher extracted power and lower dissipated power for power conditioning, toward maximum net harvested power. Moreover, the bias voltage reference in P-S3BF is self-contained and self-adaptive. Compared to the other existing solutions involving active voltage manipulations, these two conveniences brought in by P-S3BF are the most significant and necessary features, which facilitate the practical stand-alone implementation of P-S3BF under different periodic vibrations. Experimental result shows that, with the piezoelectric cantilever in use, which vibrates at a constant deflection magnitude, the P-S3BF circuit harvests 24.5% more power than its single bias-flip counterpart, the extensively studied parallel synchronized switch harvesting on inductor; and 287.6% more power than its null bias-flip counterpart, the standard EH bridge rectifier. [ABSTRACT FROM AUTHOR]

Owing to the operational characteristic of a Vienna rectifier, it is found that the traditional modulation method would result in the current distortion. This paper, therefore, proposes a novel zero-sequence component injection modulation method for improving the input quality of the Vienna rectifier with balanced or unbalanced dc-link voltages. In specific, the degree of unbalanced dc-link voltages increases the size of abnormal regions in a slant and asymmetrical space vector diagram, which leads to more serious current distortion. The proposed method identifies the abnormal intervals by average duties accurately without detecting the position of the reference vector. Considering the operational characteristics, three-phase compensation components are calculated respectively depending on an unbalanced factor and added to three-phase average duties in abnormal intervals. As a result, the current harmonics of the Vienna rectifier are mitigated significantly with balanced or unbalanced dc-link voltages. The effectiveness and the performance of the proposed zero-sequence component injection method for the Vienna rectifier are verified by simulation and experiments. [ABSTRACT FROM AUTHOR]

The three-phase four-wire inverter with split dc-link capacitors can supply unbalanced loads. For the purpose of reducing the filter inductors, a neutral inductor could be introduced into the neutral line. This paper analyzes the operation principle of the three-phase four-wire inverter with split dc-link capacitors when a neutral inductor is introduced. It is illustrated that the neutral inductor can reduce the zero-sequence switching harmonics in the voltages between the phase-leg midpoints and the output neutral point, thus the filter inductors can be reduced. The optimized design of the neutral inductor and filter inductors is proposed with the considerations of the inductor current ripple, the ability of supplying unbalanced loads, and the total energy stored in the inductors. The equivalent circuits of the three-phase four-wire inverter with split dc-link capacitors and neutral inductor is derived in the α–β–0 frame, and the zero-axis voltage regulator is modified to suppress the third-order harmonic in the zero-sequence current caused by the deadtime of the drive signals for the power switches. Finally, the experimental results from a 9-kW prototype are provided to prove the effectiveness of the proposed optimized design of the neutral inductor and filter inductors and the control strategy of the inverter. [ABSTRACT FROM AUTHOR]

In this paper, a family of step-up resonant switched-capacitor converters (RSCs) with a continuously adjustable conversion ratio is proposed based on the Cuk dual-resonance core (DRC) featuring two resonant paths. By adopting the on-time fixed frequency modulation, the two resonant paths can conduct simultaneously and satisfy the charge balance of the flying capacitor during the overlapping period. As a result, the conversion ratio—upper bounded by two determined by the circuit configuration—can vary continuously and efficiently even at the light load condition (1/10 of the rated power). A comprehensive analysis—the operation principle, voltage-gain curve, and voltage/current stresses—about the DRC is given. In addition, the Cuk DRC was extended to the series–parallel switched-capacitor converter (SCC), Fibonacci SCC, and voltage doubler to form a family of step-up RSCs, whose voltage-gain curves of different topologies are derived. Moreover, a characteristic comparison between the Cuk DRC and the traditional “direct” and “indirect” resonant core is given. Then, a 48 to 62–94.6 V resonant core with peak efficiency 97.8% and maximum power 120 W under the open loop condition was built. The analyses were verified by both experimental and simulation results. [ABSTRACT FROM AUTHOR]

In this paper, a modified selective harmonic mitigation pulse amplitude modulation (SHM-PAM) is presented to be capable of canceling all triplen harmonic orders and suitable for single-phase application of five-level type of voltage source inverters. To this end, a new constraint is established for the two switching angles (α1, α2) to derive the new formula for the harmonics’ amplitude, which results in self-elimination of all triplen harmonics (e.g., 3rd, 9th, 15th, …). The fifth and seventh harmonic orders are mitigated through normal operation of the proposed SHM-PAM technique. It is also shown that the proposed technique is extendable to other multilevel voltage waveforms and a flowchart of self-elimination of all triplen harmonics has been presented. Mathematical analysis supported by experimental investigations show the desired performance of the proposed SHM-PAM algorithm on a two-cell single-phase cascaded H-bridge inverter as a typical five-level configuration in dealing with linear and nonlinear loads. Then, it is demonstrated that the maximum number of harmonic orders would be controlled with the minimum number of available angles in a low switching frequency voltage waveform. [ABSTRACT FROM AUTHOR]

This paper presents the design, fabrication, and characterization of a module-level spring-interconnected stack power module for power semiconductor devices. The benefit of multilayer design capability offered by a low-temperature cofired ceramic (LTCC) substrate is used for this module-level power module structure. A half-bridge configuration is demonstrated using two standalone wire-bondless power modules with parallel power semiconductor devices stacked on top of each other. An interconnection scheme consisting of conductive copper clamps and a spring-loaded LTCC interposer is adopted to form a module-level 3-D package structure. The low loop and stray parasitic inductances for the 3-D stack are achieved using an antiparallel current path configuration along with the wire-bondless approach and a low-profile spring interposer. For demonstration, silicon insulated-gate bipolar transistors and silicon carbide (SiC) Schottky barrier diodes are used to fabricate the hybrid 3-D stack. Static and transient electrical characteristics of the 3-D stack power module are evaluated through simulation and experimental measurements and compared with a wire-bonded half-bridge power module to investigate the performance improvement in switching characteristics of the 3-D module. High-voltage isolation test, leakage current test, and thermal cycling are performed to validate the spring-interconnected module-level 3-D stack structure. [ABSTRACT FROM AUTHOR]

Three-phase bridge converter is popular in ac–dc power conversion. The conventional sensor control with inner current loop and outer voltage loop is often used to control the three-phase bridge converter. Many three-phase sensorless control methods had been proposed to control the bridge converter with considering the inductance and inductor resistance. In this paper, the voltage drop of the power semiconductor is first considered in the proposed three-phase current sensorless control method. At first, the dynamic behaviors of three-phase bridge converter for power factor correction (PFC) applications are studied, and its equivalent three-switch model is developed. Based on this developed model, three-phase current sensorless control with only voltage controller is proposed. Additionally, the voltage-loop transfer function of PFC bridge converter controlled by the proposed method is modeled, and the result is helpful to obtain the controller parameter. The proposed control method is implemented on the DSP-based platform for evaluation. Finally, the provided simulation and experimental results demonstrate the performance of the proposed method. [ABSTRACT FROM AUTHOR]

This paper proposes a transformerless line-interactive uninterruptible power supply (UPS) with low ground leakage current. A high-efficiency bidirectional inverter is suggested, which performs the line-interactive UPS functions with low ground leakage current. It has a full-bridge inverter and a bidirectional switch, which operate with the unipolar pulsewidth modulation. Because the bidirectional switch operates at the line-frequency, switching losses can be lower than the previous transformerless inverters. As the inverter operates, the parasitic capacitance between the inverter and the ac voltage ground is clamped to zero voltage for a positive line cycle and to the ac voltage for a negative line cycle, respectively. Thus, the parasitic capacitance can be prevented from being charged or discharged, which ensures the absence of the ground leakage current. The operation modes of the proposed system are described. The control schemes are presented to design the proposed inverter for the line-interactive UPS. Experimental results for a 2.0 kW prototype are discussed to verify the performance of the proposed system. [ABSTRACT FROM AUTHOR]

This paper presents a passivity-based control (PBC) scheme for the switched reluctance generator (SRG) in small-scale wind energy conversion systems for dc microgrid applications. The main objective is to stabilize the output voltage in case the system supplies constant power loads (CPLs) and operates with maximum power point tracking (MPPT). Stability improvement and dc-link ripple reduction in the presence of CPLs is achieved using system-level modeling of SRG-based dc microgrid through the Euler-Lagrange system (ELS) from the viewpoint of the machine physical structure. Compared with other control methods, the proposed MPPT method based on passivity-based speed controller employs the back electromotive force (EMF) in the generation process as a position-dependent voltage source to overcome the major challenge of SRG complicated uncertain dynamic model. To deal with the time-varying inductance and back EMF of SRG, an adaptation mechanism is incorporated in the proposed adaptive PBC and the control design is constructed by using the Lyapunov theorem where the closed-loop stability is ensured. The effectiveness of the proposed method in avoiding instability effects of SRG and CPL with voltage ripple reduction and precise wind turbine speed tracking is investigated with simulation results and validated with experimental by using a four-phase, 8/6 SRG drive system. [ABSTRACT FROM AUTHOR]

In this paper, a new nonisolated high step-up dc–dc converter is proposed. Active–passive inductor cells (APICs) are used to extend the topology. The ability to achieve high gains is the main merit of the proposed topology. The proposed converter operates based on parallel charging and series discharging of the inductors. The converter also achieves high step-up voltage gain with appropriate duty cycle and low voltage and current stress on the power switches and diodes. The proposed converter is analyzed in operation modes. The main parameters of the converter such as voltage gain, voltage stress of semiconductor devices are calculated to compare with other structures. Considering the output voltage ripple and filter size, the proposed converter is designed. Moreover, the losses and efficiency of the converter are calculated. The performance of the proposed converter is validated by experimental results. [ABSTRACT FROM AUTHOR]

Single-phase autoreclosing (SPAR) is among the alternatives for mitigating the many harmful effects that a line-to-ground fault in a transmission line (TL) may cause. This procedure basically consists of opening the compromised phase, waiting a preset time span (dead time), and recomposing the previously isolated phase. In the vast majority of SPAR implementations, the open phase switching proceeds with no guarantee of whether the TL is still faulted. Switching the open phase into a fault might represent a more severe threat to the system than simply disconnecting the TL in the first place. Hence, in an effort to ensure higher levels of operational reliability to SPAR, the present paper offers a new methodology to check the soundness of the open phase during the dead time before its reclosing. First, the method's fundamental concepts are exposed. Second, a huge number of steady-state tests are presented, for which both the system topology and its operative condition were varied. To conclude, the SPAR is simulated in the time-domain with the most critical condition found in the steady-state analysis. The proposed strategy was capable of correctly identifying whether the system was faulted in every performed simulation. [ABSTRACT FROM AUTHOR]

A novel scheme is proposed to monitor the operation of capacitors scattered in MV distribution systems. It first codes each capacitor with a distinctive switching character by setting a unique combination of a three-phase switching order and time interval. As a result, the transient of the three-phase reactive power during capacitor switching will appear in a unique way. Then, the reactive power disturbances monitored in the substation are decoded to identify which capacitor is being switchedonandoff. A detailed decoding method is developed to realize this identification without being impacted by the switching interference of loads and other reactive power compensation devices. Moreover, the implementation of the proposed scheme in the field is elaborated, and the resultant three-phase voltage unbalance is analyzed in this paper. Compared with existing methods, this scheme only requires one power quality monitor located at the substation to monitor the operations (energizing or de-energizing) of downstream distribution capacitors without extra communication devices. The operation information is valuable for tackling power quality problems caused by capacitor switching and optimizing the distribution grid operation. [ABSTRACT FROM AUTHOR]

On transmission lines where switching surges are not mitigated with closing resistors and/or surge arresters, high-speed reclosing on a line with trapped charge will produce high overvoltages that have been measured above 3 p.u. Careful simulations of these switching events using available electromagnetic transient (EMT) programs consistently produce significantly higher voltages than the measurements. This indicates a phenomenon present on the line that acts to reduce the switching surge magnitudes but is not typically modeled. This paper aims to identify the required simulation practices in reproducing the field measured overvoltages in EMT simulations and investigates the sensitivity of results to modeling approaches and electrical parameters. Field measurements from a switching surge test of a 230-kV line without surge mitigation have been used for model comparisons. Variations in frequency-dependent line modeling, ground resistivity, skin effect, shunt conductance, parallel lines, and source-side detail have been tested in an unsuccessful attempt to decrease the difference between the field measurements and the higher simulation overvoltages. It is demonstrated that even though the pattern of the transient voltage waveforms can be reproduced very well using frequency-dependent line models, the magnitude of the maximum overvoltage is significantly overestimated unless the effect of corona is considered. Two types of corona models are tested, and both demonstrate that corona is the primary factor that allows the simulations to correctly reproduce high peak overvoltage measurements. [ABSTRACT FROM AUTHOR]

This paper proposes a modified bridge switch-type flux-coupling nonsuperconducting fault current limiter (BSFC-NSFCL) for suppressing the fault current and voltage sag. A flux-coupling reactor and a bidirectional bridge switch are combined to perform the functions of steady-state line current sharing and fault current suppression. The modified BSFC-NSFCL mainly utilizes the magnetic flux cancellation effect to make the limiter behave as a short circuit on the circuit during normal operation. Hence, there is almost no impact on the power system when the limiter is used. When a fault event occurs, the bridge switch turnsoffimmediately, and then, the magnetic flux cancellation effect disappears. Thus, the impedance of primary coil inserts into the circuit to restrict the fault current and voltage sag phenomena. Once the fault is removed, the bridge switch turnsonagain, and the BSFC-NSFCL recovers to the normal operation. The modified NSFCL is more cost-effective and easy to be implemented than the flux-coupling superconducting fault current limiter. Theoretical analysis for the BSFC-NSFCL has been fully developed and proven by MATLAB software. Finally, the analytical, simulated, and experimental results have been carried out to verify the feasibility and performance of the proposed BSFC-NSFCL. [ABSTRACT FROM AUTHOR]

This paper proposes a new diode-clamped multilevel inverter that can effectively balance the voltages of dc capacitors. For the proposed inverter, the inductors are inserted between the diodes and the main switches. Also, the voltage balance of the dc capacitors can be guaranteed by controlling the opening time of the corresponding main switches in particular modes. Thus, the parallel circuits on the dc side in the conventional inverters are canceled. Consequently, the proposed topology requires fewer switches, diodes, and capacitors, although it adds the compensation currents to the corresponding main switches. Both the simulation and experimental results demonstrate the suitability and applicability of the proposed topology. [ABSTRACT FROM AUTHOR]

DC winding induced voltage pulsation in the wound field synchronous machines (WFSMs) will cause dc winding current ripple, challenge the dc power supply, and deteriorate the control performance, especially at high speed. In this paper, the influence of dc winding configuration including the dc coil number and the parallel branch number on its induced voltage pulsation is investigated for WFSMs. Based on the modeling of both open-circuit and on-load dc winding induced voltages, the preferred dc winding configurations for WFSMs having various stator/rotor pole number combinations with double layer or single layer ac windings are obtained and validated by finite element (FE) analysis on four typical partitioned stator WFSMs (PS-WFSMs). A PS-WFSM prototype is built and tested to validate both analytical and FE analyses. [ABSTRACT FROM AUTHOR]

In this paper, a novel space vector modulation (SVM) strategy is proposed and designed for dual three-phase three-level motor drives based on vector space decomposition (VSD), which could be applied for high-power and high-reliability applications. The key of the proposed method is to design two decoupled groups of voltage vector candidates for synthesis on α − β subspace and x − y subspace, respectively. The two decoupled groups of voltage vectors will synthesize respective voltage references on α − β subspace and x − y subspace, while having no impact on each other. The redundant small voltage vectors and zero-sequence voltage vectors are utilized to mitigate voltage oscillation in midpoint of dc link and suppress zero-sequence current component for dual three-phase windings with a common neutral. For comparison, another VSD-SVM strategy is designed based on traditional solution, which cannot offer closed-loop control on x − y subspace. Both simulation and experiments have been given to verify that the proposed decoupled VSD-SVM can suppress harmonic components on x − y subspace besides tracking torque components on α − β subspace. Furthermore, the harmonic performance of the proposed decoupled VSD-SVM has been compared with the traditional VSD-SVM strategy and the carrier disposition based pulsewidth modulation. [ABSTRACT FROM AUTHOR]

Although high-frequency circulating current exists in parallel-operated inverters, it has not attracted as much attention as low-frequency circulating current, and thus has not been analyzed in detail previously. In this paper, a mathematical model and analysis are presented, which reveal the spectrum components and their changing trends of the circulating currents caused by carrier phase differences. The impact of carrier phase difference on high-frequency circulating current is also analyzed and verified. A closed-loop control scheme is proposed to suppress the switching frequency circulating current caused by carrier phase difference. In addition, the deadbeat and closed-loop control are combined to suppress the low- and high-frequency circulating currents simultaneously, to improve the overall performance of circulating current suppression. The effectiveness of the proposed scheme is verified by the simulation and experimental results acquired from a laboratory platform. [ABSTRACT FROM AUTHOR]

Integration of decoupling capacitors into silicon carbide (SiC) metal oxide semiconductor field effect transistor (mosfet) modules is an advanced solution to mitigate the effect of parasitic inductance induced by module assembly interconnects. In this paper, the switching transient behavior is reported for a 1.2-kV SiC mosfet module with embedded dc-link capacitors. It shows faster switching transition and less overshoot voltage compared to a module using an identical package but without capacitors. Active power cycling and passive temperature cycling are carried out for package reliability characterization and comparisons are made with commercial Si and SiC power modules. Scanning acoustic microscopy images and thermal structure functions are presented to quantify the effects of package degradation. The results demonstrate that the SiC modules with embedded capacitors have similar reliability performance to commercial modules and that the reliability is not adversely affected by the presence of the decoupling capacitors. [ABSTRACT FROM AUTHOR]

The five-level nested neutral-point-clamped (5L-NNPC) converter is one of the most promising topologies for medium-voltage (2.3–7.2 kV) high-power applications such as medium-voltage drives, wind energy conversion systems, and grid-connected systems. The 5L-NNPC requires a fewer number of switching devices, freewheeling and clamping diodes, and flying capacitors compared to the existing five-level multilevel converters. In the 5L-NNPC topology, each flying capacitor voltage is regulated at one-fourth of the dc-bus voltage to obtain the five-level operation. Due to the lack of redundant switching states, it is difficult to control the flying capacitor voltages by using the pulse-width-modulation-based classical control methods. This paper proposes a model-predictive current control (MPCC) approach to control the flying capacitor voltages along with the output currents of the 5L-NNPC converter. The discrete-time model of 5L-NNPC is developed to implement the MPCC scheme. The simulation and experimental studies are conducted to verify the dynamic and steady-state performance of 5L-NNPC with the MPCC scheme. The performance of the proposed MPCC approach is compared with the conventional space-vector-modulation-based voltage-balancing approach. Furthermore, the flying capacitor voltage control capability of MPCC is verified at different load power factors. [ABSTRACT FROM AUTHOR]

This paper presents a delta-sigma modulation control scheme for buck converters that features a reconfigurable loop filter with a scalable sampling frequency for effective switching noise reduction and high conversion efficiency. Depending on the load current, the proposed controller changes the sampling frequency along with the delta-sigma modulator (DSM) structure to transform between third- and second-order loop filters. Thus, it maintains a robust noise shaping capability and reduces the power consumption over a wide load range. The loop filters are implemented with a single op-amp resonator to reduce multiple integrators into a single element and enhance controllability of the resonance. More power-efficient operation is obtained by a switching node assisted deadtime controller (SADTC) that regulates the body-diode conduction. The proposed DSM-based buck converter was fabricated on a 180 nm CMOS. A spurious-free output spectrum with a noise floor below −81 dBm was achieved across all sampling frequencies. It operated at a wide range sampling frequencies of 3.75–15 MHz and regulated the output in the range of 1.0–2.4 V with input voltages of 2.5–5.5 V. The output voltage ripples were maintained under 19 mV. The converter showed a conversion efficiency of better than 80% over a load range of 1–1000 mA with a peak efficiency of 95.4% at 125 mA. [ABSTRACT FROM AUTHOR]

This paper proposes a control method for a five-level hybrid flying-capacitor (5L-HFC) inverter, of which structure stems from the conventional five-level active neutral-point-clamped (5L-ANPC) topology by dividing the dc-link stage into three series-connected capacitors. In this inverter, the voltage stress on the power switches connected to the dc link is reduced by a half compared with that of the 5L-ANPC topology, thus the lower number of equally voltage-rated power devices can be employed. Also, the power losses in the 5L-HFC inverter are more evenly distributed than in the 5L-ANPC. In order to balance the dc-link capacitor voltages, a third-order harmonic offset injection is applied. When a diode rectifier is used to supply the dc bus voltage, the balancing method is not effective if the modulation index is higher than 0.64. Thus, an auxiliary circuit is needed to support the balancing of the dc-link capacitor voltages. However, the unbalancing problem can be overcome in a full-range operation without the auxiliary circuit if the back-to-back configuration is utilized. Finally, simulation and experiment results have verified the performance of the 5L-HFC inverter with the proposed control method. [ABSTRACT FROM AUTHOR]

In this paper, the effects of the duty ratio variation on the class-EM power amplifier are studied and analyzed, including nonlinear gate-to-drain and drain-to-source parasitic capacitances. The duty ratio is one of the important parameters in class-EM power amplifiers, which has high effects on the switch voltage and current waveforms, output power, efficiency, power loss, and output phase shift. To achieve a better agreement between theoretical and experimental results, the nonlinear gate-to-drain and drain-to-source parasitic capacitances are included in theoretical analysis. To demonstrate the validity of the presented analysis, five class-EM power amplifiers are designed, simulated, fabricated, and tested using IRF510 mosfet with the duty ratio equal to 0.5, 0.6, and 0.7 and IRFZ24N mosfet with the duty ratio equal to 0.5 with and without considering mosfet nonlinear capacitances. It is shown that the amplifier with IRFZ24N mosfet has higher efficiency than that with IRF510 mosfet. This is because of the lower drain-to-source on-state resistance of the IRFZ24N mosfet. The obtained efficiency with IRFZ24N mosfet considering nonlinear capacitances at the operating frequency of 3.5 MHz was 95.7%. The obtained output power for IRF510 and IRFZ24N mosfets at the duty ratio equal to 0.5 was 14.41 and 17.82 W, respectively. Simulation and theoretical results are performed using PSpice and MATLAB, respectively. The theoretical results and PSpice simulations agreed with experimental results. [ABSTRACT FROM AUTHOR]

This paper proposes the new clamping angle control (CAC) pulse width modulation (PWM) method to restore its maximum linear modulation range of voltage source inverters (VSIs) reduced by the duty ratio limitation in hardware implementation, which makes the VSIs to operate nonlinearly in the high modulation range. The deadtime and the bootstrap gate driver circuit mainly cause this duty ratio limitation in practice. In particular, the bootstrap gate driver circuit is used in many industrial applications by avoiding the additional power supply to apply the gate-source voltage of power switches, and therefore making the VSIs to be small size with the low cost. First, the proposed CACPWM method is theoretically analyzed. Then, it is applied in the high modulation range to overcome the limitation of the duty ratio due to the use of the bootstrap gate driver circuit. Thereafter, its practical effectiveness is verified by both simulation and experimental tests. Also, the resulting harmonic distortions are compared with those by the conventional PWM methods. [ABSTRACT FROM AUTHOR]

This paper presents an overview of resonant and hybrid switched-capacitor converters with a particular focus on multimode operation. The multimode approach is discussed as a tool to affect high efficiency and power density across a wide load range, provide variable regulation, and, as a general framework, to conceptualize the advantages and opportunities of the approach compared to more traditional dc–dc converters. A general analysis is provided to quantify the advantage of hybrid and resonant converters that factors in the tradeoffs between size and loss in the magnetic component and voltage stress on the active devices. A broader set of operating modes is presented that spans continuous and discontinuous conduction and includes resonant, quasi-resonant, and more traditional buck- or boost-like operation. A prototype flying-capacitor multilevel converter is presented to demonstrate the variety of operating modes and motivate important considerations such as voltage balance on the flying capacitors. [ABSTRACT FROM AUTHOR]

The trend toward higher switching frequencies and higher power densities in dc–dc conversion led the designers to rediscover resonant topologies. However, the analysis of these converters is often limited to a particular operating mode and/or topology. This paper wants to fill the gap by presenting a state-space-based analysis for a broad class of series-resonant converters including voltage-fed as well as current-fed topologies, either unidirectional or bidirectional. The proposed solution consists of a mathematical framework that solves the trajectory of state variables in the resonant tank, as well as the main characteristic functions such as voltage conversion ratio and transferred power. The matrix approach permits a flexible and compact formulation and easy implementation in computational tools such as MATLAB. The theoretical framework is applied to both voltage-fed and current-fed resonant topologies: the first is used to show the advantages of the proposed model respect to the first harmonic approximation, while a detailed analysis in terms of operating mode boundaries, delivered power, and voltage gain is provided for the second. Simulations and measurements on a 300-W prototype of the current-fed topology are used to validate the correctness of the proposed solution. [ABSTRACT FROM AUTHOR]

The output voltage of matrix converter (MC) is related to the frequency of input, output, and carrier signals, and these three frequencies are independent of each other. This makes it difficult to give a precise description of the harmonic spectrum with the commonly used methods such as fast Fourier transform (FFT) and the double Fourier analysis. Based on triple Fourier series, this paper proposes an analytical method to determine harmonic components of MC under space vector modulation (SVM). First, combined with the SVM strategy of MC, the expressions of output voltage harmonics are derived. Then the analytical solutions are obtained on the basis of the calculated expressions. From the analytical solutions, the harmonic amplitudes can be determined precisely, and the values of index variables k , p, and q of harmonic frequency ${kf}_{\rm c} \;\pm\; pf_{{\rm{out}}}\pm qf_{{\rm{in}}}$ are confirmed. According to the results, the harmonic distribution characteristics as well as main harmonic components are analyzed. Finally, the feasibility and accuracy of the proposed analysis method is verified by comparative analysis against the FFT results of measured output voltage waveform. [ABSTRACT FROM AUTHOR]

This paper presents a dynamic power flow management system for a solar photovoltaic (PV) system employing a single-stage single-inductor-based dual-input/output dc–dc converter feeding standalone dc loads backed up by a rechargeable battery. A time-sharing voltage-mode control scheme has been proposed for power flow management between solar PV, a battery, and a standalone dc load, and it also maintains a constant dc load voltage and performs maximum power point tracking operation of solar PV. The implementation of the control scheme has been described in detail. The steady-state performance of the single-stage converter has been explained with the relevant analytical expressions derived along with the characteristics. A state-space average model was developed for simulating the transient behavior and validating the working of the system for step changes in the input solar PV power and the dc loads. A hardware prototype of the proposed system has been fabricated, and the proposed controller has been implemented using the dSPACE DS1103 real-time interface board. The working of the proposed scheme for different levels of input solar insolation and dc load power demand has been satisfactorily demonstrated, and the corresponding results are also provided. [ABSTRACT FROM AUTHOR]

Parallel inverters are commonly adopted in high-power applications, for instance wind energy systems, smart transformers, and power conditioners. Meanwhile, interleaved pulse width modulation is usually considered as an optimal approach to reduce the current ripple and harmonics of the parallel inverters. However, in the case of a common dc link, the problem of circulating current emerges and leads to performance degradation. This paper aims at investigating the influence of different modulation techniques on the circulating current of two neutral-point-clamped (NPC) inverters under interleaved operation. Two modulation techniques, phase disposition (PD) and alternative phase opposite disposition (APOD), have been studied and compared in terms of current ripple, spectrum quality, and circulating current. Though the PD modulation was regarded as the optimum solution in most of the single-NPC cases, it offers worse performance in the two parallel NPC applications due to higher circulating current. Simulation and experimental validations are provided and show that the APOD leads to much lower circulating current and similar current ripple as well as spectrum quality compared to the PD. [ABSTRACT FROM AUTHOR]

With the development of silicon carbide (SiC) power devices, the circuit structure of power converter for high-voltage applications would be simpler and more compact because the two-level-based topologies become applicable. This paper proposes a full-bridge (FB) T-type isolated dc/dc converter for the applications with high input voltage and wide input voltage range. The proposed converter is composed of four main power switches with high voltage stress (SiC mosfet) and four auxiliary power switches with low voltage stress (Si mosfet). Comparing with the conventional diode clamped FB three-level isolated dc/dc converters, the proposed FB T-type converter has simpler circuit structure and higher efficiency. A corresponding control strategy including two working patterns is proposed, which can not only realize the zero-voltage switching for the main and auxiliary power switches but also satisfy the wide input voltage range. More importantly, the proposed corresponding control strategy has the ability of balancing the currents among the power switches, which would balance the power losses, thermal stresses among the power switches, and thus improve the reliability of the converter. The characteristics and performances of the proposed converter with the corresponding control strategy are analyzed in detail and verified by the simulation and experimental results. [ABSTRACT FROM AUTHOR]

In this paper, a novel buck–boost dc–dc converter with continuous input current is proposed. The voltage gain of the presented converter is higher than conventional converters, such as buck–boost, single-ended primary-inductance converter, Cuk, and Zeta converters. This converter works only by one switch and voltage stress across the switch is low. Input current of the proposed converter is continuous so a large filter at the input is not needed. Furthermore, continuous input current has made this converter suitable for renewable energy and fuel cell applications. In this converter, noninverting output voltage is obtained and high gain of voltage is achieved as well. So it can operate at wide output voltage range only by changing the duty cycle of the power switch pulse. The presented converter can easily controlled in continuous conduction mode operation, because of using only one power switch. In the following, the principle of operation and the mathematical analyses of the proposed converter are explained, finally, validity of the proposed dc–dc converter is verified by the experimental results. [ABSTRACT FROM AUTHOR]

In this paper, a half-bridge (HB) converter, additionally employing a diode compared with the conventional modified duty-cycle-shifted (MDCS) HB converter, is proposed to achieve a high efficiency in wide-input-voltage and low-output-current applications. Since the proposed converter has symmetrical operation, it maintains the advantages such as no transformer dc-offset current, and identical and low-voltage stresses on the secondary diodes. Moreover, due to one additional switch connected in series, the zero-voltage-switching capability of the upper switch is improved. As a result, small resonant inductances are required, which reduces the duty cycle loss, thus the primary conduction losses decrease. In addition, since additional clamping diodes separate external resonant inductor from the resonance path, additional voltage stresses on the secondary diodes can be decreased. Therefore, its snubber loss can be reduced, and it can achieve higher efficiency than that of the MDCS HB converter. To confirm the operation, features, and validity of the proposed converter, a 310–400 V input and 50-V/250-W output laboratory prototype is built and tested. [ABSTRACT FROM AUTHOR]

This paper deals with a novel reduced sensor strategy, for two-stage single-phase grid connected solar photovoltaic system with a battery, where the dc-link voltage sensor is not required. Moreover, for maximum power point tracking (MPPT), a new “normal harmonic search” (NHS) algorithm is used, and for voltage source converter (VSC) control, a novel “power normalized kernel least mean square” (PNKLMS) algorithm is proposed. The PNKLMS algorithm is used for active load component extraction from the load current, even when the load current is characterized by linear or nonlinear behavior. Moreover, PNKLMS algorithm is used for reference grid current generation. The NHS algorithm is an improved version of the harmony search, which is inspired to the music composition technique and its searching ability is improved by using the normal probability distribution factor. Therefore, NHS reaches the global maximum power point very quickly and is suitable for online searching on hardware. Moreover, the extracted power is fed into the grid. For control of VSC, the proposed PNKLMS control technique is used, which maintains the power quality. The performances of NHS-based MPPT and PNKLMS-based control technique with reduced sensor approach are tested on a developed prototype. The satisfactory steady-state and dynamic performances of the NHS algorithm are demonstrated under variable irradiance and temperature during partial shaded conditions. Moreover, the performances of the PNKLMS algorithm, without using dc-link voltage sensor are demonstrated during overvoltage, undervoltage, harmonics distortion, and load nonlinearity condition, results of which have satisfied the objective of the proposed system and the IEEE-519 standard. [ABSTRACT FROM AUTHOR]

This paper presents a new least-mean-square (LMS) algorithm based deadtime compensation method to suppress the current distortion in permanent-magnet synchronous motor (PMSM) field-oriented control (FOC) drives. Compared to conventional average value compensations, the proposed method is robust to switching device parameter variations thanks to the online adaptation capability of the LMS algorithm. Similarly, the disturbance observer compensators are also immune to switching device parameter variations; however, varying motor parameters degrade their compensation performance. Without prior knowledge of switching device or motor parameters, the proposed method can directly reduce the deadtime current harmonics by generating compensation voltage references. In addition, the proposed method is easy to implement since it does not require voltage errors estimation or current harmonics extraction, which are necessary for disturbance observer and adaptive filter based methods. The proposed method is tested on a 2.5-kW voltage-source inverter PMSM drive controlled by an FOC algorithm. Its effectiveness is validated by both experimental results and spectrum analysis. [ABSTRACT FROM AUTHOR]