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In recent years, a number of bidirectional inductive power transfer systems (BD-IPT) suitable for wireless grid integration of electric vehicles have been developed. These developments have been fueled by the enhanced efficiency and spatial tolerance offered by BD-IPT systems. A typical BD-IPT system utilizes two synchronized full-bridge converters operating at fixed duty cycles to drive the primary and secondary magnetic couplers. However, in order to cater for a wide range of loading conditions, additional circuitry is employed at the expense of cost and power density. As an alternative solution, this paper proposes a novel power converter, named a boost active bridge (BAB), to replace the full-bridge converters. The BAB topology caters to a wide range of loading conditions without the need for any extra switching devices. A comprehensive mathematical model that predicts steady-state currents, voltages, and power transfer is presented to highlight the operating principles of the BAB technology. Experimental results obtained from a 3.5-kW prototype show a nearly constant efficiency under all loading conditions, validating the viability of the proposed BAB topology. [ABSTRACT FROM AUTHOR]

This paper proposes a model predictive flux control (MPFC) strategy with cost function-based field weakening (FW) strategy for permanent magnet synchronous motor (PMSM). The stator flux vector is used as the control variable and the cost function of the proposed MPFC is configured in the form of flux increment, which can reflect the saturation degree of the inverter output. A novel space flux vector plane is introduced to explain the principle of optimal switching state selection in the proposed MPFC. The voltage and current limitations of the inverter in the high-speed region are analyzed in the flux plane to reveal the objective of FW compensation. The value of the cost function is controlled with a proportional integral controller in the proposed cost function-based FW strategy. Moreover, the reference flux vector is compensated with the output of the FW controller to enlarge the operation region of the stator flux vector. With the proposed FW strategy, the operation range of the PMSM is extended and the torque output in high-speed range is increased. Experimental studies are carried out to verify the validity and effectiveness of the proposed strategy. [ABSTRACT FROM AUTHOR]

A novel nine-level inverter topology for low-voltage applications is proposed in this paper. Each phase of the inverter is composed of a T-type three‐level cell and an active neutral point clamp three‐level cell. The operation principles and current conduction paths are analyzed in detail and phase-disposition sinusoidal pulsewidth modulation is used to balance voltages of flying capacitors and neutral point. The mathematical relationship between the capacitance and the desired ripple in the inverter output is established to select the intermediate capacitance value. Compared with other nine-level inverters suitable for low-voltage applications, the proposed inverter has advantages in a number of gate drivers, a number of dc sources, and efficiency. Simulation and experimental results under different settings of modulation index, power factor, output frequency, and load are presented to verify the effectiveness and performances of the proposed inverter. [ABSTRACT FROM AUTHOR]

A multilevel dodecagonal voltage space vector generation scheme for variable-speed drive applications with single-dc-link operation requires a large value of capacitance for cascaded H-bridge (CHB) filters, when operated at lower speeds. In existing schemes, the multilevel dodecagonal structure is obtained by cascading a flying capacitor inverter with a CHB. In this paper, a new scheme has been proposed to minimize the capacitance requirement for full speed operation by creating vector redundancies using modular and equal voltage CHBs. Also, an algorithm has been developed to optimize the selection of vector redundancies among the CHBs in order to minimize the voltage ripple of the floating capacitors. The proposed algorithm considers instantaneous capacitor voltages and phase currents for optimal selection of vector redundancies. A mathematical model for capacitor voltage deviation is presented, and the effectiveness of the proposed algorithm is verified in both the simulation and the experiment. [ABSTRACT FROM AUTHOR]

This paper presents the current control design procedure of a single-phase grid-tied five-level packed U-cell inverter (PUC5) with an LCL output filter. The PUC5 inverter is used as an interface of renewable energy sources, such as solar applications. The LCL filter is calculated according to the grid-tied operation and converter ratings. An optimal controller, based on a linear quadratic regulator with integral action, is designed to inject a sinusoidal current with low harmonic distortion at unity power factor. For that design, the PUC5 inverter is modelled in the D–Q frame. The sensorless voltage control is incorporated into the switching technique to balance the PUC5 capacitor voltage and generate a five-level waveform at the output. Experimental tests are performed on a laboratory benchmark to confirm the theoretical design. The results prove the efficiency and accuracy of the adopted control strategy in a steady state and under transients of grid current, grid inductance, ac and dc voltage amplitudes. [ABSTRACT FROM AUTHOR]

This paper presents an investigation on finite control set model predictive current control, validated experimentally with a rear axle electrical drive unit used in automotive applications. An improved problem formulation is suggested which lowers the computational turnaround time of the solver with approximately $\text{40}\%$ for an horizon length of $N=4$. Apart from the computational requirement aspects, the assessment focuses on inverter efficiency, phase current total demand distortion, and acoustic performance. The proposed solution is evaluated against a standard double proportional and integrator (PI) field-oriented current controller with pulsewidth modulation. It is shown that the proposed solution is feasible, the associated optimization problem at hand can be solved in real time, while exploiting the attractiveness of the proposed improvements. In summary, it is concluded that the inverter efficiency can be improved without deteriorating neither the phase current harmonics nor the acoustic performance. [ABSTRACT FROM AUTHOR]

This paper presents the circuit design and magnetic integration of push–pull class-E inverters for wireless power transfer (WPT) up to megahertz. The design criterion for achieving zero-voltage switching (ZVS) of a class-E inverter with coupled windings is derived mathematically. The approaches of magnetic integration for push–pull class-E inverters are analyzed and compared. Then, a new magnetic structure with hybrid magnetic materials is proposed to build the integrated inductors with either coupled windings or uncoupled windings. A 3-MHz WPT system is built to verify the analysis. The detailed comparison of the class-E inverters with magnetic integration is presented in terms of switch voltage, efficiency, harmonic currents, and thermal distribution. In the optimized design example, the switches keep ZVS over the entire load range without using any closed-loop control. The system efficiency reaches 87.1% at 350-W output power. [ABSTRACT FROM AUTHOR]

In this paper, two single-phase single-stage split-inductor buck–boost inverters are proposed: type-I and II. The proposed type-I is unity power factor inverter, while the proposed type-II inverter is suitable for any power factor. Both topologies remove the shoot-through problem. Furthermore, the reverse recovery issues for all switches are eliminated; therefore, mosfets are used to obtain higher efficiencies. The proposed inverters operated at higher switching frequencies confer the additional benefit of smaller passive components. The current stresses of the two switches in the proposed type-I and II inverters are lower of the conventional boost inverter. The dead time can be eliminated at both the high and line switching frequencies. In addition, the inductor conduction loss is minimized to improve efficiency. Moreover, the voltage stresses of the two switches in the type-I inverter can be much lower of its counterpart boost inverter. Most importantly, unlike the conventional high-reliability inverters, the magnetic volume of the proposed high-reliability type-I and II inverters is same of its counterpart boost inverter. The experimental results obtained for 500 W, 110 Vrms, 60 Hz hardware prototypes verify the analysis. [ABSTRACT FROM AUTHOR]

This paper presents a reduced component count five-level inverter topology based on the stacked cell approach to multilevel inverters. The proposed topology utilizes the fundamental properties of three-phase voltages to reduce the number of switches and flying capacitors to cut size, weight and costs while facilitating higher reliability, simpler wiring and lesser electromagnetic interference. The operational aspects of the topology such as circuit structure, modulation and capacitor balancing are explained, followed by an account of device stresses and reliability. A discussion of certain additional features such as fault tolerant operation, loss steering and common-mode elimination addresses the usefulness of the topology in practical situations. A comparison of the proposed topology with existing methods in terms of several parameters is then used to highlight its merits and features. Finally, experimental results obtained using an induction motor drive incorporating the topology are given, so as to validate the feasibility of the proposed approach. [ABSTRACT FROM AUTHOR]

T-type multilevel (T2ML) inverters feature low total harmonic distortion and high efficiency. Reliability improvement is particularly important for T2ML inverters because they have high power device count. Methods that provide T2ML inverters with the ability to tolerate simultaneous failures of multiple switches in several legs have not been addressed in the existing literature. This paper proposes a redundant unit that can be shared across phases in a T-type three-level inverter topology to manage open-circuit faults in multiple legs. The redundant unit includes two switches and six diodes, with the extra active switches connected by diodes to each middle switch of the base inverter. Under fault conditions, a standby parallel leg consisting of middle switches and the added redundant devices can be formed in each phase of the inverter to provide an extra current path connecting the dc bus and loads. The middle switches can share the redundant unit simultaneously to replace faulted half-bridge switches. By these means, open-circuit faults in multiple legs can be tolerated simultaneously and the rated output capacity can be maintained during faulted operation. Experimental tests are given to verify the effectiveness and feasibility of this proposed fault-tolerant method. [ABSTRACT FROM AUTHOR]

The time delay caused by the digital computation and the update of the duty cycle tend to worsen the dynamic performance of digitally controlled power converters. This paper proposes a real-time calculation method for single-phase cascaded H-bridge (CHB) inverters with the phase-shifted carrier pulsewidth modulation (PSC-PWM) to eliminate the time delay caused by the digital computation in the control loop without the loss of duty cycle. In the approach, a sampling method for the PSC-PWM applied in a single-phase CHB inverter is introduced, which samples the current and voltage at points of the intersection for triangular carriers of legs in all adjacent H-bridge cells. The sampling method is used alternately with the conventional regular sampling method by following a selection rule in order to avoid the loss of duty cycle. Experimental results verify that the proposed method effectively improves the transient performance of the current control loop and suppresses the effect of the distortion of the grid voltage on the line current. [ABSTRACT FROM AUTHOR]

A multilevel drive can be realized by using an open-ended machine, fed from dual two-level inverters. The topology supplied from isolated dc sources is suitable for transportation electrification. In vehicular systems, it is essential that the isolated dc sources, comprising of battery packs, should discharge uniformly and maintain balanced dc voltage at the dc-link terminal. A simple carrier-based pulsewidth modulation (PWM) technique is presented in this paper, which can effectively regulate the power drawn between the two two-level inverters while maintaining the multilevel operation of the drive. The modulation technique can balance the instantaneous state of charge of independent battery packs and dynamically equalize the power flow from the two inverters, based on drive requirement. This will enhance the reliability of the propulsion system in electric vehicles. The operation of the proposed PWM technique has been validated through detailed simulation and experimental tests. [ABSTRACT FROM AUTHOR]

Reliability of power systems can be improved by the use of voltage source inverters (VSIs) with fast dynamic control, which can handle uncertainties induced by renewable energy resources and nonlinear loads. To ensure fast-dynamic response and simplified controller design, various model predictive control (MPC) methods are investigated in this paper. In the conventional MPC design for three-level VSIs, the cost function requires an additional term to ensure the balance of the neutral-point voltage (NP-V), which however can considerably impact the main goal of the MPC. To address this issue, an enhanced MPC using virtual space vectors is proposed, which allows the use of a significantly reduced weighting factor for the term in the cost function for NP-V balancing, while retaining fast-dynamic response. Additionally, the proposed MPC leads to reduced harmonic distortion in the VSI output voltage and current. Both simulation and controller hardware-in-the-loop studies are performed to demonstrate the effectiveness of the proposed enhanced MPC in an operating microgrid under both steady-state and fast-transient conditions. [ABSTRACT FROM AUTHOR]

Conventional microinverter or module-integrated converter (MIC)-based photovoltaic (PV) systems are prone to be complex and costly because each MIC requires not only a boost converter to bridge a huge voltage gap between a PV panel and grid but also desirably a differential power processing (DPP) converter to preclude partial shading issues. This paper proposes a novel MIC based on cascaded quasi-Z-source inverters (qZSIs) with DPP capability. A traditional qZSI and voltage multiplier (VM)-based DPP converter are integrated into a single unit with sharing active switches and magnetic components, achieving system- and circuit-level simplifications. In addition, a novel control strategy utilizing two control freedoms of shoot-through duty cycle $d_{st}$ and modulation index M to simultaneously perform maximum power point tracking (MPPT) and DPP function, respectively, is also presented. A 150 W prototype for a standard PV panel consisting of three substrings is built, and experimental tests are performed emulating partial shading conditions. The results demonstrate that the proposed integrated qZSI could perform MPPT with satisfactory preventing partial shading issues while generating ac voltage at the inverter output. [ABSTRACT FROM AUTHOR]

The inductance is an important parameter impacting current ripple calculation, usually with the assumption that the designed inductance performs ideally in most of voltage source inverters (VSIs) applications. However, the initial permeability of magnetic material usually descends when the winding current reaches or goes beyond the saturation limit. In such region of saturation, the implemented inductor does not perform as expected in design stages and its value varies with the bias current. In this paper, analysis and calculation of the current ripple are presented for a three-phase VSI with powder cores-based inductors, which reveals the calculation error of current ripple caused by the soft saturation nature of powder cores. Based on the equivalent single-phase model, the influence of inductance saturation on current ripple can be quantitatively evaluated. Then, a comparison of the current ripple calculation between considering and ignoring inductance saturation of implemented inductors is drawn in detail. Furthermore, under the condition of inductance saturation, the output current ripple peak-to-peak value of three phases is used as the constraint for variable switching frequency pulsewidth modulation (VSFPWM) design. A comprehensive method is developed to compensate the effect of inductance saturation in VSFPWM. At last, the effectiveness of the proposed strategy is verified by the detailed simulation and experiment. [ABSTRACT FROM AUTHOR]

This paper proposes a new inverter topology based on the active neutral-point-clamped (ANPC) converter with capability to integrate one energy storage system (ESS) per inverter leg with an independent state of charge control, so that each inverter leg has two dc ports and one ac port. The primary dc port is common to all inverter legs and it is connected to the main power source. The secondary dc port is suitable for ESS connection because of its two-quadrant operation, with bidirectional current capability, so that the ESS can be charged and discharged with regulated current. Integration of a secondary dc port with independent control also allows the use of different ESS technologies for each inverter leg to compose a hybrid ESS. Redundant switching states of the proposed structure are used to balance the energy exchanged between the secondary dc port and the dc bus capacitors. Theoretical propositions were experimentally validated through a 1-kW single-phase inverter with a secondary dc port connected to a 230-V ESS and ac port connected to an LC filter feeding a linear load. Low total harmonic distortion (THD) sinusoidal current is generated at the ac port while charging or discharging the ESS with a constant current. [ABSTRACT FROM AUTHOR]

Transformerless inverters are getting popular in distributed photovoltaic power generation (PVPG) system due to its light weight, low cost, and higher efficiency in power conversion. However, the production of leakage current leads to severe electromagnetic interference and operational insecurity, which declines the reliability and efficiency of the overall system. Besides that many of the topologies have been addressed with real power injection capabilities in the literature. Therefore, in this paper, an improved hybrid-bridge (IH-B) inverter for transformerless PVPG system is proposed with 1) reduced leakage current by abolishing the fluctuations in common-mode voltage (CMV) due to switch junction capacitances and 2) reactive power capability with a modified sinusoidal pulsewidth modulation technique. This topology is constructed with the combination of bidirectional clamping branch and hybrid-bridge (H-B) inverter topology to maintain CMV at half of the dc-link voltage and ensure better quality of output waveforms at different power factors of the grid. Further, MATLAB simulation results of the IH-B and H-B topologies are presented and compared to prove the potential benefits of the proposed topology. Finally, a 500W prototype model is built and tested to validate the effectiveness of the IH-B topology in reduction of leakage current and reactive power capability. [ABSTRACT FROM AUTHOR]

Unipolar-pulsewidth modulation (UP-PWM) inverter takes advantages of high power efficiency and small output chokes which is widely used in the industry. However, UP-PWM inverters cannot be used in parallel operation due to a current unbalance problem. This paper studies the current unbalance problem of paralleled UP-PWM inverters with common dc bus and ac bus. First, the problem of unbalanced inductor current is defined and analyzed. Second, a technique to eliminate unbalanced currents is proposed. The proposed current balancing technique only requires one more current sensor in an inverter module rather than changing converter topology or modulation method, which makes it possible to apply UP-PWM inverters in parallel-operation while keeping the advantages of unipolar switching. The proposed current balancing method is verified by both simulation and hardware experiment. Experimental verification is performed on two 1 kW, 400 V input, and 120 V/60 Hz output prototypes, which shows a good agreement to the analytical study. [ABSTRACT FROM AUTHOR]

The integration of switched-capacitor techniques into multilevel inverters (MLIs) with a dc source string contributes to the boosting of voltage gain, renders it particularly attractive in reducing the number of input dc sources in the series string. However, the recent two-stage MLI topologies suffer from high voltage stress across the backend H-bridge. Addressing this concern, an improved topology, namely the one-switched-capacitor integrated MLI (1SCI-MLI) is proposed in this paper. An extended topology of 1SC-MLI is also established by appropriate incorporation of another switched-capacitor circuit. The two proposed topologies are endowed with voltage boosting capability. They also feature low switch count and low number of dc sources. More importantly, they resolve the high voltage stress problem in the existing counterparts. Their corresponding operational analysis and comparisons with recent MLI topologies are discussed. Simulation and experimental results from a laboratory prototype are presented to validate the effectiveness of the proposed topologies. [ABSTRACT FROM AUTHOR]

This paper deals with the analysis of the input dc-link voltage ripple in multilevel inverter based on H-bridge and level doubling network (LDN). The LDN is basically a half-bridge fed by a floating capacitor, with voltage self-balancing capability, recalling the concept of a flying capacitor configuration. The amplitude of the LDN voltage ripple is analytically determined considering both the low-order and the switching harmonic components. In particular, peak-to-peak distributions of voltage ripples over the fundamental period are analytically determined, making possible the design of dc-link capacitor relying only on the dc-voltage ripple requirements. The case study makes reference to negligible switching ripple in the output current. It well represents either grid connection or passive load having almost sinusoidal currents. Numerical simulations carried out by MATLAB/Simulink and a complete set of experimental verifications are given to confirm the theoretical developments. [ABSTRACT FROM AUTHOR]

In this paper, a novel structure of switched capacitor converter (SCC) is proposed. First, the basic unit of the proposed SCC is presented. After that, a generalized structure of the proposed SCC is discussed. The presented SCC uses one dc source, several switches, diodes, and capacitors to produce multistep dc boosted output voltage. The capacitors in the SCC can be charged in trinary asymmetrical pattern. A detailed comparative study between the proposed and other recently developed SCC structures is presented. It is shown that the proposed SCC can produce an output voltage level with lower total standing voltage and lower maximum switch stress voltage as compared to most of the suggested SCC structures. Further, a switched capacitor multilevel inverter (SCMLI) based on cross-switched multilevel inverter has been developed and analyzed for symmetric and asymmetric dc source configurations. For fair comparison with the existing SCMLI structures, the overall cost of the structures is compared based on a cost function (CF). The proposed SCMLI provides lower cost function/output voltage level (CF/NL) in comparison with most of the other SCMLI structures for both symmetric and asymmetric dc source configurations. Extensive experimental studies validate the operation and performance of the proposed SCMLI structure. [ABSTRACT FROM AUTHOR]

This paper presents the topology and modulation technique of a three-phase three-level modified Z-source neutral-point-clamped (MZS-NPC) inverter, which combines a modified Z-source impedance network and a three-phase three-level NPC inverter. The boost factor of the proposed MZS-NPC inverter is twice as high as the three existing representative topologies combing an impedance network with a three-level NPC inverter. A modulation scheme for the proposed topology, based on a maximum boost control method, is designed to achieve the maximum voltage gain with simple implementation and to balance the dc-link neutral-point voltage. A closed-loop control of the ac load voltage in the fuel-cell or photovoltaic applications based on the proposed inverter is realized, in order to supply a desired voltage to the critical load in islanding mode of a microgrid. The boosting ability and operation validity of the proposed topology and modulation technique are demonstrated with simulation and experimental results. [ABSTRACT FROM AUTHOR]

A pulsewidth-modulation bidirectional ac–dc converter (i.e., active rectifier) with dc-fault-blocking and self-pre-charge capabilities is proposed in this paper for low voltage dc (LVdc) applications. The proposed converter, which is named as “H5 + converter,” consists of an H4 bridge, a bidirectional switch, and a transient-voltage-surge (TVS) diode. The bidirectional switch and the TVS diode enable the dc fault blocking and dc bus self-pre-charge, while preserving the low common-mode voltage noise and low leakage current of the converter. Additionally, the proposed H5+ converter has advanced features under a dc-side short-circuit fault, such as fault diagnosis and fault recovery. Operation principles of the proposed converter are presented and analyzed. A down-scaled prototype is built. Experiment results are shown and analyzed, including steady-state waveforms, common-mode performance, start-up dynamics, as well as dc fault blocking, fault diagnosis, and fault recovery. Moreover, the proposed converter is compared with other two dc-fault-blocking converters for LVdc applications, in terms of converter capabilities, required devices, and power switch losses. [ABSTRACT FROM AUTHOR]

This paper proposes a new family of multilevel inverter topology that is able to generate seven voltage levels by utilizing one or two floating capacitors and 10 power switches. This novel boost switched-capacitor seven-level inverter possesses voltage boosting capability with an achievable maximum voltage level 1.5 times the input direct current (dc) voltage. The generation of higher output voltage does not incur high-voltage stress on any power switch in this topology, as the peak inverse voltages of all power switches do not exceed the input source voltage. In addition, capacitor voltage balancing is not essential since the floating capacitors are effectively balanced during the charging and discharging processes. Furthermore, the proposed topology eliminates the need for multiple isolated dc sources, and a single dc source is sufficient in both its single-phase and three-phase topologies. The operating principle and steady-state analysis of the proposed topology are elaborated. Experimental results from a single-phase prototype are then presented to verify the validity of the proposed topology. [ABSTRACT FROM AUTHOR]

Commutation failure is one of the most frequent failures in line-commutated converter based high-voltage direct-current (LCC-HVdc) systems which may lead to the outage of HVdc links, and thus affect the performance of the power system. Most commutation failures are caused by voltage reduction due to ac system faults. In this paper, a commutation failure prevention module (CFPM) is developed, which inserts the optimal value of resistance proportional to the reduced extinction angle in series with the fault current path using a simple switching method. When a fault occurs at the inverter ac side, a self turn-off switch starts switching with a pre-specified frequency and controlled modulation index, which limits the fault current to the desired value and inhibits commutation failure. The salient feature of the proposed CFPM is that it is fully controllable. In addition, despite the available controller modification methods which are not effective for low-impedance faults, the proposed CFPM can prevent commutation failure regardless of the fault severity. The practical performance and feasibility of the developed CFPM is validated through laboratory testing, using the real-time Opal-RT hardware prototyping platform. The experimental results demonstrate that the proposed strategy can effectively eliminate the commutation failure or repetitive commutation failures under different fault types. [ABSTRACT FROM AUTHOR]

In this paper, an integrated step-up inverter without transformer is investigated for photovoltaic (PV) power generation. The proposed topology can be derived by combining a traditional boost converter with a single-phase full bridge dc–ac converter. The main features of the integrated inverter are: First, the leakage current caused by the solar cell array-to-ground parasitic capacitance can be theoretically reduced to zero due to the characteristics of the converter configuration, which can improve the efficiency and the reliability of the PV generation system; second, the output ac voltage of the proposed inverter can be higher than the input dc voltage, which is capable of connecting low voltage PV panels to the grid; third, only five active switches are used in the presented inverter, and those switching devices can be synchronously driven by various sinusoidal pulsewidth modulation methods based on the carrier; therefore, the proposed inverter is compact and with curtailed cost. The working principle and analysis of the proposed integrated inverter are elaborated. Finally, simulation and experimental results are obtained in a lab prototype, which agree well with the theoretical analysis. [ABSTRACT FROM AUTHOR]

In order to provide high and extendable power levels for inductive power transfer (IPT) system, a parallel multi-inverter system based on modular inverter is presented. Various power requirements can be implemented by an adjustment of the number of paralleled inverters, which provides a high modularity. A master−slave scheme is employed for the switching-driver signals of parallel inverters, where one acts as a leader while others act as followers. Despite the master−slave scheme, the proposed circuit topology has natural robustness because of the equality in terms of the hardware configuration of each modular inverter. For proper parameters, the output phase (current lagging corresponding voltage) of an inverter is lower than the average of output phase of all inverters, when its output voltage lags behind others, and vice versa. Based on this approach, PI controllers are designed to implement phase synchronization for output voltages of all inverters. An IPT prototype supplied by the proposed parallel multi-inverter with three inverters was designed, built, and tested. Experiments show that the proposed parallel multi-inverter system has not only good circulating current suppression capacity but also excellent performance of phase synchronization. The maximum dc−dc efficiency was 94% at a 35.1 kW receiving power. This paper is accompanied by a Matlab/Simulink file demonstrating phase synchronization control. [ABSTRACT FROM AUTHOR]

In this paper, a robust adaptive sliding-mode observer (SMO) is designed based on the surface permanent-magnet synchronous machine (SPMSM) model in rotor reference frame ($\gamma \delta $ -axis), and an online inverter nonlinearity identification and compensation method is proposed. In order to reduce the chattering of the SMO, an adaptive law is presented to help estimate the back electromotive forces of an SPMSM; thus, smaller gains can be set for switching functions of the SMO. The small-signal model of the proposed sensorless scheme is derived for analyzing the steady-state and dynamic behavior of the sensorless scheme. Voltage distortion, caused by nonlinear characteristics of switching devices, not only causes (6k ± 1)th harmonics in phase currents but also leads to a rotor position estimation error. The equivalent amplitude of the voltage distortion can be identified based on the derived small-signal model of the proposed sensorless scheme. To improve the accuracy of the estimated voltage distortion, a recursive restricted total least squares is applied to obtain the estimated amplitude of the voltage distortion. Experimental results validate the proposed sensorless control scheme and its effectiveness. [ABSTRACT FROM AUTHOR]

This paper proposes a new 7-level inverter topology for induction motor drives. It is a hybrid topology formed by cascading a 5-level active neutral-point-clamped inverter with a 3-level T-type converter. It is obtained using low-voltage semiconductor devices with voltage blocking capability of Vdc/3 and Vdc/6. The topology uses three floating capacitors per phase, which are balanced within a pulsewidth modulation (PWM) switching duration using switching-state redundancies for each pole-voltage level. Topology forms two stacks at the front-end, which requires individual symmetrical dc source. The analysis of switching loss and conduction loss is performed and compared with some of the existing 7-level multi-level inverters reported in various literatures to show the advantages of the proposed topology. Furthermore, the single dc source operation with two stacked capacitors and closed-loop control of neutral-point voltage using symmetrical six-phase induction motor is proposed. The voltage-control algorithms for floating capacitors and dc-link stacked capacitors are proposed, which are independent of load power factor and modulation index. Open-loop V/f and closed-loop rotor field oriented control are performed, and various results at steady and transient states are presented to validate the aforementioned claims. [ABSTRACT FROM AUTHOR]

This paper proposes a new grid current controller for a photovoltaic (PV) module integrated buck inverter using a single pulsewidth modulation switch and an unfolding H-bridge, which significantly reduces switching losses. To achieve this, an internal grid current loop with active damping is presented with an LCL filter to connect it to the utility grid. The problem of the filter natural resonance is solved by means of a virtual impedance (active damping), demanding no additional sensor. Experimental results obtained from a 200-W prototype achieved a European efficiency of 96.27% with a current total harmonic distortion of 3.7%. [ABSTRACT FROM AUTHOR]

A gate driving for power devices is a key technology to further improve switching characteristics. With the help of digital gate driver IC, the switching behavior of power devices can be enhanced even under high-speed switching. In this paper, an evaluation platform for determining the optimal switching pattern of an active gate drive control is proposed for an inverter circuit. A high speed optimization system is built up to search for an advantageous switching pattern that reduces total switching loss of two power devices in an inverter circuit and constrains surge voltage simultaneously. The proposed online optimization demonstrates its feasibility for the full-bridge inverter circuit, which is rated at 500 V with digital active gate drive control. Experimental results show that the proposed optimization system is able to obtain optimal switching pattern from $64^{60}$ possible combinations of switching patterns within 15 min, which is 6 times faster than the previous study. Optimizations can also conducted under different load current conditions. Eventually, the obtained optimal pattern yields up to 42% reduction in the total switching loss when it constrains surge voltage to minimum compared with the conventional driving pattern. [ABSTRACT FROM AUTHOR]

Electrically excited synchronous machines have shown potential to be an alternative to permanent magnet synchronous machines in electromobility and wind power applications. High-frequency wireless power transferring technology enables a compact design of brushless exciters for the machine. In this paper, a dynamic model of high-frequency brushless exciters is proposed for the purposes of operating condition monitoring and excitation control. The modeling is done by using arithmetic and differential equations as well as considering different operation modes of the system. The operation modes are defined based on the physical behaviors of the excitation circuit. Experiments are performed to verify the model with variations of different circuit parameters. Furthermore, parameter sensitivity study, component parameter selection, and loss analysis are conducted to demonstrate the effectiveness of the model. The model is therefore proposed as an effective tool to assist the design and optimization of the brushless excitation system. [ABSTRACT FROM AUTHOR]

One of the recent trends in power electronics field is to achieve high efficiency and compact size by using wide bandgap power devices such as silicon carbide (SiC) or gallium nitride switches. This paper compares the efficiency, the motor terminal voltage quality (dv/dt), and the common mode current of the SiC-based variable frequency drives (VFDs) according to the inverter topologies with and without the output filters. For this purpose, both the 2-level (2L) and 3-level (3L) topologies with SiC devices are built and tested. Here, the well-known 2L half-bridge inverter is compared with the well-known 3L T-type neutral point clamped inverter. A dv/dt filter and a sine wave filter have been discussed to satisfy the National Electrical Manufacturers Association standards as well. The experiments have been carried out with a 380-V/60-Hz, 3.7-kW induction motor and the custom designed power stages. Additionally, the experiments with both a 3-m and a 50-m cable length between the VFD and the induction motor are performed and reported. [ABSTRACT FROM AUTHOR]

In this paper, a new Lyapunov-based model predictive controller is proposed for a 7-level packed U-cell (PUC7) grid-connected inverter. A cost function of the proposed model predictive controller is designed from the system stability point of view, inspired by the Lyapunov control theory. The proposed controller eliminates the need for gains that are associated with cost function coefficients, as seen in classical model predictive control based controllers. Therefore, the control design problem is significantly simplified. In addition, the average switching frequency is also reduced, as shown in both simulation and experimental results, leading to a reduction in switching losses. Simulation and experimental tests, on a PUC7 lab prototype, demonstrate the excellent performance of the proposed control system, in terms of high disturbance rejection, robustness to parameter mismatches, and fast dynamic response. Such features qualify the proposed control strategy as a good candidate for grid-tied applications. [ABSTRACT FROM AUTHOR]

A novel single-stage high-frequency link three-phase ($3\phi$) inverter along with a modulation strategy is presented in this paper. The topology is targeted for grid integration of utility scale renewable and alternative energy sources like solar, fuel cell, and wind, where the power flow is unidirectional (from dc to ac). The primary side converter has a $3\phi$ voltage source inverter (VSI) structure along with an additional half-bridge leg. Sinusoidal pulsewidth modulation is implemented in the primary side converter. The three legs of the primary side VSI are zero voltage switched (ZVS) for most part of the line cycle. The additional half bridge leg is ZVS over the complete line cycle. The active switches in secondary side converter are line frequency switched and thus results in negligible switching loss. The converter switching process is described in detail to show the soft-switching of the primary side converter using the device capacitances and leakage inductances of the high-frequency transformers (HFTs). The HFT galvanic isolation results in high power density. A 4-kW laboratory scale hardware prototype is built and tested with the proposed modulation strategy. The experimental results are presented to verify the converter operation. [ABSTRACT FROM AUTHOR]

The efficiency improvement of the on–off controlled Class E dc–dc converter operated at 20 MHz switching frequency is investigated in this paper. It is found that with the on–off control, the input power of the converter during the on mode increases with the increase of the input voltage, and it can be reduced by increasing the switching frequency. With this discovery, a variable switching frequency (VSF) on–off control is proposed, which slightly increases the switching frequency when the input voltage increases, maintaining the input power during the on mode slightly higher than the rated output power over the entire input voltage range, and thus highly improving the efficiency of Class E dc–dc converter at high input voltage. A prototype of 9-V–18-V input, 10-W Class E dc–dc converter has been fabricated and tested in the lab. The experimental results show that the proposed VSF on–off control improves the conversion efficiency of the Class E dc–dc converter by 4%–10% compared to the constant switching frequency on–off control. [ABSTRACT FROM AUTHOR]

This paper presents a novel approach to derive a pulsewidth modulation (PWM) technique for the generalized multi-phase drive. This novel approach is called a phase traversing principle. The given phase traversing principle is applied to the proposed PWM technique for five-phase open-end winding induction motor drive fed from a single dc source. The proposed PWM technique has the benefits of phase clamping, symmetrical operation of inverters, and common-mode current (CMC) elimination. Thus, it reduces the switching losses and also minimizes the issue of the CMC. The symmetrical operation of dual inverters further helps in the even distribution of losses. Also, the proposed PWM technique gives a good harmonic performance. The performance of the proposed PWM technique is analyzed using the switching loss function and harmonic flux trajectory methods. The first analysis gives justification of the reduced switching losses. While the second analysis gives the deviations in the motor flux with respect to variation in. modulation indices The proposed PWM technique is verified with both simulation and hardware results. [ABSTRACT FROM AUTHOR]

In order to reduce switching loss of neutral point clamped three-level inverter (NPC TLI), generally discontinuous pulsewidth modulation (DPWM) is used. But it can result in dc offset and ac ripple on neutral point (NP) voltage. So a novel pulse sequence DPWM (NPSDPWM) is proposed to reduce switching loss and control NP voltage simultaneously in this paper. NP voltage is controlled by choosing proper clamping modes. To avoid unexpected switching action during changing clamping mode, an improved pulse sequence is also presented. The switching loss and NP voltage ripple of NPSDPWM, traditional and proposed DPWM in previous literature are compared, respectively. The experimental results show that NPSDPWM has well NP voltage control ability and the switching losses are reduced effectively. [ABSTRACT FROM AUTHOR]

Three-level inverter has an outstanding performance and is more advantageous in the switching vector selection than two-level inverter. In particular, the neutral-point voltage unbalance and common-mode voltage (CMV) reduction of three-level inverter should be carefully regulated for the appropriate operation, both of which, however, are mutually coupled resulting that the conventional space vector modulation (SVM) scheme cannot deal with them properly. To overcome this limitation, this paper proposes an improved space vector modulation (ISVM) technique to reduce the CMV and neutral-point voltage imbalance simultaneously. The generating mechanism of neutral-point voltage oscillation is derived. Based on the analysis, the proposed ISVM method adopts four voltage vectors (large, medium, small, and zero vectors) with adjusted dwell times to eliminate the ac unbalance of the neutral-point voltage. Considering the occurrence of neutral-point voltage disturbances, the dc neutral-point unbalance voltage is controlled by selecting the P-type or N-type small vector and adjusting the dwell times of small vectors for neutral-point voltage recovery. In addition, a novel switching sequence arrangement method with the minimal number of switches transition in one switching cycles and between switching cycles is proposed to reduce the total switching loss. Theoretical analysis and verification results show that the proposed ISVM scheme can reduce the magnitude of CMV to half of value using the conventional SVM, and an accurate control of ac and dc unbalanced neutral-point voltage can be obtained. [ABSTRACT FROM AUTHOR]

The magnetic resonant wireless power transfer (WPT) system with a class E inverter has wide application in mid-range power transmission, especially for several megahertz scenario. However, it is cumbersome for the existing modeling and analysis methods to obtain the analytical solution to the system variables, which limits the evaluation of system characteristic. This paper proposes a nonlinear mathematical model for the WPT system with a class E inverter. The equivalent small parameter method (ESPM) is first adopted to solve the proposed six-order nonlinear model, and symbolic-form steady-state periodic solutions are yielded. During the whole solving process, only three iteration steps are needed for the proposed method. Compared with other existing modeling and analysis methods, the symbolic periodic results acquired by the ESPM exhibit sufficient accuracy by virtue of the combination of more higher harmonics. Meanwhile, the calculation complexity is simplified remarkably. Simulation and available experiments validate the effectiveness and accuracy of the proposed method. [ABSTRACT FROM AUTHOR]

In this paper, a generalized switching modification method is proposed to reduce the root-mean-square (rms) current flowing into a dc-link capacitor in a dc–dc–ac structure consisting of a boost converter and a three-phase inverter. To analyze the current flowing into the capacitor, we analyze the currents at the respective converter and inverter sides. Based on this analysis, we derive an analytical method to find the modification time between the converter and inverter pulsewidth modulation (PWM) carriers through a Fourier series and approximation to facilitate real-time implementation. Real-time implementation of the modification time calculated by the derived method is described. To verify the validity of the proposed method, experimental results are presented based on a 1-kVA dc–dc–ac prototype. The proposed method has a better capacitor rms current reduction performance than the conventional method in various inverter power factors and PWM strategies. Especially, it has an excellent performance in mid-power factor level (0.95–0.1). [ABSTRACT FROM AUTHOR]

In this paper, a hybrid switch with the combination of large-current silicon (Si) insulated gate bipolar transistor (IGBT) and small-current silicon carbide (SiC) metal-oxide semiconductor field-effect transistor (mosfet) is utilized in a three-phase T-type three-level grid inverter. The hybrid switch can optimize the cost of the system while achieving high efficiency. The relationship between efficiency improvement and cost of the hybrid switch is investigated. Several switching patterns, which can decrease the loss of the small-current SiC mosfet for the hybrid switch, are studied. Different switching patterns for the hybrid switch of the grid inverter are compared based on the inverter efficiency. Finally, a 20 kW three-phase T-type three-level grid inverter prototype with the hybrid switch of large-current Si IGBT and small-current SiC mosfet (1:2.4 SiC/Si current ratio) is built to verify the main results. [ABSTRACT FROM AUTHOR]

This paper proposes a new pulse amplitude width modulation (PAWM) procedure for cascaded H-bridge multilevel inverters fed by dc voltage sources with unequal amplitudes. With proposed procedure, the generated output voltage is obtained modulating a sinusoidal reference signal at the desired fundamental frequency with equally spaced switching angles. It has been analytically demonstrated that, under these assumptions, all harmonics except those of order $n=2kl\pm 1$ , $k=1,2,\ldots$ are deleted from the output voltage waveform. After a detailed description of the method and a comparative analysis with others existing in the literature, its harmonics elimination capability has been experimentally verified with 5-, 7-, 9-, and 11-level cascaded H-bridge inverters, moreover, it has been mathematically demonstrated that it reduces total harmonic distortion below 5% with a 17-level inverter and it is capable of eliminating the first 49 harmonics considered by standards with a 27-level inverter. [ABSTRACT FROM AUTHOR]

A multiphase-interleaved non-isolated high step-up dc/dc resonant converter for high-current applications with wide load range is proposed in this paper. The converter consists of an inverter stage with multiple resonant inverters in parallel interleaving operation that is cascaded to a common diode–capacitor rectifier stage. The topology of the inverter stage is a variation of class E inverter, which is designed for voltage boosting and of which the voltage gain is insensitive to load change. The rectifier stage comprises multiple pairs (correlated to the number of inverters in parallel) of diodes in parallel and a small output capacitor, which makes it simple to implement and of low cost. Together, the voltage gain variance of the converter can be confined within a small value and zero voltage switching operation can be maintained over a wide load range. A detailed mathematical analysis of the proposed converter is conducted for systematizing its design. A prototype of the proposed converter with an input voltage of 23.6 V, a rated output voltage of 190 V, and a rated output power of 80 W at 486 kHz is constructed for verification. A frequency controller is implemented to achieve fine regulation of the output voltage. [ABSTRACT FROM AUTHOR]

This paper describes a novel family of single-phase single-stage buck–boost inverters using output unfolding circuits. Operation principles and component design guidelines along with modulation techniques are presented and discussed. The simulation results confirm all theoretical statements. Experimental setup of the most promising solution is assembled and tested, where the efficiency for different operation modes is analyzed. Finally, the pros and cons along with applications of the proposed solutions are discussed in the conclusions. [ABSTRACT FROM AUTHOR]

The class-E shunt inductor inverter (SII) topology typically operates based on zero-current switching (ZCS) and zero-derivative current switching (ZDCS) conditions. Based on these terms, the peak switch voltage and load resistance are eliminated as the major limitation parameters to implement the class-E SII with the desired design specifications. This paper introduces the design and analysis of the class-E SII with the specified deviation from both ZCS and ZDCS conditions. Therefore, 2 degrees of the design freedom are obtained. Two new parameters that are normalized by the dc-supply current are defined in terms of the deviation from ZCS, i.e., $\alpha $ and ZDCS, i.e., $\beta $. This operation mode of class-E SII is named as the nonzero current. The performance characteristics and design relationships are obtained in terms of the phase shift between the input and output voltages. The demonstration of the proposed operation mode is proven by fabrication of a prototype circuit with output power 10 W at 4-MHz operating frequency and close agreement between experimental outcomes with the simulation and theoretical results. [ABSTRACT FROM AUTHOR]

In this paper, the zero sequence circulating current in open winding permanent magnet synchronous machine (OW-PMSM) drives with common dc bus is systematically analyzed for the first time. It is revealed that the zero sequence circulating current is affected by zero sequence back-electromotive force, cross coupling voltages in zero sequence from the machine side, pulse-width modulation induced zero sequence voltage, and inverter nonlinearity from the inverter side. Particularly, the influences from the cross coupling voltages in zero sequence and parasitic effect of inverter nonlinearity are investigated for the first time in this paper. Then, the synthetic model of the equivalent zero sequence circuit is proposed as well. Each cause is studied independently via analytical modeling, finite element analysis, and experiments. Meanwhile, to tackle this issue, the relevant suppression strategy using frequency adaptive proportional resonant controller is presented and tested on the 3 kW OW-PMSM platform. [ABSTRACT FROM AUTHOR]

In this paper, a new space vector pulse width modulation method to extend the linear modulation range of a cascaded five level inverter topology with a single dc supply is presented. Using this method, the inverter can be controlled linearly and the peak phase fundamental output voltage of the inverter can be increased from 0.577 to 0.637 V\text{dc} without increasing the dc bus voltage and without exceeding the induction motor voltage rating. This new technique makes use of cascaded inverter pole voltage redundancy and property of the space vector structure for its operation. Using this, the induction motor drive can be operated till the full speed range (0–50 Hz) with the elimination of lower order harmonics in the phase voltage and phase current. The five-level topology presented in this paper is realized by cascading a two-level inverter and two full bridge modules with floating capacitors. The inverter topology and its operation for extending the modulation range is analyzed extensively. Simulation and experimental results for both steady-state and dynamic operating conditions are presented in this paper. [ABSTRACT FROM AUTHOR]

In this paper, an improved direct torque control (DTC) technique of a two-level inverter-fed five-phase induction motor (FPIM) drive for low-speed operation is presented. The operation of the FPIM with distributed winding requires the elimination of third-harmonic voltage, which, if not taken care of, would generate distorted stator current. For this, the concept of virtual vectors (VVs) is utilized. Before selecting the VVs for the DTC operation, a theoretical analysis is carried out to find the effects of these VVs on the torque and flux response of the FPIM under different speed and loading conditions. It is found that the rotor speed plays a crucial role in the selection of VVs. A particular VV has different effects on the torque change as speed varies. This analysis helps in the selection of VVs, hysteresis torque bandwidth, flux bandwidth, and efficient formation of sectors. Furthermore, in this paper, the performance of the FPIM during low-speed operation is improved by avoiding the demagnetization of the stator flux. To achieve this, a new modified lookup table is proposed. Superiority of the proposed method over the reported approaches is illustrated by experimental results. [ABSTRACT FROM PUBLISHER]

The degradation in power quality causes adverse economical impact on the utilities and customers. Harmonics in current and voltage are one of the most commonly known power quality issues and are solved by the use of a hybrid series active power filter (HSAPF). In this paper, a new controller design using sliding-mode controller-2 is proposed to make the HSAPF more robust and stable. An accurate averaged model of a three-phase HSAPF is also derived in this paper. The design concept of the robust HSAPF has been verified through simulation and experimental studies, and the results obtained are discussed. [ABSTRACT FROM AUTHOR]