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This paper studies pulse width modulation (PWM) techniques suitable for a four-level five-phase open-end winding (OeW) drive. The drive comprises a five-phase induction machine, supplied using two two-level voltage source inverters with isolated and unequal dc-link voltages, in the ratio 2:1. A decoupled carrier-based (CB) PWM modulation strategy, based on unequal voltage reference sharing between the two converters, is introduced in this paper. The stability of dc-link voltages in OeW drives is investigated next, using a novel analysis technique. Several modulation methods are analyzed and the results show that application of the coupled PWM technique, with carriers having in-phase disposition, leads to overcharging of the capacitor in the dc-link of the inverter intended to operate with the lower dc-link voltage. On the other hand, the proposed decoupled CB PWM scheme naturally eliminates the dc-link capacitor overcharging problem. These findings are verified experimentally, using open-loop V/f control. Two different decoupled CB modulation methods are compared and the best performing modulation method is selected and incorporated further into an OeW drive with field-oriented control. The presented steady state and transient experimental results demonstrate that the decoupled CB PWM technique is suitable for high-performance variable speed drive applications. [ABSTRACT FROM AUTHOR]

Increasing demands for power supplies have contributed to the population of high-frequency ac (HFAC) power distribution system (PDS), and in order to increase the power capacity, multilevel inverters (MLIs) frequently serving as the high-frequency (HF) source-stage have obtained a prominent development. Existing MLIs commonly use more than one voltage source or a great number of power devices to enlarge the level numbers, and HF modulation (HFM) methods are usually adopted to decrease the total harmonic distortion (THD). All of these have increased the complexity and decreased the efficiency for the conversion from dc to HF ac. In this paper, a nine-level inverter employing only one input source and fewer components is proposed for HFAC PDS. It makes full use of the conversion of series and parallel connections of one voltage source and two capacitors to realize nine output levels, thus lower THD can be obtained without HFM methods. The voltage stress on power devices is relatively relieved, which has broadened its range of applications as well. Moreover, the proposed nine-level inverter is equipped with the inherent self-voltage balancing ability, thus the modulation algorithm gets simplified. The circuit structure, modulation method, capacitor calculation, loss analysis, and performance comparisons are presented in this paper, and all the superior performances of the proposed nine-level inverter are verified by simulation and experimental prototypes with rated output power of 200 W. The accordance of theoretical analysis, simulation, and experimental results confirms the feasibility of proposed nine-level inverter. [ABSTRACT FROM AUTHOR]

Three-phase voltage-source inverters typically feature a significant amount of dc energy storage to maintain a stiff dc bus. In these cases, the dc-link capacitor is sized to store enough energy to maintain several tens of cycles of ac output at the rated power. In this paper, we propose to reduce the size of the dc-link capacitor dramatically to store enough energy to provide just one high-frequency switching cycle of the ac output power. The dc bus is no longer stiff, and hence, classical sinusoidal pulse-width modulation cannot be used. However, the stored energy modulation (SEM) proposed herein synthesizes high-quality sinusoidal output voltage waveforms, even with such tiny dc-link capacitors. In SEM, the switching intervals of the interconnecting switches are carefully determined nonlinear functions of various operating parameters such as reactive component sizing, switching frequency, load levels, etc. This paper presents the analytical and detailed design development of the SEM approach along with circuit simulation, experimental results, and comparative evaluation of a dc-to-three-phase system example. [ABSTRACT FROM PUBLISHER]

One of the main challenges of the solid-state transformer (SST) lies in the implementation of the dc–dc stage. In this paper, a quadruple-active-bridge (QAB) dc–dc converter is investigated to be used as a basic module of a modular three-stage SST. Besides the feature of high power density and soft-switching operation (also found in others converters), the QAB converter provides a solution with reduced number of high-frequency transformers, since more bridges are connected to the same multiwinding transformer. To ensure soft switching for the entire operation range of the QAB converter, the triangular current-mode modulation strategy, previously adopted for the dual-active-bridge converter, is extended to the QAB converter. The theoretical analysis is developed considering balanced (equal power processed by the medium-voltage (MV) cells) and unbalanced (unequal power processed by the MV cells) conditions. In order to validate the theoretical analysis developed in the paper, a 2-kW prototype is built and experimented. [ABSTRACT FROM PUBLISHER]

This paper presents a topology for bidirectional solid-state transformers with a minimal device count. The topology, referenced as dynamic-current or Dyna-C, has two current-source inverter stages with a high-frequency galvanic isolation, requiring 12 switches for four-quadrant three-phase ac/ac power conversion. The topology has voltage step-up/down capability, and the input and output can have arbitrary power factors and frequencies. Further, the Dyna-C can be configured as isolated power converters for single- or multiterminal dc, and single- or multiphase ac systems. The modular nature of the Dyna-C lends itself to be connected in series and/or parallel for high-voltage high-power applications. The proposed converter topology can find a broad range of applications such as isolated battery chargers, uninterruptible power supplies, renewable energy integration, smart grid, and power conversion for space-critical applications including aviation, locomotives, and ships. This paper outlines various configurations of the Dyna-C, as well as the relative operation and controls. The converter functionality is validated through simulations and experimental measurements of a 50-kVA prototype. [ABSTRACT FROM PUBLISHER]

This paper presents a pulse width modulation (PWM) technique for the minimization of the leakage current in the grid-connected/stand-alone transformerless photovoltaic (PV)-cascaded multilevel inverter (CMLI). The proposed PWM technique is integrated with the MPPT algorithm and is applied to the five-level CMLI. Furthermore, using the proposed PWM technique the high-frequency voltage transitions in the terminal and common mode voltages are minimized. Thus, the proposed PWM technique minimizes the leakage current of the PV array and electromagnetic interference filter requirement in the system without addition of any extra switches. Furthermore, this paper also presents the analysis for the terminal voltage across the PV array and the common mode voltage of the inverter based on the switching function. Using the given analysis, the effect of the PWM technique can be analyzed, as it directly links the switching function with the common mode voltage and leakage current. Also, the proposed PWM technique requires reduced number of carrier waves compared to the conventional sinusoidal pulse width modulation technique for the given CMLI. Complete details of the working principle and analysis with the support of simulation and experimental results of the proposed PWM technique are presented in this paper. [ABSTRACT FROM PUBLISHER]

In this paper, a new topology for half-bridge Z-source inverter is proposed. The proposed topology has only one impedance network. Unlike to the conventional half-bridge inverter, the proposed topology can provide zero voltage level at the output. It also increases output voltage level and stabilizes it in the desired value. Capacitor voltage stress in the proposed topology is low, and, therefore, nominal voltage of capacitor and cost decreases. In this paper, the steady-state analysis of the proposed inverter in two new operations which are named synchronous operation of diodes and asynchronous operation of diodes is conducted based on mathematics calculations. A method to obtain high-voltage gains by cascading the Z-network and combining middle inductors is presented that leads to cost, size, and weight reduction. Comparison among the proposed converter with conventional ones shows its excellent performance. The experimental results have good agreement with analytical analysis for the proposed topology. [ABSTRACT FROM PUBLISHER]

This paper presents a method for generating a multilevel dodecagonal voltage space vector structure using a single dc source for induction motor drives. Multilevel dodecagonal structure combines the advantages of both multilevel and dodecagonal structures, and hence, generates low dv/dt phase voltage along with the elimination of fifth- and seventh-order harmonics over the entire modulation range. This eliminates low-order harmonic currents and prevents the generation of sixth-order torque ripple in the motor. The topology used requires only one dc source making four-quadrant operation of the drive system simpler compared to previously proposed multilevel topologies generating dodecagonal space vector structures. The topology used consists of a three-level flying capacitor (FC) inverter cascaded with a capacitor fed H-bridge. The FC inverter operates at a lower switching frequency and the low-order harmonics are eliminated by the switching action of the cascaded H-bridge inverter. The capacitors in the cascaded H-bridge modules are maintained at a substantially smaller voltage compared to the dc-link voltage and are inherently balanced during the pulsewidth modulation operation. This results in low switching loss, in the FC inverter as well as in the cascaded H-bridge inverter. Experimental results are included to validate the operation of the topology and modulation scheme presented in this paper. [ABSTRACT FROM AUTHOR]

Zero-common-mode-voltage (CMV) operation of multilevel inverters results in reduced dc-bus utilization and reduced linear modulation range. In this paper, a method to increase the linear modulation range for zero-CMV operation without increasing the dc-bus voltage using a cascaded multilevel inverter with a single dc supply is presented. Using this method, the peak fundamental output voltage can be increased from 0.499 to 0.637  \textV\text{dc} with zero CMV inside the linear modulation range. Also, various pulse width modulation (PWM) switching sequences are analyzed in this paper, and the PWM sequence that gives minimum current ripple is used for the zero-CMV operation of the inverter. The inverter topology with single dc supply is realized by cascading a two-level inverter with two floating-capacitor-fed full-bridge modules. Simulation and experimental results for steady-state and dynamic operating conditions are presented to validate the proposed method. [ABSTRACT FROM AUTHOR]

This paper proposes a new direct torque control (DTC) method for a three-level neutral point clamped (3L-NPC) inverter-fed interior permanent magnet synchronous motor (IPMSM) drive. Theoretically, in comparison to a two-level inverter, a 3L-NPC inverter is advantageous for reducing the torque and flux ripples in DTC drives. Nonetheless, the ripples can still be excessive and detrimental if low switching frequencies are desired. To reduce the torque and flux ripples while maintaining a low average switching frequency, a switching table-based DTC scheme employing two voltage vectors in each sampling period is proposed in this paper. A duty ratio calculation method with minimal parameter dependence is developed, taking into account the dynamic torque and flux characteristics of an IPMSM. In addition, the problems of neutral point voltage fluctuations and smooth voltage vector switching, which are inherited from the 3L-NPC inverter, are addressed. Simulation and experimental results are presented to prove the effectiveness of the proposed method. [ABSTRACT FROM PUBLISHER]

This paper proposes a dual-space vector control scheme for the open-end winding permanent magnet synchronous motor (OEW-PMSM) drive fed by the dual inverter with a single dc supply. Potential zero-sequence current in the open-end winding drive system has to be considered since it causes circulating current in the winding and leads to high current stress of power semiconductor devices and high losses. Zero-sequence current in open-end winding ac motor drives is usually caused by the zero-sequence voltage, and therefore switching combinations which do not produce zero-sequence voltage are used to synthesize the reference voltage in existing methods. But even so, the zero-sequence voltage can also be produced by the dead time of the inverter. In order to suppress zero-sequence current in the OEW-PMSM drive, a dual-space vector control scheme is proposed and a novel dual-inverter space vector pulse width modulation (PWM) with the zero-sequence voltage reference is employed to regulate system zero-sequence voltage in this paper. Compared with existing dual inverter PWM strategies, the novel algorithm build a regulation mechanism for the zero-sequence voltage. The proposed method is compared with the conventional vector control by simulations and experiments, and the results shown that the proposed scheme can suppress zero-sequence current effectively. [ABSTRACT FROM AUTHOR]

In this paper, the near-state pulsewidth modulation (NSPWM), adapted to be implemented in dual-voltage-source inverter (VSI) fed open-end motor, is proposed with the aim of mitigating low-order harmonics (which lead to current total harmonic distortion (THD) minimization). The following two proposed methods are studied in detail: 1) fixing phase angle displacement (PAD) between two VSIs to 120° while adjusting the modulation index (MI); and 2) fixing MI to the predetermined value (wherein low-order harmonics are highly mitigated) while adjusting PAD. Furthermore, the proposed approaches enhance efficiency by limiting the number of commutations within the switching interval. The paper also presents the mathematical approaches to accurately determine low-order harmonic components and switching losses for dual-VSI structure. The experimental setup, including dual-VSI and open-end induction motor, is assembled in the laboratory to evaluate performance of the proposed method. Finally, the simulation results, carried out in the MATLAB/Simulink environment, are found to be in close agreement with experimental data. [ABSTRACT FROM AUTHOR]

Magnetically coupled impedance-source (MCIS) networks are recently introduced impedance networks intended for various high-boost applications. It employs coupled magnetic in the circuit to achieve higher voltage gain. Various MCIS networks have been proposed in the literature for myriad applications; however, due to effective role of system modeling in the closed-loop controller design, this paper is allocated to small-signal modeling and analysis of MCIS converters. The modeling is performed by means of the circuit averaging and averaged switch technique. A generalized small-signal derivation is demonstrated for pulse width modulation (PWM) MCIS converters and it is shown that the derived transfer functions can simply be applied to Y-source, Γ-source, and T-source impedance networks. Various transfer functions for capacitor voltage, output voltage, magnetizing current, input and output impedance are derived and have been validated through frequency and dynamic responses of computer simulation results. In addition, a comprehensive analysis has been done for all mentioned PWM MCIS converters regarding their circuit parameters. Furthermore, the effect of considering the equivalent series resistances of capacitor and inductor on the stability margin of MCIS converters is revealed in this paper. Finally, in order to validate the derived transfer functions and to consolidate the perfumed analysis, experimental results are presented for all mentioned MCIS converters. [ABSTRACT FROM PUBLISHER]

Based on the Z-source inverter, this paper proposes a novel commutation torque ripple reduction strategy for brushless DC motor (BLDCM). The proposed strategy employs the same modulation mode in both the normal conduction period and the commutation period, and the commutation torque ripple is reduced by regulating the shoot-through vector and active vector duty cycles. The proposed detection method acquires the end point of commutation by comparing the clamped terminal voltages with reference zero level, and the signal-noise-ratio of the detection is improved by avoiding the attenuation of the terminal voltages. Furthermore, a certain pulse width of the shoot-through vector can not only reduce the commutation torque ripple but also provide a new opportunity to detect the end point of commutation. Moreover, Z-source inverter provides the buck–boost ability for BLDCM drive system, then the dc voltage utilization can be improved, and the safety of the drive system can also be improved. In addition, this paper analyzes the terminal voltages during each vector. The experimental results verify the correctness of the theories and the effectiveness of the proposed approach. [ABSTRACT FROM PUBLISHER]

This paper proposes a new fault-tolerant strategy for a multilevel converter with an integrated impedance-source network. The proposed fault-tolerant strategy leverages the flexibility provided by the impedance-source network to implement the fundamental phase-shift compensation (FPSC) method in order to restore operation of a multilevel converter with one or more faulty switches to the prefault conditions. In case of a fault occurrence, the proposed fault-tolerant strategy makes the most use of the remaining converter capacity and generates balanced line-to-line voltages, while evenly distributing an inevitable voltage stress increase, over all converter switches. In this paper, first, a brief background about an impedance-source based cascaded H-bridge converter and a suitable modulation method for it is provided. Then, the FPSC method is explained and the proposed fault-tolerant strategy based on this method is introduced. Finally, several experimental results from a prototype converter are provided to validate the operation of the proposed strategy. [ABSTRACT FROM PUBLISHER]

In several electrical dc–ac power conversions, the ac output voltage is higher than the input voltage. If a voltage-source inverter (VSI) is used, then an additional dc–dc boosting stage is required to overcome the step-down VSI limitations. Recently, several impedance source converters are gaining higher attentions [1], [2], as they are able to provide buck-boost capability in a single conversion stage. This paper proposes the merging of the boost stage and the VSI stage in a single stage dc–ac power conversion, denoted as split-source inverter (SSI). The proposed topology requires the same number of active switches of the VSI, three additional diodes, and the same eight states of a conventional space-vector modulation. It also shows some merits compared to Z-source inverters, especially in terms of reduced switch voltage stress for voltage gains higher than 1.15. This paper presents the analysis of the SSI and compares different modulation schemes. Moreover, it presents a modified modulation scheme to eliminate the low frequency ripple in the input current and the voltage across the inverter bridge. The proposed analysis has been verified by simulation and experimental results on a 2.0-kW prototype. [ABSTRACT FROM PUBLISHER]

This paper shows how to use modular Marx multilevel converter diode ( \textM^3 CD) modules to apply unipolar or bipolar high-voltage pulses for pulsed power applications. The \textM^3 CD cells allow the assembly of a multilevel converter without needing complex algorithms and parameter measurement to balance the capacitor voltages. This paper also explains how to supply all the modular cells in order to ensure galvanic isolation between control circuits and power circuits. The experimental results for a generator with seven levels, and unipolar and bipolar pulses into resistive, inductive, and capacitive loads are presented. [ABSTRACT FROM AUTHOR]

The paper proposes a method of active switching harmonics current reduction in the dc-link capacitor of a two-level, three-phase, back-to-back converter. Based on the derived analytical solution for switching harmonic currents in the dc-link, it is shown that by specific control over the pulsewidth-modulated (PWM) carriers’ phase angles, the targeted harmonics of the rectifier and the inverter can be synchronized in phase such that their cancellation occurs in the dc-link capacitor. This synchronization is provided by harmonic phase feedback control. A three-step procedure to implement the method is detailed in the paper. The effectiveness of the proposed approach is verified experimentally. [ABSTRACT FROM AUTHOR]

This paper proposes a new topological configuration for a unified power quality conditioner (UPQC). Generally, the power structure of the three-phase three-wire UPQC consists of two back-to-back connected six-switch inverters. For this configuration, out of 12 switches, six of the series inverter switches will be underutilized most of the time. To improve the semiconductor utilization and consequently to reduce the total switch count, this paper proposes a new reduced switch topology for the UPQC. The proposed topology is realized using only ten switches and retains all the performance merits of the 12-switch UPQC while minimizing its underutilization without increasing the switch VA rating. The paper provides a detailed analytical study and evaluation by comparing the proposed topology with the twelve- and nine-switch-based UPQC system configurations. The feasibility of the proposed topology is validated through experimental investigation. [ABSTRACT FROM AUTHOR]

This paper proposes a new fault-tolerant strategy for the purpose of revamping the performance of three-phase multilevel (ML) converters with faulty switches. The proposed fault-tolerant strategy is based on an adaptation of the modified space vector modulation (SVM) technique to the fundamental phase-shift compensation method. The proposed fault-tolerant strategy generates balanced line-to-line voltages with increased voltage levels in the faulty condition. In this paper, first a brief background about cascaded H-bridge (CHB) ML converters and SVM technique is provided. Then the proposed fault-tolerant strategy and the modified SVM technique are presented. Finally, several experimental results are provided to validate operation of the proposed strategy. [ABSTRACT FROM AUTHOR]

Aimed at the problem that the auxiliary commutation circuit (ACC) of auxiliary resonant commutated pole (ARCP) inverters has a high loss in commutation processes, this paper presents a novel modulation strategy with shunt dead time based on a double ARCP (DARCP) inverter. In comparison with the original modulation strategy, this modulation strategy cannot only achieve soft switching for all switches, but also avoid the superposition of resonance current and load current at commutation moments in double ACCs (DACCs) and make the maximum current through DACCs approximately equal to load current in commutation processes. So, the circulating current loss in DACCs and the current stress of auxiliary switches can be effectively reduced. According to the equivalent circuits in different operation modes under the novel modulation strategy, this paper analyzes the operation principle, soft-switching implementation condition, and optimal parameter design procedure of the DARCP inverter. Finally, a 10-kW–16-kHz DARCP inverter prototype with insulated gate bipolar transistor-based switches is built. Experimental results are given to demonstrate the validity and features of the DARCP inverter under the novel modulation strategy. [ABSTRACT FROM AUTHOR]

Model predictive control (MPC) has been widely advocated as a design strategy for many aspects of industrial electronics. The methodology has been strongly promoted by some researchers but has also attracted criticism from others. In this context, the purpose of this paper is twofold. First, we show that many existing and popular control strategies, including finite set MPC and linear controllers [proportional integral, proportional resonant (PR)], can be viewed as special cases of MPC. Second, we show that the predictive control framework allows one to embellish these classical control architectures with novel features and to design new and advanced control architectures to address various challenges posed by power electronics applications. The findings of the paper are supported by a practical example of designing of a novel form of PR controller with superior tracking performance and delay compensation, confirmed via simulation and experiments. [ABSTRACT FROM PUBLISHER]

This paper presents a model predictive control technique applied to a dual-active bridge inverter where one of the bridges is floating. The proposed floating bridge topology eliminates the need for isolation transformer in a dual inverter system and therefore reduces the size, weight, and losses in the system. To achieve multilevel output voltage waveforms, the floating inverter dc-link capacitor is charged to the half of the main dc-link voltage. A finite-set model predictive control technique is used to control the load current of the converter as well as the floating capacitor voltage. Model predictive control does not require any switching sequence design or complex switching time calculations as used for space vector modulation; thus, the technique has some advantages in this application. A detailed analysis of the converter as well as the predictive control strategy is given in this paper. Simulation and experimental results to validate the approach are also presented. [ABSTRACT FROM PUBLISHER]

This paper presents a three-phase open-end winding induction motor drive. The drive consists of a three-phase induction machine with open stator phase windings and dual-bridge inverter supplied from a single dc voltage source. To achieve multilevel output voltage waveforms, a floating capacitor bank is used for the second of the dual bridges. The capacitor voltage is regulated using redundant switching states at half of the main dc-link voltage. This particular voltage ratio (2:1) is used to create a multilevel output voltage waveform with three levels. A modified modulation scheme is used to improve the waveform quality of this dual inverter. This paper also compares the losses in the dual-inverter system in contrast with a single-sided three-level neutral point clamped converter. Finally, detailed simulation and experimental results are presented for the motor drive operating as an open-loop v /f controlled motor drive and as a closed-loop field-oriented motor controller. [ABSTRACT FROM PUBLISHER]

This paper describes active shunt LC decoupling circuit with ceramic capacitors, allowing volume reduction and lifetime improvement of the high-voltage dc filters. Active filtering is based on the energy exchange between high-voltage coupling and low-voltage auxiliary capacitors. The coupling capacitor enables use of the low-voltage switched-mode power stage and low-voltage auxiliary decoupling capacitor. Advantageously, this allows to reduce power dissipation, switching frequency ripple current, and to reduce volume of the circuit. Additionally, power efficiency and capacitor lifetime are improved by using recent high-voltage coupling multilayer ceramic capacitors, reaching very low ESR. This paper provides description of the active decoupling capacitor, and shows an example of the feedback control. Obtained performances are demonstrated on the prototype of 1300-μF/450-V capacitor, allowing to reduce volume by three, when compared to ordinary 450-V electrolytic capacitor. [ABSTRACT FROM AUTHOR]

The increasing interest in multiphase drive systems has led to the extension of inverter topologies and pulse width modulation (PWM) methods from three-phase to multiphase occasions. Carrier-based PWM (CPWM) dominates space vector PWM when the phase number increases, because of its simple computation and modular implementation. Although intensive work has been done on modifying PWM methods to reduce the common-mode voltage (CMV), not enough work has been done on CPWM methods with CMV reduction for multiphase drives. This paper extends the phase-shifted sinusoidal PWM (PS-SPWM) method for five-phase and six-phase two-level voltage-source inverters (VSI) and employs the intersection-plotting method and Fourier analysis to reveal the nature of the CMV. Both experiment and simulation results comply with theoretical analysis that compared with the conventional SPWM, the PS-SPWM can effectively reduce the CMV in peak-to-peak value and RMS value, though it leads to a higher phase current distortion. In addition, the hardware realization of PS-SPWM for multiphase inverters by a distributed control system is presented in this paper. [ABSTRACT FROM AUTHOR]

Two three-level inverters driving an open-end winding induction motor can generate equivalent voltage waveforms as a single five-level inverter-based drive. In addition, it can bring in benefits such as reduced dc-link voltage, less number of devices, and fault-tolerant capability, which is favored in high-power motor drive applications. The main challenge with this type of configuration is the appearance of large zero-sequence current circulating between the two inverters, which generates extra losses in the switching devices and the motor as well as affects the normal operation of the machine. Another challenge is to balance the dc-link neutral point voltage of the two three-level inverters. This paper has proposed a simplified decoupled space-vector pulsewidth-modulation (PWM) strategy to eliminate the averaged zero-sequence voltage in each switching cycle by the placement of redundant vectors of each individual inverter using a time shift. Neutral point voltage balance is further achieved by adjusting the time duration of the redundant vectors. In this paper, it is shown that it is possible to operate this kind of drive configuration with a single dc power supply and achieve averaged zero-sequence voltage elimination and neutral-point voltage balancing at the same time. Experimental results of a 5.5-kW dual three-level inverter drive using the proposed PWM strategy are presented, which validates the control method and drive configuration. [ABSTRACT FROM PUBLISHER]

Paralleled inverters have the merits of high power rating, improved reliability, and convenient maintenance. However, zero-sequence circulating current (ZSCC) will occur and lead to current distortion and system loss. The ZSCC control is more complicated when three-level topology is utilized and paralleled number is increased. Therefore, this paper proposes a simplified ZSCC suppression scheme for multi-paralleled three-level T-type inverters (3LT2Is). A novel equivalent model is developed and the ZSCC controller based on the new model is easier to implement. Thus, the number of paralleled inverters can be increased without complicating the control scheme and the inverters could be switched on or off optionally. Besides, Feed-Forward (FF) strategy is adopted to eliminate the ZSCC spikes caused by symmetrical three-level space vector modulation. The effectiveness of the proposed control scheme is verified by both simulation and experimental results. [ABSTRACT FROM AUTHOR]

This paper introduces a three-phase grid-connected inverter for commercial-scale photovoltaic systems. The circuit topology combines an ac-inductor-less active bridge with a parallel-connected pulsewidth modulation inverter acting as an instantaneous reactive power compensator. The active bridge, called a 120° conduction inverter, operates at a switching frequency equal to the grid frequency and outputs a 120° rectangular current, while the compensator eliminates the harmonic currents included in the rectangular current. The main advantage of this strategy is the reduction in size of the required ac inductor by a factor of 4, as well as the reduction of power losses in the switching devices. The theoretical analysis clearly shows that the compensator can synthesize a sinusoidal output current by controlling only instantaneous reactive power, thus eliminating the need for electrolytic capacitors. A 5-kW experimental setup validates the operating principle and the control method of the proposed inverter and exhibits an inverter efficiency as high as 99.2% with Si superjunction mosfets. [ABSTRACT FROM AUTHOR]

Three-level neutral-point-clamped (NPC) inverters are being widely adopted in low-voltage low-power applications. For an intended application, the modulation strategy and the operating conditions are the two key factors that highly influence the major performance indices of the NPC inverter, such as efficiency, harmonic distortion, and voltage oscillations at neutral point (NP). Considering dynamic loading applications where the operating point varies significantly, this paper proposes an improved adjustable pulsewidth modulation (PWM) strategy for a three-level NPC inverter that can alter its modulation pattern to meet desired performance objectives for the full operation range. It has been shown that by varying two control parameters namely discontinuity control parameter and bias control parameter, the proposed modulation strategy changes its pattern between the most efficient generalized discontinuous PWM to NP oscillations-free partial dipolar PWM strategy. Additionally, to obtain a tradeoff between the performance parameters—efficiency, NP oscillations, and waveform quality—The proposed strategy has the ability to settle at the intermediate modulation patterns by transforming into a hybrid modulation signal. Furthermore, considering NP voltage unbalance mitigation as major technical challenge in adjustable modulation strategy, a voltage unbalance compensator that exhibits satisfactory balancing performance for the entire variations of modulation patterns and operating conditions has also been presented. The performance of the proposed modulation strategy in conjunction with voltage unbalance compensator has been evaluated in simulation by widely varying the speed and load of induction motor, and verified in experimentation. [ABSTRACT FROM AUTHOR]

This paper presents design of an isolated high-step-down dc–dc converter based on a class-DE power stage, operating at a 10-MHz switching frequency using enhancement-mode gallium nitride transistors. The converter operating principles are discussed, and the power stage design rated for 20 W is presented for a step down from 200–300 V input to 0–28 V output. Commercially available magnetic materials were explored and the high-frequency resonant inductor and transformer designs using a low-loss Fair-Rite type 67 material are presented. Finite-element simulations have been performed to estimate the parameters of magnetics at 10-MHz. Experimental results are presented at 12 W, 254 V input to 22 V output and 5 W, 254 V input to 14 V output on a laboratory prototype operating at 10-MHz. At 20 W, the experimental prototype achieved an efficiency of 85.2%. [ABSTRACT FROM AUTHOR]

This paper presents a novel model predictive control (MPC) for the T-type single-phase three-level inverters. The cumbersome procedure in tuning of weighting factors is eliminated so that the implementation of the proposed MPC becomes easy. The constant switching frequency is achieved during the control implementation in order to facilitate the filter design. In order to optimize the distribution of the output current harmonics, multiple voltage vectors are employed in each control cycle with their application times setting inversely proportion to the respective cost function. The redundant small voltage vectors are utilized to balance the neutral point voltage of the inverter by directly regulating the upper and lower dc-link capacitors voltages. Finally, the proposed MPC algorithm is experimentally evaluated and compared with other two unfixed switching frequency MPC algorithms in terms of the steady state, transient performance, and parameter sensitivity. [ABSTRACT FROM AUTHOR]

This paper presents a new reconfiguration module for asymmetrical multilevel inverters in which the capacitors are used as the dc links to create the levels for staircase waveforms. This configuration of the multilevel converter makes a reduction in dc sources. On the other hand, it is possible to generate 13 levels with lower dc sources. The proposed module of the multilevel inverter generates 13 levels with two unequal dc sources (2VDC and 1VDC). It also involves two chargeable capacitors and 14 semiconductor switches. The capacitors are self-charging without any extra circuit. The lower number of components makes it desirable to be used in wide range of applications. The module is schematized as two back-to-back T-type inverters and some other switches around it. Also, it can be connected as a cascade modular which leads to a modular topology with more voltage levels at higher voltages. The proposed module makes the inherent creation of the negative voltage levels without any additional circuit (such as H-bridge circuit). Nearest level control switching modulation scheme is applied to achieve high-quality sinusoidal output voltage. Simulations are executed in MATLAB/Simulink and a prototype is implemented in the power electronics laboratory in which the simulation and experimental results show a good performance. [ABSTRACT FROM AUTHOR]

Some electrified vehicles, for example the Toyota Prius, integrate a dc–dc converter between the battery pack and the traction inverter to increase the powertrain efficiency. However, adding this extra converter adversely affects the cost and power density of the powertrain due to the additional components, such as the switches and the inductor, that are expensive and heavy in high-power converters. The concept of the multi-source inverter was previously introduced as an alternative solution to reduce the power rating of the dc–dc converter while keeping similar powertrain performance. In this paper, the implementation of the multi-source inverter in a hybrid power-split powertrain is discussed. The operating modes during both dc–ac and ac–dc conversions are detailed and a prototype is experimentally tested with a load. New control strategies of the proposed powertrain show that three out of five operating modes bring new opportunities in terms of battery charging and power rating reduction of the dc–dc converter. A vehicle-level simulation model is developed in MATLAB/Simulink to quantify the benefits of the proposed topology. Simulations are performed for four drive cycles to compare the power profile of the dc–dc converter of the suggested powertrain with the Toyota Prius. The average power transferred by the dc–dc converter can be reduced by up to 25 $\%$ in most drive cycles tested. [ABSTRACT FROM AUTHOR]

A variable switching frequency space vector modulation control method is proposed in this paper. It is used to achieve zero-voltage switching (ZVS) for two parallel 180° interleaved three-phase grid-connected voltage-source inverters at unity power factor. A wide range of ZVS can be achieved without any additional sensor, auxiliary circuit, or current zero-crossing detection circuit. The carrier wave frequency is easy to be calculated and updated with digital control. The current ripple is precisely predicted and controlled to minimize unnecessary circulation loss. The high current ripple at the inverter side can be considerably canceled by the parallel interleaved configuration. LCL filter is used to further attenuate the current ripple and improve the power quality at the grid side. The switching loss can be significantly reduced especially by using a wide bandgap device with low turn-off loss. The power density is greatly improved owing to the high switching frequency and low component parameters of the filter. A 4.5-kW simulation and experimental prototype interfacing 400 V dc with a three-phase 110-V ac grid is developed to verify the performance of the proposed control strategy. [ABSTRACT FROM AUTHOR]

Leakage current reduction is one of the important issues for transformerless photovoltaic (PV) systems. Many interesting solutions have been reported to reduce the leakage current for three-phase PV inverters. However, most of them are limited to two-level inverters. Moreover, there is a potential risk of the overcurrent phenomenon. In order to solve the problem, a Z-source three-level four-leg inverter with a new modulation strategy is proposed in this paper. First, the mathematical modeling of the three-level four-leg Z-source inverter for leakage current reduction is established for the first time. Second, a new carrier-based modulation strategy is proposed by utilizing the effective large, medium, small, and zero vectors, instead of the invalid vectors, to achieve the constant common-mode voltage, as well as the leakage current suppression. Finally, the proposed solution is carried out on the Texas Instruments TMS320F28335 DSP + Xilinx XC3400 field-programmable gate array digital control hardware platform. The experimental results verify the effectiveness of the proposed solution. [ABSTRACT FROM AUTHOR]

This paper identifies extra junction capacitances and switching commutation loops introduced by line-frequency devices (i.e., non-active every other half line cycle) in three-level ac/dc converters and investigates the corresponding effects. Junction capacitances and power loops are well known as the key factors that impact converter switching loss and device stress, thus influence device selection, power stage layout, and thermal design. By examining switching transients of the commonly used T-shaped and I-shaped three-level converters, the cause and mechanism of the extra junction capacitances and power loops are presented. The impacts on switching loss, device voltage stress, and ac-side voltage/current distortion are respectively reported and analyzed. A loss calculation scheme for the three-level converter to include that extra loss is proposed. A power layout scheme to mitigate the device voltage stress is provided. Compensation and modeling of the voltage and current distortion are also proposed. Experimental results conducted on several types of three-level converter prototypes including a gallium nitride based 115 $V_{{\text{ac}}}{\text{/650}}$ Vdc/1.5-kW/450-kHz Vienna-type rectifier and a SiC mosfet based 1-kV/10-kW/280-kHz three-level active neutral-point-clamped inverter confirm the presented effects and verify the associated analysis and solutions. [ABSTRACT FROM AUTHOR]

A new boost-type multilevel inverter using switched capacitor structure is proposed. The main feature of the proposed inverter is boosting and multilevel output with small number of components. Due to the passive voltage balancing of each capacitor maintains a constant voltage without additional control. In this paper, the operation principle, the modulation method, the voltage/current stresses on switches and the determination of capacitances, the simulation results with MATLAB/Simulink R2015a, the experimental results, and the 2-kW simulation are shown. The simulation and the experiments were conducted under resistive load and inductive load conditions. In addition, the load variation was conducted in the experiment. Under both resistive load and inductive load conditions, the obtained waveforms by simulation and experiment agreed well with the theory. In the load variation experiment, the obtained waveforms were not distorted and the capacitor voltages maintained constant. [ABSTRACT FROM AUTHOR]

This paper explores the issue of the neutral-point oscillation in the four-leg neutral-point clamped inverter. Such an issue is closely associated with the neutral-point current, so this study models the inverter on the dc side to clarify its relationship and presents a three-dimension pulsewidth modulation to eliminate the neutral-point oscillation. In addition, an offset-injection approach to reducing the neutral-point oscillation is also investigated and discussed. The laboratory test results will validate the analysis of the proposed approach, and a discussion will be presented to evaluate the effectiveness of eliminating the neutral-point oscillation. [ABSTRACT FROM AUTHOR]

The strive to increase the energy yield of photovoltaic (PV) power systems has made PV module integrated dc–dc converters (dc-MICs) a reality of modern PV plants. These converters regulate their input voltage, and their dynamic behavior is heavily influenced by the non-linear characteristic of the PV module. The regulation of the PV module voltage and average inductor current by means of a linear cascaded controller is a popular control technique, simplifying the converter dynamics, and providing inherent current limiting; however, it is prone to instability depending on the interaction between the PV source and the interfacing converter, as well as the value of the controller parameters. These factors present a clear challenge for control design; moreover, the converter transient response undesirably depends on the PV module operating point. In order to solve these issues, while maintaining regulation of PV module voltage and average inductor current, this paper proposes to adopt a non-linear controller designed with the feedback linearization control (FLC) technique. The control laws are derived and implemented in a non-inverting buck–boost dc module integrated converter, as this is a favorite topology for the PV interfacing application. A digitally controlled converter prototype is built and used to obtain experimental results, where the FLC technique is compared with a linear cascaded control technique. The results confirm the superior performance of the presented FLC technique, which is robust and able to regulate the converter input voltage with fast and consistent dynamics, regardless of the PV module or load operating conditions. [ABSTRACT FROM AUTHOR]

The three-level dual-inverter connected to five-phase open-end winding induction motor (FPOEWIM) drive with a single dc source results in the flow of common mode current (CMC). The CMC flows through the common dc bus connected to dual-inverter and the motor phase windings. The CMC can be eliminated by using the switching states that can generate zero common mode voltage (CMV). In case of FPOEWIM, these switching states may result in higher current ripple. This paper proposes a decoupled pulsewidth modulation (PWM) technique to reduce the motor phase current ripple by using nearest possible space vector locations (SVLs) with zero as well as non-zero CMV. The use of non-zero CMV states results in CMC. So, the CMC is averaged to zero using sample-averaged common-mode current elimination (SACE) PWM technique in conjunction with decoupled PWM, which is named as DSACE PWM technique. Furthermore, the application of the proposed PWM is also supported using simulation for the closed-loop control scheme, such as DTC. Also, the proposed decoupled and DSACE PWM techniques are verified experimentally and the results are compared with the conventional 144° decoupled PWM technique. [ABSTRACT FROM AUTHOR]

In this paper, a variable switching frequency space vector pulsewidth modulation control is proposed. It is used to achieve zero voltage switching (ZVS) for a three-phase grid-connected voltage source inverter with unity power factor. A wide range of ZVS can be realized without any additional sensors, auxiliary circuits, or current zero crossing detection circuits. The switching frequency can be easily calculated by a digital controller. The frequency variation range in a line cycle is only about 1.5 times at any specific load. An LCL filter is used to attenuate the high current ripples at the inverter side, and active damping is adopted to avoid the resonance and reduce the filter power loss. The switching loss can be significantly reduced by using silicon carbide mosfets so that the conversion efficiency is high. The power density can also be improved due to the high switching frequency and the low inductance value of the filter. The operating principle, design considerations, and loss analyses are discussed in detail. A 3.5-kW simulation and experimental prototype interfacing a 350–400-V dc with a three-phase 110-V ac grid is developed to verify the performance of the proposed control strategy. [ABSTRACT FROM AUTHOR]

SiC mosfets allow a higher frequency, lighter weight inverter over their Si counterparts for electric vehicle (EV) applications. However, using SiC-based EV traction inverters is likely to increase the shaft voltage in an ac motor drive system, which significantly affects the reliability of the system. This paper investigates the impact of high-speed switching of SiC devices and high switching frequency of SiC-based inverter on the common-mode voltage (CMV) and the shaft voltage. It is theoretically illustrated and experimentally demonstrated that the high switching frequency increases the amplitude of the shaft voltage, while the fast switching speed has limited influence on both CMV and the shaft voltage. Afterward, active zero state pulsewidth modulation (AZSPWM) and common-mode chokes are employed to mitigate the shaft voltage. The experimental results show that either the AZSPWM modulation scheme or common-mode chokes have the capability to minimize the shaft voltage. Better performance can be achieved by utilizing both techniques simultaneously. It is also observed that the high switching frequency enabled by the fast-speed SiC device is able to be helpful to the use of reduced shaft voltage technologies. [ABSTRACT FROM AUTHOR]

This paper introduces a new configuration of bidirectional multilevel converter in electric vehicle (EV) applications. It has multilevel dc–dc converter with a dc link capacitor voltage balance feature. The multilevel dc–dc converter operates in a bidirectional manner, which is a fundamental requirement in EVs. Compared to the conventional configurations, the proposed one only implements two extra power switches and a capacitor to balance the voltage of the T-type multilevel inverter (MLI) capacitor over a complete drive cycle or at fault conditions. Therefore, no extra isolated sensor, control loops, and/or special switching pattern are required. Moreover, the proposed configuration due to the high-frequency cycle-by-cycle voltage balance between ${C_N}$ and ${C_P}$ , the bulky electrolytic capacitors used in T-type MLI, are replaced with more reliable longer life film capacitors. This will result in a size and weight reduction of the converter by 20%. This allows more real estate for the EV battery in the chassis’ space envelope to increase its capacity. The proposed configuration is tested and validated using a matlab/Simulink simulation model. A laboratory prototype of 1 kW is built to provide the proof of concept results as well. [ABSTRACT FROM AUTHOR]

This paper proposes a single-vector-based model predictive control (MPC) for an induction motor drive supplied by a three-level neutral-point-clamped inverter operating at a low switching frequency. Unlike the torque and flux control in the conventional MPC, the proposed MPC tries to minimize the error between the applied voltage vector and a reference voltage vector obtained based on the principle of deadbeat control, thereby reducing the number of weighting factors in the cost function. To reduce the computational burden and restrict the high jumps in both phase and line voltages, two switching tables are proposed and compared for the preselection of candidate voltage vectors. The neutral point potential fluctuation and switching frequency are also included in the cost function to achieve the balance between the upper and lower dc voltages and a relatively low switching frequency. Furthermore, a speed adaptive stator flux observer with a novel gain matrix is proposed to achieve speed-sensorless operation, which has a higher speed and flux estimation accuracy than conventional fixed gains. Finally, the proposed MPC is extended to the field-weakening operation by adjusting the torque and stator flux references online, which significantly widens the speed range and improves the practical value of the MPC. The effectiveness of the proposed method is confirmed by the experimental results obtained at an average switching frequency of less than 600 Hz. [ABSTRACT FROM AUTHOR]

Due to the pulsating power at the inverter output terminals, the passive storage elements of the boost stage of the current-fed switched inverter (CFSI) contain a power frequency harmonic component (100 Hz), apart from dc and switching frequency components. In prior designs, the second harmonic component is suppressed by increasing the size of the input filter inductor and capacitor or by using additional circuits. This paper presents a complete characterization of a control-based approach to suppress the power frequency harmonic component in the input inductor current of a CFSI. It also presents a comprehensive characterization of the harmonic power redistribution. Using the proposed approach, it is demonstrated that the inductor value of a CFSI is reduced by 61% for the same peak-to-peak ripple. This leads to an improvement in the conversion ratio, efficiency, and power density of the overall converter. A SiC MOSFET-based CFSI with 75-kHz switching frequency is used to verify the proposed design philosophy. [ABSTRACT FROM AUTHOR]

This paper presents a high-efficiency inverter with the aid of the soft-switching technology, which is accomplished by the resonance of the in-series inductance with the snubber capacitance. The equivalent circuit of the quarter-phase ultrasonic motor is initially deduced, based on which the topology along with the operations of the novel inverter is subsequently presented. The configuration of the new quarter-phase inverter shows its uniqueness in terms of the shared arms and the especially designed snubber capacitance in comparison with the existing inverters. The circuit analysis infers that the dead time of the inverter is the key factor to arrive at the zero-voltage-switching or the zero-current-switching operations. Experimental measurements have demonstrated that the efficiency of the whole drive increases by a factor of 1.25 after replacing the traditional inverter with the proposed one. It should also be noted that the proposed inverter in association with the design method of the dead time not only can work for the quarter-phase ultrasonic motor, but also can be applicable for other kinds of quarter-phase devices. The soft-switching operations are achieved in the quarter-phase inverter for the first time, whose amplitudes of the output voltage and switching frequency are not required to be constant any more. [ABSTRACT FROM AUTHOR]

Two parallel interleaved two-level (2L) three-phase voltage source inverters (VSIs) can be analyzed as a single three-level (3L) VSI. A generalized carrier-based method is proposed in this paper for implementing different 3L pulsewidth modulation (PWM) techniques using two parallel interleaved 2L VSIs. The proposed method modifies the given three-phase reference signals of 3L VSI for implementation of the PWM technique using two parallel interleaved 2L VSIs. The influence of nonidealities on the equivalent 3L PWM switching sequences is also discussed. To overcome the effect of nonidealities, a new modified discontinuous PWM technique (MDPWM1) is proposed. The analysis of different performance indices is carried out for different 3L PWM techniques, and the key advantages of different PWM techniques are identified. Simulation and experimental results are also presented. [ABSTRACT FROM AUTHOR]