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In order to achieve the purpose of extending the speed range and reducing power electronics devices for the permanent-magnet linear motor drive system, a half-centralized open-end winding (OEW) topology is studied for rail transit applications in this paper. In this topology, compared with the traditional OEW topology, the number of voltage-source-inverters (VSIs) can be reduced from four to three to drive two OEW movers and all these VSIs share a common dc bus voltage. In order to improve the steady-state performances, a four-vector phase model predictive voltage control (FV-PMPVC) is proposed in this paper. Due to the spatial distribution of phase voltage vector (PVV), an orthometric synthesis principle (OSP) is proposed to calculated the duration time for the vector synthesis, which reduces the computation burden and enhances the robustness. Comparing the existing control method, FV-PMPVC can get similar dynamic performances but better steady-state performances. Additionally, the half-centralized topology using FV-PMPVC can have same speed range while less VSIs are required. The effectiveness of FV-PMPVC is verified by experimental results. [ABSTRACT FROM AUTHOR]

In renewable energy micro-source applications, a wide range of voltage conversion of the step-up converter is an essential part to equalize the typical low voltage of micro-source with DC-bus voltage of Inverter or motor drives. In order to meet this purpose, an ultra-voltage gain step-up DC-DC converter is proposed in this paper. The proposed converter has made an arrangement of the regenerative-boost fed switched inductor and capacitor configurations. Thereby, due to such an organization of structure, the proposed converter can develop an extremely high voltage-gain even at lower duty ratios. In addition, it has the advantage of lower switching stress across all power semi-conductive diodes. Furthermore, this paper describes the steady-state analysis and comparative features of the converter with existing recent literature. Finally, to validate theoretical analysis and test the feasibility and suitability of the proposed ultra-gain converter, the experimental results were observed by a 500 W fabricated prototype. [ABSTRACT FROM AUTHOR]

This paper presents an optimization framework for sequential reconfiguration using an assortment of switching devices and repair process in distribution system restoration. Compared to existing studies, this paper considers types, capabilities and operational limits of different switching devices, making it applicable in practice. We develop a novel multi-phase method to find the optimal sequential operation of various switching devices and repair faulted areas. We consider circuit breakers, reclosers, sectionalizers, load breaker switches, and fuses. The switching operation problem is decomposed into two mixed-integer linear programming (MILP) subproblems. The first subproblem determines the optimal network topology and estimates the number of steps to reach that topology, while the second subproblem generates a sequence of switching operations to coordinate the switches. For repairing the faults, we design an MILP model that dispatches repair crews to clear faults and replace melted fuses. After clearing a fault, we update the topology of the network by generating a new sequence of switching operations, and the process continues until all faults are cleared. To improve the computational efficiency, a network reduction algorithm is developed to group line sections, such that only switchable sections are present in the reduced network. The proposed method is validated on the IEEE 123-bus and 8500-bus systems. [ABSTRACT FROM AUTHOR]

The dc-dc converters with high step-up DC-voltage gain play a vital role in integrating low voltage DC sources. Though several converter topologies are reported in the recent past, attempts have been made to reduce the components, especially the switching devices, passive elements, converter losses, etc., of the converter. A novel DC-DC converter topology, viz., single switched impedance network (SSIN)-based converter with n-stage is proposed in this paper. The operation of the SSIN based converter in continuous and discontinuous conduction modes are discussed. The effect of parasitic elements on DC-voltage gain and efficiency of the SSIN is carried out. The small-signal model of the SSIN converter is derived. The performance of the SSIN converter is compared with the similar converter topologies. The 500 W prototypes of the SSIN with n = 1 and n = 2 are fabricated, and the experimental results are presented in this paper. To improve the converter performance, SiC-based semiconductor devices are used. The SSIN converter with two-stage has low switch loss at 500 W load, improved efficiency during high power and high output voltage operation, the switch stress of Vo/2, etc. [ABSTRACT FROM AUTHOR]

The modular multilevel converter (MMC), owing to the presence of a large number of submodules (SMs) and energy storing elements, requires a large footprint and initial investment. To address these issues, this paper proposes the switched modular multilevel converter (SMMC). It consists of two major elements; the chain-links (CLs), consisting of cascade connection of SMs as in MMC, and the single-pole-triple-throw (SPTT) switches, which can be realized using either the T-type or NPC-type switch strings. The SMMC works on the principle of connecting all the phase-legs in series and their respective positions are mutually interchanged. It offers a compact structure as the SMs count is reduced to 33% of MMC, which results in a much lower energy storage requirement. Furthermore, it does not have inter-phase circulating current problem and hence the CL inductors can also be avoided. The SMMC structure, operating principles, control, and modulation schemes are explained in detail. A detailed comparison of SMMC with the other major existing converters is carried out to highlight the important features of SMMC. The efficacy of SMMC is validated using PSCAD simulation studies with a 19-level grid-connected SMMC model. A 3-phase 19-level SMMC laboratory prototype is developed to further validate its feasibility. [ABSTRACT FROM AUTHOR]

The safety of converters is key to the stable operation of AC/DC hybrid power grids after AC faults. Thyristor valve current is a direct manifestation of the converter observability, but there are no measuring elements inside the converter, so the thyristor valve current can be reflected only indirectly through external electrical quantities. This paper proposes a virtual measurement scheme based on the temporal features of the converter terminal current. First, under the action of the trigger pulse, the polarity characteristics of the AC current and temporal features between the valves are utilized to predictive estimate the valve state. Then, when commutation failures occur and the bypass paths form, the conduction state of valve is constructed based on the relationship between AC and DC current. Last, when the valve is to be shut-off in the bypass path, the blocking state of the valve is corrected based on the unidirectional conductance characteristics of the valve. According to the above analysis, combined with the topological current equation of the converter, the valve current can be calculated in the whole process. Through the simulation of the different valve states and bypass paths and analysis of the field record data, the results show that the valve current can still be accurately calculated based on the virtual measurement scheme. [ABSTRACT FROM AUTHOR]

In this paper, we address the finite-time and fixed-time synchronization of a general class of switched neural networks (SNNs) with time delays subject to stochastic disturbances. Considering two types of switching in this class of SNNs: 1) intra-SNN state-dependent switching and 2) inter-SNN Markovian switching, we develop three control laws and derive three sets of sufficient conditions for both finite-time and fixed-time synchronization of SNNs subject to stochastic disturbances. We make two remarks on the effects of control-law parameters on synchronization settling time. Moreover, we derive several upper bounds of synchronization settling time and evaluate their pros and cons. Finally, we elaborate on two numerical examples to illustrate the viability of the theoretical results. [ABSTRACT FROM AUTHOR]

This paper focuses on the issue of network connectedness (NC) in security-constrained optimal transmission switching problems, which is complicated by branch contingencies and corrective line switching. Two criteria are firstly proposed with the principle of preserving NC as much as possible within reasonable limits. By extending the electrical flow based NC constraints, a proposition is derived to associate different cases of NC with the optimum of a linear program, yielding the mathematical formulation of the NC criteria. By Karush-Kuhn-Tucker conditions, this formulation is further transformed into a tractable version which can be incorporated with existing SCOTS models without affecting the applicability of original solution approaches. Finally, case studies on various networks and SCOTS models demonstrate the efficacy of the proposed approach. [ABSTRACT FROM AUTHOR]

Differential power processing (DPP) converters have been developed for photovoltaic (PV) panels to preclude energy yield reduction due to partial shading. In large-scale PV systems comprising numerous series-connected panels, DPP converters with good modularity are preferable because the number of series-connected panels varies depending on applications. This paper proposes a switched capacitor converter (SCC)-based modular DPP architecture for large-scale PV systems. Four panels are grouped as a module, each having a panel-level DPP converter, and modules are connected in series to form a string. The design of the panel-level DPP converter is fixed while the system can be arbitrarily extended by stacking modules, achieving good modularity. Adjacent panel-level DPP converters are dc-coupled, by which modules can be connected using long cables, mitigating installation limitations. The experimental results of the laboratory and field testing demonstrated the energy yield enhancement by 10%–20%, depending on shading conditions. [ABSTRACT FROM AUTHOR]

The paper develops two computationally efficient models, namely a detailed equivalent model and an average-value model, with provisions for representation of the critical state of converter blocking, for modular multilevel converters with embedded storage. These models are indispensable in the simulation of dc faults. The developed detailed equivalent model provides accuracy that matches electromagnetic transient (EMT) simulations, with much reduced computational burden; the developed average-value model represents the averaged behavior of the converter by neglecting switching transients. Both models are extensively evaluated in the context of an HVDC system against benchmark results form a detailed switching model developed in PSCAD/EMTDC. The results confirm the validity and accuracy of the models for steady state, transient, and faulted operating conditions including when the converter is blocked in response to a dc fault. [ABSTRACT FROM AUTHOR]

This paper proposes a novel dual input nine-level inverter (DINLI) topology which requires only seven controllable devices. The dual inputs are un-identical DC voltage sources in the ratio 1:3. A simple control scheme is derived by appropriately modifying the phase disposition pulse width modulation technique to generate high-quality 9-level output from the DINLI topology. At any given instant, a maximum of four switches conduct out of which only a maximum of two switches operate at high frequency, bringing down the switching and conduction losses significantly and improving the overall system efficiency. The bidirectional DINLI (BDINLI) topology with reactive power capability can be realized by replacing the unidirectional devices with the controlled switches (i.e., total nine switches). In addition, the proposed DINLI topology does not require extra voltage balancing circuits which further improves the efficiency. The DINLI operation is verified through MATLAB simulations for grid-connected applications and its extension to an n-level, 3-phase application is also investigated. Experiments performed on a 1KVA laboratory prototype to validate the theoretical claims. [ABSTRACT FROM AUTHOR]

Most microgrid protection schemes found in published literature suffer from a lack of generality in that they work well for the assumed topology, including type and placement of sources. Other generic protection schemes tend to be too complicated, too expensive, or both. To overcome these drawbacks, a topology-agnostic, scalable, and cost-aware protection based on fundamental principles that work in the presence of high penetration of inverter-based resources (IBRs) is developed and tested in this paper. The protection system also implements stable automatic reconfiguration of the healthy sections of the system after clearance of fault, thus increasing resilience by self-healing. To achieve this ambitious goal, stable inverter models are developed that operate in unbalanced networks in grid-connected and islanded modes, even with 100% IBRs, share power without conflicting controls, and can ride through faults while limiting fault currents. The scheme is tested for primary and backup protection and reconfiguration on the IEEE 123-node feeder in grid-connected and islanded modes with 15 IBRs connected to the system. [ABSTRACT FROM AUTHOR]

Miniaturization and low cost contribute to the development and popularization of wireless power transfer (WPT). Reducing the number of power conversion stages can reduce the volume and cost of the WPT converter, and even make it possible to improve the efficiency. A single-stage WPT converter with constant current (CC) and constant voltage (CV) output and its asymmetric modulation method are proposed in this paper. A direct AC-AC converter is applied to the primary side of the WPT converter to directly convert line-frequency AC to high-frequency AC. The applied direct AC-AC converter that can replace the commonly used multi-stage primary converter reduces the number of circuit devices, thereby reducing the volume and cost of primary converter. The proposed WPT converter can realize zero voltage switching (ZVS) and power factor correction (PFC). In order to achieve CC and CV output, a switchable hybrid compensation topology is applied to the proposed WPT converter. A 720-W experimental prototype was manufactured to verify the rationality of the proposed WPT converter and the correctness of the theoretical analysis. [ABSTRACT FROM AUTHOR]

This paper proposes a novel data driven framework for detecting topology transitions in a distribution network. The framework analyzes data from phasor measurement units (PMUs) and relies on the fact that changes in network topology results in changes in the structure and admittance of the network. Using voltage and current phasors recorded by PMUs, the proposed method approximates network parameters using an ensemble-based deep learning model and thus, it does not require any knowledge of network parameters and load models. Using the prediction error of the proposed model, a connectivity matrix which shows the status of switches is constructed. In contrast to other methods, this proposed framework does not require a library of voltage and current transients associated with possible network transitions. It can also detect simultaneous switching actions and is robust to noise and load variations. The model yields a lower error detection rate, and its performance is validated using a modified version of the IEEE 33 bus network and a real feeder located in Queensland, Australia, under full and partial observability conditions. The proposed model has also been compared with another data driven method in terms of inference time and error detection rates. [ABSTRACT FROM AUTHOR]

The missing capability of DC fault current limitation is an inherent disadvantage in the typical half-bridge modular multilevel converter (MMC), which restricts its application in long-distance high voltage direct current (HVDC) systems. The full-bridge submodule (FBSM) and clamped double submodule (CDSM) topologies allow for fault current self-clearing, but also suffer from additional hardware cost and power losses. In this paper, an improved submodule topology utilizing the new reverse-blocking insulated gate bipolar transistor (RB-IGBT) is proposed to improve system economy without compromising its performance. The operating principles and DC fault characteristics of the proposed topology are analyzed in details, including comparison with various topologies in terms of cost, losses, fault current clearing speed and thermal. Compared with the traditional CDSM topology, the proposed RBSM can clear DC faults faster with reduced cost of switching devices. A DC fault protection strategy for MMC-HVDC system is also presented. Simulation results under normal operating, permanent and transient fault conditions are carried out to verify the effectiveness of the proposed topology. [ABSTRACT FROM AUTHOR]

The reliable operation of a power distribution system relies on a good prior knowledge of its topology and its system state. Although crucial, due to the lack of direct monitoring devices on the switch statuses, the topology information is often unavailable or outdated for the distribution system operators for real-time applications. Apart from the limited observability of the power distribution system, other challenges are the nonlinearity of the model, the complicated, unbalanced structure of the distribution system, and the scale of the system. To overcome the above challenges, this paper proposes a Bayesian-inference framework that allows us to simultaneously estimate the topology and the state of a three-phase, unbalanced power distribution system. Specifically, by using the very limited number of measurements available that are associated with the forecast load data, we efficiently recover the full Bayesian posterior distributions of the system topology under both normal and outage operation conditions. This is performed through an adaptive importance sampling procedure that greatly alleviates the computational burden of the traditional Monte-Carlo (MC)-sampling-based approach while maintaining a good estimation accuracy. The simulations conducted on the IEEE 123-bus test system and an unbalanced 1282-bus system reveal the excellent performances of the proposed method. [ABSTRACT FROM AUTHOR]

A multi-level boost topology based on a flying capacitor is compared in this work with the hybrid, multi-level, partial power processing topology already presented in the literature for use as a highly efficient and compact dc/dc stage in 1500-V, two-stage, grid-connected PV systems. Different variations of the resonant stage of the hybrid topology are analyzed and compared in terms of losses, volume and complexity. Full multivariable optimization is conducted for the multi-level boost topology with different number of levels and for all the analyzed variations of the resonant stage of the hybrid topology. Appropriately rated new classes of 650-V and 900-V WBG devices are included in the optimization algorithm. It is concluded that due to the dominant conduction losses and gap in the voltage rating of the commercially available WBG devices between 650V and 200V, increase of the number of levels over 4 leads to the deteriorated loss and volume performances. All the analysis related to the resonant stage of the hybrid topology is confirmed by detailed and comprehensive measurements of two prototypes of 4kW of nominal and 7kW of maximal power. Additionally, all the loss models applied in the optimization algorithms presented in this paper are confirmed by detailed measurements, thermal calibration and finite element thermal simulations of the wide bandgap devices and inductor designs employed in this work. [ABSTRACT FROM AUTHOR]

Data center networks typically adopt multi-rooted tree topologies to provide high bisection bandwidth. Various fine-grained load balancing schemes have been proposed to split flows across multiple paths. However, data center networks suffer from many uncertainties such as highly dynamic traffic. These uncertainties easily make network become asymmetric, resulting in significant packet reordering. Unfortunately, existing solutions passively deal with packet reordering based on a threshold and hardly adapt to asymmetric networks because of lacking the explicit reordering feedback. These solutions either fail to quickly respond to packet loss or cause unnecessary fast retransmission, which reduces link utilization and increases flow completion time. In this paper, we propose a fine-grained load balancing scheme RMC to eliminate the impact of packet reordering and handle uncertainties in asymmetric networks. To avoid unnecessary fast retransmission, the switch proactively identifies reordered packet according to local queue length and global path latency. Furthermore, we employ a coding technique with redundancy optimization to reduce long-tailed flow completion time under network asymmetry. Through a series of large-scale NS2 simulations and testbed experiments, we demonstrate that RMC effectively avoids unnecessary fast retransmission under different network scenarios and reduces flow completion time by up to 72% compared with state-of-the-art schemes. [ABSTRACT FROM AUTHOR]

This paper presents an isolated single-stage on-board electric vehicle charger without an intermediate DC-link. Based on an isolated current-source topology, the converter features soft-switching in semiconductors regardless of load variation for the full AC line voltage range. Moreover, it requires no external snubber or clamp circuits. The power factor correction and voltage regulation are provided by a relatively simple phase shift modulation, while the amount of circulating energy is kept at minimum. The charger is distinguished by its efficiency characteristic – the maximum is achieved in the constant power charging mode. The control method, component stresses, and design constraints of the topology are analyzed. The concept is verified using a 3 kW experimental SiC-based prototype, which reaches a peak efficiency of 96.4%. Moreover, the charger has demonstrated efficiencies above 95% with the THD of 4.1% when operating in constant power mode at the maximal power. [ABSTRACT FROM AUTHOR]

This paper presents a new single-source three-phase seven-level inverter with an inherent three-time voltage boosting capability for medium-voltage applications. The proposed topology is comprised of series connection of two switched-capacitor (SC) networks with an added half-bridge module per phase. Each of such integrated SC networks requires a single capacitor associated with three active power switches. The three-time voltage boosting feature of the proposed topology can reduce the dc-link voltage requirements by 50% in comparison to the traditional neutral point clamped (NPC), flying capacitors, active NPC (ANPC), hybrid clamped ANPC, and cascaded H-bridge topologies, and 75% to advanced ANPC topologies. It can also reduce the number of required switches and capacitors as well as their voltage stresses compared to those state-of-the-art topologies reported in the literature. By integrating “n” number of added SC networks in the proposed seven-level basic topology, the number of output voltage levels can be extended to 2n+3 per phase. A finite control set model predictive control algorithm is also derived to control the converter in both the active and reactive power exchanges modes without distorting the generated grid current quality. The capacitor voltage balancing is inherent in the proposed topology, and thus, there is no need for any additional voltage balancing circuit, which further reduces the control complexity. The performance of the proposed topology and its control algorithm are validated by several measurement results. [ABSTRACT FROM AUTHOR]

This paper introduces a network topology identification (TI) method based on deep neural networks (DNNs) for online applications. The proposed TI DNN utilizes the set of measurements used for state estimation to predict the actual network topology and offers low computational times along with high accuracy under a wide variety of testing scenarios. The training process of the TI DNN is duly discussed, and several deep learning heuristics that may be useful for similar implementations are provided. Simulations on the IEEE 14-bus and IEEE 39-bus test systems are reported to demonstrate the effectiveness and the small computational cost of the proposed methodology. [ABSTRACT FROM AUTHOR]

In this paper, we propose a topology-cognizant optimal power flow (OPF) paradigm with additional safety constraints for multi-terminal direct current (MTDC) grids. The resulting formulation is concerned with the optimization of controller set-points, i.e., voltage and power levels at each bus, and the switching status of transmission lines that collectively referred to as grid topology. A pair of additional safety constraints are integrated into the problem formulation to prevent voltage violations caused by power fluctuations in between two controller set-point updates. Searching for a grid topology that offers more efficient operation leads to a mixed-integer nonlinear program (MINLP) which is computationally challenging due to: i) Non-convex power flow equations, (ii) Non-convex converter loss equations, and iii) Binary variables accounting for the operational status of transmission lines. Non-convexities of power flows and converter loss equations are tackled by means of a mixed-integer second-order cone programming (MISOCP) relaxation, while the optimal switching status of transmission lines are determined via a branch-and-bound search. Numerical results for the modified IEEE 14, 30, and 57-bus systems are used to verify the merits of the proposed method. Furthermore, this method is experimentally validated using the CIGRE B4 DC grid benchmark in a real-time hardware-in-the-loop platform. [ABSTRACT FROM AUTHOR]

Conventionally, the converter of switched reluctance motor (SRM) is fed by the uncontrollable diode bridge rectifier (DBR), which leads to a low grid-side power factor (PF) and high current total harmonic distortion (THD). In this paper, an alternative solution for the grid-connected high-speed SRM drive system with improved PF is proposed. In the proposed drive system, the three-level active front end (AFE) is connected in cascade with the midpoint converter for SRM operation. A centralized strategy, which controls the AFE and SRM together, is proposed to govern the motor speed and grid-side PF by regulating the real power and reactive power of the system, respectively. Specifically, the real power, reactive power, and the voltage balancing of split capacitors are controlled by the model predictive directed power control (MP-DPC) algorithm, which significantly reduces the control complexity and guarantees the fast dynamic response. Consequently, satisfying speed regulation, high PF, low current THD, and bi-directional power-transfer capability are achieved. An idea-proofed testbench is constructed in laboratory, and the applicability of the proposed drive system is verified by a series of experimental results. [ABSTRACT FROM AUTHOR]

Network topology identification (TI) is an essential function for distributed energy resources management systems (DERMS) to organize and operate widespread distributed energy resources (DERs). In this paper, discriminant analysis (DA) is deployed to develop a network TI function that relies only on the measurements available to DERMS. The propounded method is able to identify the network switching configuration, as well as the status of protective devices. Following, to improve the TI resiliency against the interruption of communication channels, a quadratic programming optimization approach is proposed to recover the missing signals. By deploying the propounded data recovery approach and Bayes’ theorem together, a benchmark is developed afterward to identify anomalous measurements. This benchmark can make the TI function resilient against cyber-attacks. Having a low computational burden, this approach is fast-track and can be applied in real-time applications. Sensitivity analysis is performed to assess the contribution of different measurements and the impact of the system load type and loading level on the performance of the proposed approach. [ABSTRACT FROM AUTHOR]

Isolated, zero-voltage-switching dc–dc converter topologies represent attractive solutions in the continuous run toward higher switching frequencies, allowing more compact power supplies. Among them, the asymmetrical half-bridge flyback converter represents an interesting option, featuring simple duty-cycle control at constant switching frequency, as opposed to the popular LLC converter. The majority of papers dealing with this topology consider an approximated voltage gain similar to that of an isolated buck converter operating in continuous conduction mode, i.e., proportional to the duty cycle and, practically, load independent. On the contrary, the true voltage gain is nonmonotonic at high duty-cycle values. Anytime the converter is designed for a resonant operation, as is advisable to eliminate any reverse recovery problem of the rectifier diode, the voltage gain not only increases, but also becomes a function of the switching frequency. This article investigates the converter's voltage gain in detail, deriving a theoretical framework capable of capturing its real behavior and dependencies. The proposed analytical model has been verified through simulations as well as experimental measurements taken on a 160-W prototype working at 400 kHz. [ABSTRACT FROM AUTHOR]