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Common-mode voltage output is closely associated with switching states in three-phase three-wire neutral point clamped converter. Detailed analysis shows avoiding redundant states can effectively improve the common-mode voltage, so this paper proposes a pulse width modulation (PWM) technique with zero redundant state to reduce the common-mode voltage output, and evaluates their performance with the conventional PWM schemes. This paper also takes the compensation of neutral point potential deviation into consideration. Laboratory test results are presented to verify the effectiveness of the proposed scheme. [ABSTRACT FROM PUBLISHER]

This paper proposes an active switching harmonic current reduction method within the dc-link capacitor of two-level, three-phase, back-to-back converters. This method is based on the derived analytical solution for switching harmonic currents in the dc-link. It is shown that by controlling the pulse width modulation carrier waveform's phase angles, the harmonics in the second carrier band of the rectifier and the inverter can be synchronized such that cancellation occurs in the dc-link capacitor. This synchronization is provided by harmonic phase feedback control. The feasibility of the proposed approach has been verified experimentally and results are presented in this paper. [ABSTRACT FROM PUBLISHER]

The modeling and control of a buck–boost and stacked dual half-bridge (DHB) integrated bidirectional dc–dc converter have been studied in this paper. This converter features high-voltage transfer ratio, high efficiency, and the minimum number of switches. In this paper, an extended, continuous, full-order, state-space averaging modeling method is proposed. Compared with existing methods, the proposed method exhibits higher coincidence with the switching circuit simulation, in steady and especially dynamic states. Due to its high dynamic accuracy and low complexity, the proposed modeling method provides a better theoretical analysis and a fast simulation tool for transient process and control design of converters with dual-active-bridge units, especially with DHB units. By using this method, the high-frequency transformer series inductance current is directly divided into a sampled dc component and a fluctuant component. Only the sampled dc one is included into state variables, but both components are considered into state equations. Besides, this method regards the entire converter as a linear superposition of its subsections, which provides a stepwise modeling based on linearization of subsections. Moreover, a decoupled proportional-integral control method is proposed to enhance the stability and dynamic response of the converter. This control method is analyzed by the proposed models, which can be regarded as an application of the proposed modeling method. Simulation and experiments have validated both the proposed modeling and the decoupled control strategy. [ABSTRACT FROM PUBLISHER]

Digital current controllers have the key impact on the performance of grid-side converters and ac drives. The voltage disturbances are commonly suppressed by enhancing the controller with an inner active resistance feedback. In cases where the switching noise and parasitic oscillations introduce sampling errors, conventional sampling is replaced by the oversampling-based error-free feedback acquisition which derives the average of the measured currents over the past switching period. The time delay introduced into the feedback path creates difficulties in designing the current controller with the active resistance. In this paper, we introduce a novel structure of the current controller, which includes the error-free sampling and the active resistance feedback. Devised structure improves the disturbance rejection by extending the range of permissible values of the active resistance. Controller structure is based on the internal model principles, and it maintains the input step response unaffected. This paper comprises analytical design, the gain setting procedure, computer simulation, and experimental results obtained from an experimental setup with a three-phase inverter, digital controller, and a permanent-magnet synchronous motor. [ABSTRACT FROM PUBLISHER]

A novel hybrid pulse width modulation (PWM) technique is proposed in this paper for two parallel interleaved, two-level, three-phase voltage source inverters (VSIs). The two parallel interleaved VSIs are analyzed as a three-level (3L) inverter. A 3L inverter provides minimum line current ripple when nearest three voltage vectors are applied. In this paper, a novel carrier-based PWM technique is developed that ensures the application of nearest voltage vectors, keeping average circulating current to zero over a switching period. For carrier-based implementation of the proposed PWM, generalized common-mode (CM) offsets are derived in terms of maximum and minimum values of reference signals. Each 3L space-vector sector is divided into seven subsectors. For each subsector, a CM offset is calculated, addition of which to reference signals ensures the minimum line current ripple and zero average circulating current. Simulation and experimental results are provided to validate the proposed technique. [ABSTRACT FROM PUBLISHER]

The aim of this paper is to study the dynamics of a permanent magnet direct current (PMDC) brushed motor while two crucial space-domain effects, namely, slotting effect and commutation phenomenon are taken into account. Semi-analytical dynamic time-domain PMDC brushed motor model inclusive of these space-domain effects is used to analyze and investigate the dynamics. Pulse width modulation operated discontinuous current PMDC brushed motor drive with steady duty cycle is employed to acquire the bifurcation patterns. The chaotic nature due to slotting effect and commutation is identified from the bifurcation patterns and reported. It also has to be admired that such nonlinear dynamical behavior with the same set of parameters at similar operating condition has not been observed when a conventional PMDC brushed motor dynamic model is considered. These space-domain effects, namely, slotting effect and commutation also have a prominent impact to make some time-domain states of a PMDC brushed motor drive chaotic. The role of slotting effect and commutation phenomenon to analyze the chaos over time-domain state variables of the PMDC brushed motor drive is investigated and validated experimentally in this paper. [ABSTRACT FROM PUBLISHER]

Dual active bridge (DAB) converter is the most suitable converter to transfer high power with bidirectional power flow capability and isolation. However, it has the drawbacks of circulation power flow (CPF) and limited range of zero voltage switching (ZVS). To overcome these drawbacks, several modulation strategies have been proposed; however, the CPF can be eliminated either at input or output voltage ends. In order to eliminate the CPF at both input and output sides, a novel front and rear end switch DAB (FRS-DAB) bidirectional dc–dc converter has been proposed in this paper. It has the advantages of lower current stress, extension of ZVS range, higher power transfer capacity, and improved efficiency compared to the conventional DAB converter. The paper presents the detailed operating modes and analysis of power flow control for the proposed FRS-DAB converter. The operation and analytical results of the proposed converter have been verified through the experimental results using an FPGA Spartan 3AN processor. [ABSTRACT FROM PUBLISHER]

The modular multilevel converter (MMC) with nearest level modulation (NLM) is widely used in the high voltage applications for low switching frequency and easy implementation. Existing literature has not provided a complete submodule (SM) fault ride-through scheme for MMC with NLM. In this paper, a strategy including fault detection, localization, redundancy, and recovery is proposed to ensure continuous operation of MMC under IGBT open-circuit faults conditions. It only requires a few hardware and software resources. The features of MMC and SMs with three types of failures are studied, respectively. Based on these, the fault detection method is proposed by using a simple hardware circuit, thus high computation complexity is avoided. Since current fault localization schemes are limited to MMC with carrier phase shifted pulse width modulation, this paper further proposes a strategy for MMC with NLM to locate the faulty SM and identify the fault type. After this, the fault redundancy and the proposed fault recovery method are applied to eliminate the fault and then exit the failure state. Therefore, the ability of SM fault ride-through can be realized. Analysis of failure characteristics are verified in simulation. Experimental results based on a single-phase MMC prototype with 11 SMs per arm are presented to demonstrate the validity of the proposed fault ride-through strategy. [ABSTRACT FROM AUTHOR]

This paper presents a novel single source fed isolated gate driver circuit based on the dual-forward converter topology. The two forward converters are paralleled at the secondary side to achieve 0%–100 $\%$ duty cycle range together with galvanic isolation. The gate driver switching frequency is independent of the main pulse-width modulation frequency (PWM). As a result, the gate driver switching devices and magnetics are designed for high frequencies independent of the main PWM frequency. At high frequencies, problems of resonance due to parasitics become significant. This paper discusses this problem and proposes a novel solution to mitigate it. In addition, this paper also presents a novel solution and circuit to produce negative gate pulse for miller clamp. The proposed circuit can be used for any application, irrespective of switching frequency, thus making it a wide band generalized gate driver. The circuit is analyzed and verified experimentally. [ABSTRACT FROM PUBLISHER]

This paper presents a new feed-forward strategy for suppressing low-order harmonic circulating currents in pulsewidth-modulated (PWM) based modular multilevel converters (MMCs). The approach is based on the new average model approach established in this paper, which identifies cross-coupling interactions between the system-level and submodule elements using decomposed dependent sources. As well as improving the damping of the system, the major advantage of this approach is that it maintains the natural DC bus balance property of a PWM modulated MMC by considering the upper and lower arms together (unlike existing feed-forward schemes which treat each MMC arm independently). Moreover, unlike existing direct control resonant strategies, which require careful gain tuning and are highly dependent on the ac system frequency, the proposed approach achieves wideband circulating current ripple suppression without requiring knowledge of the circulating current harmonic frequencies and needs only a simple proportional–integral (PI) controller to regulate the circulating current dc component for power balance. This makes it particularly suitable for use in multifrequency or variable-frequency ac systems. Extensive simulation and matching experimental results, including steady-state and transient responses compared against existing circulating current suppression approaches, validate the effectiveness and benefits of this new feed-forward compensation technique. [ABSTRACT FROM PUBLISHER]

The performance of modular multilevel converters (MMCs) in medium-voltage applications, where the number of required submodules is not high, can be improved utilizing low switching frequency modulations such as (2N+1) selective harmonic elimination-pulse width modulation (SHE-PWM), which provides tight control of lower order harmonics and low switching losses. This paper proposes a calculation method, which is based on a novel formulation, to solve the SHE-PWM problem. In particular, MMCs with (2N+1) phase output voltage levels are considered, obtaining a (2N+1) SHE-PWM waveform. This method utilizes a unique system of equations that is valid for any possible waveform. Therefore, it is able to calculate simultaneously, without predefined waveforms, both the switching patterns and the associated firing angles that solve the (2N+1) SHE-PWM problem. Consequently, the search process is simplified and optimized. Furthermore, this paper also proposes a circulating current control technique, which can be applied along with (2N+1) SHE-PWM without disturbing the phase output voltage. Simulation results and experimental tests obtained with a single-phase laboratory prototype prove the validity of the novel (2N+1) SHE-PWM implementation method and the proposed circulating current control technique. [ABSTRACT FROM PUBLISHER]

This paper presents a hybrid seven-level converter based on T-type converter and H-bridge cascaded suitable for low-voltage and high-power-density applications. The operation principles and conduction paths are analyzed comprehensively. Voltage balance control of the floating capacitors is the key point of this paper. Mathematical expressions of capacitor voltage balance conditions are deduced based on sinusoidal pulse width modulation (SPWM). The results show that floating capacitor voltages are only balanced when the modulation index is below 0.82 under SPWM. In order to enlarge the modulation index ensuring the capacitor voltage balance, space vector modulation (SVM) is also applied to regulate floating capacitor voltages taking advantage of redundant switching vectors. Meanwhile, in SVM, there are no additional control requirements for the capacitor voltage. Taken both SPWM and SVM into consideration, the limit to the range of operation for this seven-level converter is presented, which is a function of the modulation index and the power factor. The merit of dc voltage utilization improvement in this topology is also analyzed based on simulation results. Simulations and experimental results under different modulation index and RL load are presented to verify the modulation strategies illustrated in this paper. [ABSTRACT FROM PUBLISHER]

This paper targets the reduction of common-mode voltage in an indirect matrix converter (IMC) through an intelligent space-vector-based modulation technique. This mode of control results in lower dV/dt at the motor terminals, thereby, reducing voltage stress to windings; and reduced output voltage distortion resulting in lower machine losses. The conventional indirect space vector pulse-width modulation method of controlling matrix converters involves independent control of either the rectifying stage or the inverting stage of the converter. However, in this paper, by suitable selection of space vectors, the rectifying stage of the matrix converter generates different levels of virtual dc-link voltage. Therefore, the responsibility of formulating output voltages with a particular magnitude and frequency, which can be translated to different machine speeds, has been transferred solely to the rectifying stage of the IMC. Estimation of the degree of distortion in the three-phase output voltage is another facet discussed in this paper, which aids the sizing and designing of output passive filters. The analysis of output voltage distortion and the proposed modulation strategies have been substantiated by simulations in MATLAB/Simulink and experimentally verified on a scaled down laboratory prototype. [ABSTRACT FROM AUTHOR]

The selective harmonic current mitigation pulsewidth modulation (SHCM-PWM) technique can be used in cascaded multilevel converters to extend the harmonic reduction spectrum, reduce the coupling inductance and increase the efficiency. The offline SHCM-PWM technique has small number of switching transitions as its switching angles can only change once in a fundamental cycle and relatively long time delays because it uses FFT. As a result, its dynamic response has a lot to desire. As it will be proven in this paper, in four-quadrant power converters, to have a good transient dynamic response, both active and reactive power must be controlled at least two times in a fundamental cycle. In this paper, a hybrid modulation technique is introduced. The proposed technique uses SHCM-PWM under steady state and phase-shift PWM (PSPWM) under transient. In addition, in order to extend the modulation index range and ensure that SHCM-PWM can process four-quadrant active and reactive power, the constraints of the switching angles for the SHCM-PWM are modified. Simulations and experiments are conducted on a seven-level cascaded H-bridge converter to verify the proposed technique. [ABSTRACT FROM PUBLISHER]

Wide bandgap semiconductor switches have been increasingly utilized to improve the power density and efficiency of power converters, as such devices are able to operate at very high frequencies, e.g., up to 100 MHz, with reduced power losses. However, such a high-frequency operation may impose a challenge to the digital control system, and the system clock frequency should be up to 100 GHz in high-precision applications, which is difficult to realize in low-cost microprocessors. Instead of using extremely high-frequency clocks, preprocessing-based solutions that utilize digital pulse-width-modulated (DPWM) dither techniques can also enhance the DPWM resolution with moderate frequency clocks. Unfortunately, this is usually achieved at the expense of introducing low-frequency harmonics, which may complicate system controller and output filter design. In this paper, an optimal dither technique is proposed to enhance the resolution of DPWM power converters. The concepts of positive dither and negative dither are first proposed in this paper. Furthermore, vector-diagram-based analysis indicates that with proper utilization of positive dithers and negative dithers and carefully selected dither sequences, the lowest order harmonic introduced by the conventional dither technique can be completely eliminated when the dither period is multiples of six switching periods. In other cases, the proposed optimal dither technique can produce minimized lowest order harmonic. Finally, experimental results obtained from a Gallium Nitride (GaN) devices-based synchronous buck converter validate the feasibility of the proposed dither technique. [ABSTRACT FROM PUBLISHER]

This paper introduces a novel five-level nested neutral point piloted (NNPP) converter and analyzes the operating principle of five-level NNPP converter. This paper presents a novel space vector pulse width modulation (SVPWM) algorithm based on gh coordinate for five-level NNPP converter. First, the common-mode voltage is reduced by choosing the appropriate redundant switching states. After that, the floating-capacitor voltage balance control strategy is presented. The appropriate switch combinations of each phase are determined by the control requirements of floating-capacitor voltages respectively and the hardware mapping method of the switching states is presented. Furthermore, the neutral-point voltage balance control strategy is presented. In order to balance the dc-link capacitor voltages, the seven-segment switching sequence is selected according to the control requirements of dc-link capacitor voltages and the neutral-point voltage regulatory factor is introduced to regulate the durations of the redundant switching states in a switching cycle. Finally, the validity of the novel SVPWM algorithm with decoupling control strategies of floating-capacitor voltages and dc-link capacitor voltages is verified by the experimental results of five-level NNPP converter under steady-state and dynamic conditions. [ABSTRACT FROM AUTHOR]

This paper analyzes three different carrier-based modulation patterns applied to a three-phase high-power-factor-corrected (PFC) five-level buck+boost-type converter acting as an interface between dc distribution systems and an ac grid. The modulation is analyzed employing the space vectors theory so that the achievable performance is demonstrated. The main advantage of the analyzed modulation strategy is its simplicity, which makes it suitable for digital signal controller (DSC) implementations. This seems straightforward for voltage source converters, but is a challenge for current-multilevel converters that typically employ field-programmable gate array devices to achieve better harmonic distortion performance. This is due to modern power electronics DSCs being typically designed for other converter topologies. The power converter is constructed with two phase-shift-modulated six-switch buck-type PFC converters, paralleled by interphase transformers, and an inverting circuit. The system features: bidirectional current carrying capability; relatively low parts count; high utilization of the semiconductors; and low current and voltage ripple at its terminals. The principle of operation, detailed description, analysis of the modulation strategy, and dimensioning equations for three different power circuit realizations are described in this paper assuming the analyzed modulation patterns. The feasibility of the presented converter is demonstrated by means of a constructed hardware prototype. [ABSTRACT FROM AUTHOR]

In the topology of double-inverter fed wound rotor induction machine (DI-WRIM) two voltage source inverters (VSIs) are connected one each on stator and rotor terminals. This leads to ripple in both stator and rotor currents. In this paper, these current ripples are analyzed in terms of the stator- and rotor-flux ripples, which are estimated from their respective terminals. To reduce the current ripples, the VSIs of the stator and rotor terminals are modulated with different pulsewidth modulation (PWM) sequences. The switching loss in the DI-WRIM is also analyzed for the proposed stator–rotor PWM sequence combinations, based on the flexibility of changing the power factor, by changing the flux component of the current fed from either side of a DI-WRIM drive. The proposed PWM combinations with the proposed flux component in currents are found to reduce the stator and rotor current ripples and, the switching losses. The analytically estimated root mean square current ripples for the proposed PWM combinations are validated using the simulation and the experimental results obtained from a 3-kW DI-WRIM drive. The analysis on switching losses is validated by measuring the temperature rise of heat sinks present in the individual stator and rotor side VSIs of the DI-WRIM drive. [ABSTRACT FROM AUTHOR]

This paper proposes the use of advanced bus clamping switching sequences to reduce the impedance network inductor current ripple of the three-phase Z-source inverter (ZSI). Proposed technique is named as ABC4_MCB. MCB denotes that the maximum constant boost control method is used for the voltage boosting. One of the conventional space vector pulsewidth modulation of ZSI, “ZSVM6,” is termed as ZSVM6_MCB under the maximum constant boost control method. The switching sequences of ABC4_MCB technique are designed in such a way that it offers around 34% reduction in the maximum instantaneous inductor current ripple as compared to the ZSVM6_MCB for the equal average switching frequency. The factor of percentage reduction in the inductor current ripple using the proposed technique is constant over the entire range of shoot through duty ratio (0–0.48). Theoretical findings have been verified using simulation and experimental results. [ABSTRACT FROM AUTHOR]

This paper proposes a new multilevel inverter (MLI) topology that utilizes trinary sequence for the dc sources. It gives maximum output voltage level with minimum dc source and switch count when compared to other sequences, such as symmetric, natural, binary, and quasi-linear. This is due to the fact that the trinary sequence generates of all additive and subtractive combinations of input dc levels in the output voltage waveform. The concept is implemented on a 9-level asymmetric MLI using only four active devices. Multicarrier unipolar pulsewidth modulation technique is adopted to create the switching pulses. Theoretical calculation of total harmonic distortion in both voltage and current waveforms has been performed using asymptotic time domain formula. These values are compared with simulation and experimental values for different modulation indices. Power loss calculation for proposed topology is discussed with appropriate mathematical equations. [ABSTRACT FROM AUTHOR]

This paper presents a novel fault-tolerant method for active–neutral-point-clamped (ANPC) inverter using a modified carrier-based pulsewidth modulation. At a fault event, the ANPC inverter is divided into subinverters, and the modulating signal is modified to two modulating signals. The modified modulating signals are used to control the subinverters and allow continuous operation of the three-level ANPC inverter during faulty conditions even up to four open-switch faults per phase. This technique provides the fault-tolerant capability of the ANPC inverter without the need to add any additional phase legs or complex control strategies. Furthermore, the proposed technique ensures the voltage balancing of the dc-link capacitors. The performance of the proposed fault-tolerant technique is verified through simulation studies in MATLAB/Simulink under different faulty conditions. The feasibility of the proposed technique is also verified experimentally. [ABSTRACT FROM AUTHOR]

The aim of this paper is to propose a novel switching control method to improve the efficiency of the basic half-bridge converter for the whole range of the load current. Using multimode control for this purpose, instead of modifying the structure of the converter, is proposed for the first time. Efficiency improvement is achieved by using a digital controller to select and change the control mode to the most efficient one, for each of the load sub-ranges. Control modes are prominent ones, including asymmetric, duty phase shift, pulsewidth modulation, and burst control, and are selected in turn, while the load current varies in its entire range from the full down to the no-load. The three transition points between control modes, being specific values of the load current, are analytically determined based on comparing the half-bridge converter power losses for different control modes. The digital controller compares the load current with the transition points and puts the converter in the control mode with the highest efficiency. The accuracy of the analytically determined transition points and the efficiency improvement of the proposed control method over the previous ones are investigated and approved by the experimental results. [ABSTRACT FROM AUTHOR]

This paper presents a new single-phase ac–dc–ac three-level three-leg converter composed of three coupled-inductors and six active switches. The system model, operation principles, and a control strategy are presented and discussed. Additionally, a space-vector pulsewidth modulation technique is developed to double the effective frequency of the grid and load voltages and to reduce the switching losses. The proposed converter is compared to other similar converters in terms of switch count, harmonic distortion, and power losses. The results show that the proposed topology has improved power quality and uses fewer switches and gate drive circuits. These characteristics can potentially reduce the costs and the complexity of the system. In addition, the proposed converter eliminates the requirement for dead time to prevent short circuit of the dc-link. In order to validate the theoretical analysis, simulated and experimental results are presented and discussed. [ABSTRACT FROM AUTHOR]

Battery energy storage system based on the modular multilevel converter (MMC-BESS) is able to realize the decentralized management of battery packs, which is suitable for the retired battery utilization to improve the efficiency of battery recycling. With multiple submodules (SM), the corresponding SM fault ride-through method is mandatory to improve operational reliability. This paper proposes a redistributed pulsewidth modulation method for MMC-BESS to ride-through the SM fault through employing the simple logic operation, which could avoid the unexpected carrier shift under various modulation indexes induced by the SM fault or grid voltage rise. MATLAB simulations and experimental results are presented to verify the performance of the proposed method. [ABSTRACT FROM AUTHOR]

In this paper, an LLC type converter with two interleaved pulsewidth modulation (PWM) rectifiers is proposed. Compared with the conventional LLC converter, it achieves a wide voltage regulation range independent of load. In the proposed structure, each secondary-side PWM rectifier can operate individually. With the interleaving technique and shared primary-side switching network, the circuit secondary-side current stress is halved and the primary-side current stress is largely reduced. Besides, the filter capacitor requirement is reduced. Therefore, the proposed structure is a good option for medium/high power wide output range applications. The symmetrical LLC resonant tanks always operate at the resonant frequency, which marks the optimal operation point of the LLC resonant tank. Therefore, the conduction loss is effectively mitigated. In the proposed converter, zero-voltage turning-on (ZVS) of the primary-side MOSFETs can be ensured and is independent of the load. Moreover, the turning-off currents of the primary-side MOSFETs are small and are also load independent. This brings the benefits of minimized circulating current and negligible turning-off loss and no MOSFET turning-off voltage spike. The secondary-side auxiliary MOSFETs turn-on with ZVS and rectifying diodes turn-off with limited di/dt. Topological analysis and experimental results of a 1.3 kW/100 kHz prototype generating 230–440 V output from 390-V input are presented. The prototype demonstrates 97.31% peak efficiency and good performance over a wide output range. [ABSTRACT FROM AUTHOR]

Wide bandgap semiconductors with fast switching speed capability are becoming an enabler to achieve the higher power density design. However, the further increase of switching frequency cannot continuously improve the power quality of ac-side waveforms in dc–ac/ac–dc application. The main reason is the distortion of pulsewidth modulation (PWM) voltage at switching point under high switching frequency. In general, there are two contributors causing PWM voltage distortions in bridge-based topologies. One is the deadtime, which occupies higher ratio in the small duty cycle case under high switching frequency and induces the voltage errors. The other one is the turn-off transient in the small load current or around the zero-crossing point of the ac-side current, because the relatively slow rising slope of the drain–source voltage will affect the right duty cycle. To solve this issue, this paper proposes a closed-loop modulation scheme to compensate the duty cycle distortion of PWM voltage based on one-cycle control or charge control. Compared to the traditional feedforward type of compensation, the proposed scheme does not need online calculation and instantaneous inductor current sampling, and it shows potential to be a general scheme for variety of topologies and modulations. Simulations and experiments are carried out on a 400-kHz single-phase full-bridge inverter with 400-Hz fundamental frequency to demonstrate the performance of the proposed approach. [ABSTRACT FROM AUTHOR]

To achieve high frequency and high efficiency over a wide load range, a monolithic voltage-mode dc–dc buck converter with advanced burst mode (ABM) and pulsewidth modulation (PWM) is presented in this paper. The load current is detected by estimating the currents flowing through the high-side and low-side switches, which maintains a near constant mode changing point. A counter-based scheme is used to achieve seamless and smooth transition between PWM and ABM. Both operating modes share the same control blocks, and no additional zero current detecting circuit is needed. In addition, the output stage switch size can be adjusted to reduce switching loss and improve efficiency under ultra-light load conditions. Experimental results show that the integrated 3 MHz converter achieves high efficiency from 80 to 91%, over a wide load range from 0.001 to 5 A. When the switch size is set to 1/3 of the maximum value, an additional 5% efficiency improvement at under 0.1 A load can be realized. The mode changing point is set at 0.4 A with less than 10% variation when the input voltage changes from 3 to 5 V. The load transient response is also improved significantly. [ABSTRACT FROM AUTHOR]

This paper presents an investigation on finite control set model predictive current control, validated experimentally with a rear axle electrical drive unit used in automotive applications. An improved problem formulation is suggested which lowers the computational turnaround time of the solver with approximately $\text{40}\%$ for an horizon length of $N=4$. Apart from the computational requirement aspects, the assessment focuses on inverter efficiency, phase current total demand distortion, and acoustic performance. The proposed solution is evaluated against a standard double proportional and integrator (PI) field-oriented current controller with pulsewidth modulation. It is shown that the proposed solution is feasible, the associated optimization problem at hand can be solved in real time, while exploiting the attractiveness of the proposed improvements. In summary, it is concluded that the inverter efficiency can be improved without deteriorating neither the phase current harmonics nor the acoustic performance. [ABSTRACT FROM AUTHOR]

In photovoltaic applications, many previous research works have focused on pulsewidth modulation (PWM) resonant converters in order to achieve a high efficiency with a wide input voltage range. Conventional approaches utilized symmetric boosting modulation at the secondary side rectifier to obtain a symmetric operation, and they utilized two boosting modes in a switching period. Among various rectifier structures, the voltage doubler structure has a strong advantage due to a small number of components. However, it suffers from serious hard switching losses in the secondary side rectifier. In this paper, a new converter with a novel asymmetrical modulation is proposed and verified. The strong point of the proposed converter is that it eliminates hard switching turn-on losses from the rectifier, while maintaining the minimized number of components. Although the proposed converter adopts an asymmetric modulation, the offset current on the transformer becomes zero inherently. Furthermore, a “forced half resonance” operation of the proposed converter keeps rms current stresses at the same level as conventional converter although it has a higher peak current. Accordingly, the proposed converter achieves a superior efficiency with the minimum number of components at 35–25 V input and 380 V/300 W output specification. [ABSTRACT FROM AUTHOR]

Three-phase current reconstruction techniques with a single current sensor have been studied for permanent magnet synchronous machines (PMSMs) drive system due to its reducing cost and volume. In order to minimize the current reconstruction dead zone in the conventional method with a single dc-link current sensor, a strategy to couple multiple available positions through the single current sensor is proposed in this paper. With the proposed method, two independent equations of the stator currents can be obtained by sampling the single current sensor twice in both zero voltage vectors and active voltage vectors. By solving these two equations, the phase current reconstruction can be achieved accurately, which moves the current reconstruction dead zone toward six corner area of the space vector hexagon. Meanwhile, in order to guarantee the proposed method suitable in the whole linear modulation region, the suitable selection of the pulsewidth modulation switching period is analyzed in detail. Furthermore, the optimal selections of multiple sampling positions are discussed to lower the actual implementation difficulty of the proposed method. Finally, the experimental results on the PMSM demonstrate that the reconstructed phase currents with the proposed method can be always in consistent with the actual measured currents under different working conditions. [ABSTRACT FROM AUTHOR]

Photovoltaic (PV) systems having rechargeable batteries are prone to be complex and costly because multiple converters are necessary to individually regulate a load, PV panel, and battery. This paper proposes novel nonisolated multiport converters (MPCs) integrating a bidirectional pulsewidth modulation (PWM) converter and phase-shift-switched capacitor converter (PS-SCC) for standalone PV systems. A PWM converter and PS-SCC are integrated by reducing the total switch count, realizing the simplified system and circuit. In the proposed MPCs, two control freedoms of duty cycle and phase shift angle are manipulated to individually regulate the load, PV panel, and/or battery. The detailed operation analysis was performed to mathematically derive gain characteristics and zero voltage switching operation boundaries. For the battery discharging mode, in which the PV panel is not available and the MPC behaves as a single-input–single-output converter with two control freedoms available, the optimized control scheme achieving the lowest rms current is also proposed to maximize power conversion efficiencies. Various kinds of experimental verification tests using a 200-W prototype were performed to verify the theoretical analysis and to demonstrate the performance of the proposed MPC. [ABSTRACT FROM AUTHOR]

As research in matrix converters (MCs) has progressed over time, space vector modulation has emerged as the most popular technique for their modulation. Lately, model predictive control (MPC) has also been explored for the modulation and control of MCs, primarily gaining popularity due to the ease in realization of multiple objectives, as desired in MCs. However, multi-objective MPC employs assignment of weights to each control objective, wherein weight tuning is either empirical in nature or computationally cumbersome. This paper proposes a new modulation technique for MCs, inspired from delta sigma modulation for voltage source converters, that can be used for load voltage and source current control of MCs. Since source currents are samples of the load current envelope, it is required that this envelope be known for the control of source current. To eliminate load current sensors, predictive model of the load is used in envelope estimation. Further, independent switching schemes are generated for each objective, and an error minimization approach is used in integrating the two schemes into a final state selection, hence eliminating weighing factors. Unlike MPC, error predictions for all states of MCs, are not needed, hence facilitating easier implementation without significant processor burden, besides ensuring the quality of response. [ABSTRACT FROM AUTHOR]

A multilevel drive can be realized by using an open-ended machine, fed from dual two-level inverters. The topology supplied from isolated dc sources is suitable for transportation electrification. In vehicular systems, it is essential that the isolated dc sources, comprising of battery packs, should discharge uniformly and maintain balanced dc voltage at the dc-link terminal. A simple carrier-based pulsewidth modulation (PWM) technique is presented in this paper, which can effectively regulate the power drawn between the two two-level inverters while maintaining the multilevel operation of the drive. The modulation technique can balance the instantaneous state of charge of independent battery packs and dynamically equalize the power flow from the two inverters, based on drive requirement. This will enhance the reliability of the propulsion system in electric vehicles. The operation of the proposed PWM technique has been validated through detailed simulation and experimental tests. [ABSTRACT FROM AUTHOR]

A novel PWM full bridge (FB) dc–dc converter for large power industrial applications is proposed in this paper. The soft switching mode of the primary switches can be varied under different input and output conditions to achieve optimum system efficiency. In the zero-voltage and zero-current switching (ZVZCS) mode, the turn-on and turn-off switching loss can be optimized because the soft switching conditions of the turn-on and turn-off instants are well decoupled. In the zero-voltage switching (ZVS) mode, the turn-off switching loss can also be optimized because there is no requirement for light load operation in this mode. Four mosfets with ultra-low on-state resistance are used, thus, the added conduction loss is small. The auxiliary mosfets with high switching frequency are turned on with zero-current and off with zero-voltage, hence, the added switching loss can also be neglected. Furthermore, some drawbacks of the conventional ZVS and ZVZCS converters, e.g., narrow ZVS load range, high primary circulating current, incomplete reset of the primary current, and unreasonable VA rating of the added components, have been well solved. The operation principles and soft switching characteristics are discussed. Experimental results from an 18-kW prototype are provided to verify the proposed converter. [ABSTRACT FROM AUTHOR]

Numerous studies show that power semiconductors are significant contributors to the overall failure rate of pulsewidth modulation (PWM) voltage source rectifier (VSR) systems. Aimed at this problem, this paper presents an improved diagnosis system for open-circuit faults of a three-phase PWM VSR based on ac current distortion characteristics, which consists of a diagnosis module, a register module, and a decision module. The diagnostic module employs a hysteresis comparator to judge the change trend of the currents, and thereby diagnoses the single open-circuit (OC) faults. The register module is employed to achieve multi-switch OC fault diagnosis, and the decision module is used to output the final result. The proposed method extends the previous work to multi-switch OC fault conditions as well as improves the diagnosis accuracy. The experimental results show that the proposed method can correctly achieve fault diagnosis, including 6 kinds of single-switch faults and 15 kinds of different double-switch faults. Additionally, the proposed method also shows superior anti-interference performance and high robustness under abrupt load transient conditions, different power factor conditions, unbalanced and/or distorted grid voltage conditions, and different ac filter structure conditions. Furthermore, the average diagnostic time of this method is only 3.68 ms. [ABSTRACT FROM AUTHOR]

The inductance is an important parameter impacting current ripple calculation, usually with the assumption that the designed inductance performs ideally in most of voltage source inverters (VSIs) applications. However, the initial permeability of magnetic material usually descends when the winding current reaches or goes beyond the saturation limit. In such region of saturation, the implemented inductor does not perform as expected in design stages and its value varies with the bias current. In this paper, analysis and calculation of the current ripple are presented for a three-phase VSI with powder cores-based inductors, which reveals the calculation error of current ripple caused by the soft saturation nature of powder cores. Based on the equivalent single-phase model, the influence of inductance saturation on current ripple can be quantitatively evaluated. Then, a comparison of the current ripple calculation between considering and ignoring inductance saturation of implemented inductors is drawn in detail. Furthermore, under the condition of inductance saturation, the output current ripple peak-to-peak value of three phases is used as the constraint for variable switching frequency pulsewidth modulation (VSFPWM) design. A comprehensive method is developed to compensate the effect of inductance saturation in VSFPWM. At last, the effectiveness of the proposed strategy is verified by the detailed simulation and experiment. [ABSTRACT FROM AUTHOR]

Unipolar-pulsewidth modulation (UP-PWM) inverter takes advantages of high power efficiency and small output chokes which is widely used in the industry. However, UP-PWM inverters cannot be used in parallel operation due to a current unbalance problem. This paper studies the current unbalance problem of paralleled UP-PWM inverters with common dc bus and ac bus. First, the problem of unbalanced inductor current is defined and analyzed. Second, a technique to eliminate unbalanced currents is proposed. The proposed current balancing technique only requires one more current sensor in an inverter module rather than changing converter topology or modulation method, which makes it possible to apply UP-PWM inverters in parallel-operation while keeping the advantages of unipolar switching. The proposed current balancing method is verified by both simulation and hardware experiment. Experimental verification is performed on two 1 kW, 400 V input, and 120 V/60 Hz output prototypes, which shows a good agreement to the analytical study. [ABSTRACT FROM AUTHOR]

Parallel interleaved two-level (2L) three-phase voltage source inverters (VSIs) are widely used due to their distinct advantages of high power delivery, modularity, low current rating devices, etc. Along with these advantages, the parallel interleaved 2L VSIs could also be analyzed as a single three-level (3L) VSI. Conventionally parallel interleaved 2L VSIs are modulated using the 2L pulsewidth modulation (PWM) techniques. However, implementation of parallel interleaved 2L VSIs using the 2L PWM techniques may generate a higher ac side current ripple as compared to implementing the parallel interleaved 2L VSIs using 3L PWM techniques. This paper proposes a carrier-based method for implementing different 3L discontinuous PWM (DPWM) techniques for parallel interleaved 2L three-phase VSIs. Comparison of different 2L switching sequences for implementing a 3L DPWM switching sequence based on circulating current, line current ripple, and switching loss is also carried out. Simulation and experimental results are also displayed to validate the proposal. [ABSTRACT FROM AUTHOR]

This paper deals with the analysis of the input dc-link voltage ripple in multilevel inverter based on H-bridge and level doubling network (LDN). The LDN is basically a half-bridge fed by a floating capacitor, with voltage self-balancing capability, recalling the concept of a flying capacitor configuration. The amplitude of the LDN voltage ripple is analytically determined considering both the low-order and the switching harmonic components. In particular, peak-to-peak distributions of voltage ripples over the fundamental period are analytically determined, making possible the design of dc-link capacitor relying only on the dc-voltage ripple requirements. The case study makes reference to negligible switching ripple in the output current. It well represents either grid connection or passive load having almost sinusoidal currents. Numerical simulations carried out by MATLAB/Simulink and a complete set of experimental verifications are given to confirm the theoretical developments. [ABSTRACT FROM AUTHOR]

Droop control is broadly used in dc power distribution systems, e.g., dc microgrids. Implementing droop control for switch mode power supplies requires the measurement of average current. Synchronous sampling is used in digital control systems to obtain the average of a triangular inductor waveform. However, the dead time, semiconductor turn-on and turn-off delays, and signal conditioning delays shift the sensed waveform and change the effective duty cycle, resulting in a misalignment and measurement error from the average value. This paper proposes a duty cycle weighted averaging method based on double sampling. By sampling twice per switching period and averaging the results using duty cycle as the weighting factor, the error due to waveform misalignment is theoretically eliminated. The result always equals the average value of the triangle. This method does not rely on the knowledge of circuit delays, making it easy to implement and robust to parameter variations. Simulations and experimental measurements validate the superior performance compared with conventional single and double sampling methods. The experiment on a droop-controlled dc–dc converter demonstrates a more accurate droop characteristic. [ABSTRACT FROM AUTHOR]

According to different clamping methods, nine modes (C_MODE1-9) of the traditional discontinuous pulsewidth modulation (DPWM) for neutral-point-clamped three-level converter have been revealed. Since traditional DPWM cannot balance neutral point (NP) voltage under the full range of modulation index (MI) and power factor (PF), two extended modes (E _MODEs) are proposed in this paper, which can balance NP voltage. The proposed extended discontinuous pulsewidth modulation (EDPWM) is characterized by using C_MODEs and E_MODEs alternately.Therefore, EDPWM can balance NP voltage under the full range of MI and PF. Since the switching numbers under C_MODE and E_MODE in one switching cycle are two and three, respectively, the switching loss under EDPWM is lower than that under other pulsewidth modulation (PWM) strategies. The performance of EDPWM is analyzed and compared with traditional DPWM, space vector PWM (SVPWM) and virtual SVPWM (VSVPWM) in terms of switching loss, waveform quality, and the ability of NP voltage control. Finally, the feasibility and superiority of the proposed method are verified by experiments. [ABSTRACT FROM AUTHOR]

The pulse-width modulated (PWM) switching rectification that can achieve a high power factor (PF) for increasing the energy transfer efficiency between an LC resonator and a rectifier and voltage step-up and -down conversion is proposed for a wireless power transfer (WPT) receiver. The proposed method can emulate the switching rectifier as a resistive load by using an inductor and integrated phase synchronizers. Additionally, similar to a switched-inductor converter that controls the duty cycle ratio (D), the proposed PWM rectifier can control the output voltage VOUT when the input is a rectified, wirelessly coupled voltage instead of a constant voltage. Thus, unlike a conventional PWM switching rectifier for ac mains, an additional voltage conditioning circuit would not be needed after the proposed rectifier for WPT. The proposed PWM switching rectification is implemented in the AMS 0.18 μm 1.8 V/5 V CMOS process. PF = 1 is measured, indicating the most efficient energy transfer, compared to only 0.55–0.65 in a peak detection rectifier. Additionally, 88.2% of peak power conversion efficiency of the switching rectifier is achieved, and the maximum output power is 80.3 mW at 500 kHz of the WPT frequency. Moreover, the measured voltage conversion ratios ranging between 0.73× and 2× are demonstrated in this paper. [ABSTRACT FROM AUTHOR]

This paper proposes a novel pulsewidth modulation cell-level diffusion charge redistribution (DCR) converter based on a switched capacitor converter (SCC) utilizing diffusion capacitance of photovoltaic (PV) cells for PV modules under partial shading. Although a discrete inductor and capacitor are additionally necessary, Joule losses associated with switching operations can be reduced compared to the conventional capacitorless DCR converter. First, ac impedance measurement for a PV cell with 125 × 125 mm was performed, and the diffusion capacitance values were measured to be approximately 6.0 mF at its maximum power point voltage of 0.574 V. Second, the theoretical loss model was derived based on the detailed analysis, and it revealed that an optimal duty cycle achieving the lowest Joule loss was dependent on shading conditions. Third, a dual maximum power point tracking (MPPT) algorithm that controls duty cycles of not only the DCR converter, but a front-end boost converter is also proposed. With the dual MPPT control, the DPP converter operates at its optimal duty cycle to minimize the Joule loss while the boost converter seeks the MPP. The experimental results demonstrated that the maximum power significantly increased, thanks to the DCR converter, and that both the DCR and boost converters operated with respective optimal duty cycles. [ABSTRACT FROM AUTHOR]

This paper proposes a new grid current controller for a photovoltaic (PV) module integrated buck inverter using a single pulsewidth modulation switch and an unfolding H-bridge, which significantly reduces switching losses. To achieve this, an internal grid current loop with active damping is presented with an LCL filter to connect it to the utility grid. The problem of the filter natural resonance is solved by means of a virtual impedance (active damping), demanding no additional sensor. Experimental results obtained from a 200-W prototype achieved a European efficiency of 96.27% with a current total harmonic distortion of 3.7%. [ABSTRACT FROM AUTHOR]

This paper presents a novel approach to derive a pulsewidth modulation (PWM) technique for the generalized multi-phase drive. This novel approach is called a phase traversing principle. The given phase traversing principle is applied to the proposed PWM technique for five-phase open-end winding induction motor drive fed from a single dc source. The proposed PWM technique has the benefits of phase clamping, symmetrical operation of inverters, and common-mode current (CMC) elimination. Thus, it reduces the switching losses and also minimizes the issue of the CMC. The symmetrical operation of dual inverters further helps in the even distribution of losses. Also, the proposed PWM technique gives a good harmonic performance. The performance of the proposed PWM technique is analyzed using the switching loss function and harmonic flux trajectory methods. The first analysis gives justification of the reduced switching losses. While the second analysis gives the deviations in the motor flux with respect to variation in. modulation indices The proposed PWM technique is verified with both simulation and hardware results. [ABSTRACT FROM AUTHOR]

In order to reduce switching loss of neutral point clamped three-level inverter (NPC TLI), generally discontinuous pulsewidth modulation (DPWM) is used. But it can result in dc offset and ac ripple on neutral point (NP) voltage. So a novel pulse sequence DPWM (NPSDPWM) is proposed to reduce switching loss and control NP voltage simultaneously in this paper. NP voltage is controlled by choosing proper clamping modes. To avoid unexpected switching action during changing clamping mode, an improved pulse sequence is also presented. The switching loss and NP voltage ripple of NPSDPWM, traditional and proposed DPWM in previous literature are compared, respectively. The experimental results show that NPSDPWM has well NP voltage control ability and the switching losses are reduced effectively. [ABSTRACT FROM AUTHOR]

Direct power control (DPC) has been proposed as an effective control method for pulsewidth modulated (PWM) converters. The recent development focuses on the integration of the model predictive (MP) control and DPC to obtain better steady-state performance. In most MP-DPCs, duty cycle optimization (DCO) is a common technique to achieve the power error minimization. However, the periodic occurrence of a duty cycle larger than one (D > 1) deteriorates the performance of the PWM converter by inducing current spikes and power surges. To address this problem, this paper conducts an in-depth examination on the “D > 1” case common in MP-DPC using DCO. It is found the “D > 1” case is caused by the wrong control action of the active power in the starting period of each sector. Furthermore, a new table containing an additional pre-calculated interval in every sector is developed to eradicate the “D > 1” case and its associated power quality issues. Both simulation and experimental results are provided to demonstrate the effectiveness of the new table. [ABSTRACT FROM AUTHOR]

In this paper, a generalized switching modification method is proposed to reduce the root-mean-square (rms) current flowing into a dc-link capacitor in a dc–dc–ac structure consisting of a boost converter and a three-phase inverter. To analyze the current flowing into the capacitor, we analyze the currents at the respective converter and inverter sides. Based on this analysis, we derive an analytical method to find the modification time between the converter and inverter pulsewidth modulation (PWM) carriers through a Fourier series and approximation to facilitate real-time implementation. Real-time implementation of the modification time calculated by the derived method is described. To verify the validity of the proposed method, experimental results are presented based on a 1-kVA dc–dc–ac prototype. The proposed method has a better capacitor rms current reduction performance than the conventional method in various inverter power factors and PWM strategies. Especially, it has an excellent performance in mid-power factor level (0.95–0.1). [ABSTRACT FROM AUTHOR]

In this paper, a hybrid switch with the combination of large-current silicon (Si) insulated gate bipolar transistor (IGBT) and small-current silicon carbide (SiC) metal-oxide semiconductor field-effect transistor (mosfet) is utilized in a three-phase T-type three-level grid inverter. The hybrid switch can optimize the cost of the system while achieving high efficiency. The relationship between efficiency improvement and cost of the hybrid switch is investigated. Several switching patterns, which can decrease the loss of the small-current SiC mosfet for the hybrid switch, are studied. Different switching patterns for the hybrid switch of the grid inverter are compared based on the inverter efficiency. Finally, a 20 kW three-phase T-type three-level grid inverter prototype with the hybrid switch of large-current Si IGBT and small-current SiC mosfet (1:2.4 SiC/Si current ratio) is built to verify the main results. [ABSTRACT FROM AUTHOR]

This paper proposes a new pulse amplitude width modulation (PAWM) procedure for cascaded H-bridge multilevel inverters fed by dc voltage sources with unequal amplitudes. With proposed procedure, the generated output voltage is obtained modulating a sinusoidal reference signal at the desired fundamental frequency with equally spaced switching angles. It has been analytically demonstrated that, under these assumptions, all harmonics except those of order $n=2kl\pm 1$ , $k=1,2,\ldots$ are deleted from the output voltage waveform. After a detailed description of the method and a comparative analysis with others existing in the literature, its harmonics elimination capability has been experimentally verified with 5-, 7-, 9-, and 11-level cascaded H-bridge inverters, moreover, it has been mathematically demonstrated that it reduces total harmonic distortion below 5% with a 17-level inverter and it is capable of eliminating the first 49 harmonics considered by standards with a 27-level inverter. [ABSTRACT FROM AUTHOR]