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According to the number of segments, the space vector modulation (SVM) can divide into conventional SVM sequence (CSVMS) and special SVM sequence (SSVMS). It is well known that SVM can be equivalently realized by carrier-based pulse width modulation (CBPWM) with a zero component injection in both two-level and three-level inverters. For eight segment CSVMS in three-level inverters, many papers have ever got the injected zero component equation. But similar approach does not work for SSVMS, which has more than eight segments, e.g., 10, 12, or 14. What more, the accurate injected zero component has never been achieved so far. To solve above problems, therefore, a generated decomposition method of modulation wave has been proposed in this paper. By strict theoretical derivation, the same correlation can be extended to SSVMS and the corresponding zero component expression can be acquired. Based on this method, this paper puts a lot attention on the essential feature explanation, mathematical proof, and gives a detailed process to get the zero component equation, using it can realize SSVMS by CBPWM. The simulation and experimental results illustrate that the generated decomposition method of modulation wave is correct, and the unified theory of CBPWM and SVM is verified. [ABSTRACT FROM AUTHOR]

This paper investigates time-domain analysis of sampling effect in digital pulsewidth modulation (DPWM) of dc–dc converters. The relation between the sampling delay, duty ratio, and multisampling factor (sampling to carrier frequency ratio) has been characterized. The sampling delay of the digital controller used for DPWM of the dc–dc converter has close relation with the actual pulsewidth-modulation output. An increase in the multisampling factor can reduce the delay effect of the DPWM. The output voltage varies as a stepped function of the duty ratio instead of the linear function as observed in ideal modulation. It is shown in this paper that this delay is a periodic function of the duty ratio. The effect of variations in the sampling frequency, switching frequency, and modulation index has been analyzed. The proposed sampling effect has been verified analytically for the buck, boost, and buck–boost dc–dc converters. The experimental results for the buck and boost converters have been obtained with the control circuit realized through a field-programmable gate array-based digital controller. [ABSTRACT FROM PUBLISHER]

This paper presents an integrated solution for a photovoltaic (PV)-fed water-pump drive system, which uses an open-end winding induction motor (OEWIM). The dual-inverter-fed OEWIM drive achieves the functionality of a three-level inverter and requires low value dc-bus voltage. This helps in an optimal arrangement of PV modules, which could avoid large strings and helps in improving the PV performance with wide bandwidth of operating voltage. It also reduces the voltage rating of the dc-link capacitors and switching devices used in the system. The proposed control strategy achieves an integration of both maximum power point tracking and V/f control for the efficient utilization of the PV panels and the motor. The proposed control scheme requires the sensing of PV voltage and current only. Thus, the system requires less number of sensors. All the analytical, simulation, and experimental results of this work under different environmental conditions are presented in this paper. [ABSTRACT FROM AUTHOR]

In this paper, we propose model predictive control methods to reduce the common-mode voltage of three-phase voltage source inverters (VSIs). In the reduced common-mode voltage-model predictive control (RCMV-MPC) methods proposed in this paper, only nonzero voltage vectors are utilized to reduce the common-mode voltage as well as to control the load currents. In addition, two nonzero voltage vectors are selected from the cost function at every sampling period, instead of using only one optimal vector during one sampling period. The two selected nonzero vectors are distributed in one sampling period in such a way as to minimize the error between the measured load current and the reference. Without utilizing the zero vectors, the common-mode voltage controlled by the proposed RCMV-MPC algorithms can be restricted within ±Vdc/6. Furthermore, application of the two nonzero vectors with optimal time sharing between them can yield satisfactory load current ripple performance without using the zero vectors. Thus, the proposed RCMV-MPC methods can reduce the common-mode voltage as well as control the load currents with fast transient response and satisfactory load current ripple performance compared with the conventional model predictive control method. Simulation and experimental results are included to verify the effectiveness of the proposed RCMV-MPC methods. [ABSTRACT FROM AUTHOR]

In this paper, various types of discontinuous space vector pulse-width modulation techniques for a three-leg voltage source inverter supplying balanced two-phase loads are proposed. The main objectives of the paper are to analyze switching loss characteristics associated with semiconductor devices and to reduce output current ripple by dealing with various types of zero space vector time in each switching sequence. Capabilities of reductions in switching losses and current ripple for both balanced and unbalanced output phase voltages at high modulation index and load power factor angle of 30° lagging are focused. The validity of the proposed techniques is verified by simulation and experimental results in terms of voltage spectrum, current waveforms, reductions in switching losses, and output current ripple at high modulation index when compared to a continuous space vector pulse-width modulation technique. [ABSTRACT FROM AUTHOR]

A solid-state transformer is a three-phase ac/ac converter with a high-frequency transformer. Due to advanced features like high power density, on demand var support and frequency regulation, solid-state transformer is an enabling technology for the modern power distribution system. It can also find application in high-power-density motor drives. The single-stage solid-state transformer considered in this paper is capable of bidirectional power flow and open loop power factor correction. This topology uses a minimum amount of copper and has relatively few semiconductor switches. One major problem in this converter is the commutation of leakage energy which results in power loss, reduction in switching frequency, loss of output voltage, and additional common-mode voltage switching. This paper presents a source-based commutation strategy along with a novel modulation technique resulting in elimination of additional snubber circuits, minimization of the frequency of leakage inductance commutation, recovery of the leakage energy, and soft switching of the output converter. The topology and its proposed control have been analyzed. Simulation and experimental results confirm the operation. [ABSTRACT FROM AUTHOR]

Based on the Z-source inverter, this paper proposed a novel approach to zero-crossing point (ZCP) detections during the shoot-through vectors for sensorless brushless dc motor (BLDCM). The proposed approach separates the ZCP detections from speed adjustment, and makes the shoot-through vector not influence the motor speed-adjustment directly, while the zero-vectors and active-vectors are used exclusively to adjust the speed of BLDCM. With the proposed approach, the sensorless BLDCM can operate in a wide speed range without switching the detection points and the reference levels, and it is unnecessary to change the reference levels according to the PWM technique. The terminal voltages limited by diode can be directly compared with the reference zero level during the shoot-through vectors, so as to reduce the detection error caused by attenuation. Moreover, Z-source inverter not only provides boost voltage for sensorless BLDCM drive system, but also improves the utilization rate of dc source voltage and the safety of the drive system. In addition, this paper analyzed the terminal voltages of the floating phase during each vector. The experimental results verified the correctness of above theories and proved the effectiveness of the proposed approach. [ABSTRACT FROM AUTHOR]

Pulse width modulation (PWM) converters generate switching common-mode voltages (CMVs) across the load terminals. These voltages cause common-mode currents, leading to bearing failure in motor loads and electromagnetic interference problems. This paper presents a generalized carrier-based PWM technique for open-end winding motor drives that completely eliminates switching CMV. The proposed method is applicable to both dual two-level voltage source inverter and dual matrix converter-based open-end winding drives. Detailed analysis shows that the carrier-based method requires significantly less computation compared to the corresponding space vector implementation. This paper also outlines the relationship between the two implementations. The carrier-based method is shown to achieve superior performance in terms of resource requirements and execution time when implemented on a field-programmable gate array-based real-time control platform. Simulation and experimental results have been presented to validate the proposed method. [ABSTRACT FROM AUTHOR]

This paper proposes a space vector modulation (SVM) strategy for asymmetrical cascaded multilevel converters operating under fault conditions on the power cells. During each switching interval, one voltage vector is chosen to be implemented by the high voltage cells. It is then subtracted from the reference, resulting in a new reference for the low voltage cells. However, under fault conditions, if the high voltage vectors are not properly chosen, the converter may saturate. This paper presents a comparison between the choice of the high voltage vector as the nearest one to the reference, and as the one whose domain encompasses it. It is shown that the second choice is better, as it avoids saturation of the converter as much as possible. The proposed SVM is performed in the output line-to-line voltages coordinate system, in which the converter voltage vectors have only integer entries. The algorithm is presented considering as an example a converter with two cells per phase: one of 1 pu that switches with PWM, and one of 2 pu, switching at the fundamental frequency, respectively called low-voltage-high-frequency and high-voltage-low-frequency cells. Finally, experimental results are given to demonstrate and validate the good performance of the proposed SVM. [ABSTRACT FROM AUTHOR]

Exploiting the rich switching redundancies of the dual inverter, new hybrid pulsewidth-modulation (PWM) switching methods are proposed in this paper using the degree of freedom of operating the individual inverters independently, in addition to exercising the degree of freedom of controlling the switching action of the individual legs independently. Two voltage entities, namely, common-mode voltage (CMV) and differential-mode voltage are identified in the dual inverter, and all hybrid PWMs are envisaged aimed at reducing and also eliminating the CMV in it. The effects of such attempts on motor shaft voltage and also the motor bearing currents are presented in detail. Furthermore, bearing current profiles of an open-end winding induction motor are also presented with both conventional and hybrid PWMs proposed in this paper. Electric discharge machining discharge currents are completely eliminated with the use of all hybrid PWM methods proposed in this paper. In addition, implications of completely eliminating the CMV are also presented in this paper. All hybrid PWMs proposed in this paper are first simulated using MATLAB and are experimentally verified on a dual two-level inverter feeding a 1.1-kW 415-V 3- $\phi$ open-end winding induction motor drive. [ABSTRACT FROM PUBLISHER]

Multilevel inverters with dodecagonal (12-sided polygon) voltage space vector structure have advantages, such as complete elimination of fifth and seventh harmonics, reduction in electromagnetic interference, reduction in device voltage ratings, reduction of switching frequency, extension of linear modulation range, etc., making it a viable option for high-power medium-voltage drives. This paper proposes two power circuit topologies capable of generating multilevel dodecagonal voltage space vector structure with symmetric triangles (for the first time) with minimum number of dc-link power supplies and floating capacitor H-bridges. The first power topology is composed of two hybrid cascaded five-level inverters connected to either side of an open-end winding induction machine. Each inverter consists of a three-level neutral-point-clamped inverter, which is cascaded with an isolated H-bridge making it a five-level inverter. The second topology is for a normal induction motor. Both of these circuit topologies have inherent capacitor balancing for floating H-bridges for all modulation indexes, including transient operations. The proposed topologies do not require any precharging circuitry for startup. A simple pulsewidth modulation timing calculation method for space vector modulation is also presented in this paper. Due to the symmetric arrangement of congruent triangles within the voltage space vector structure, the timing computation requires only the sampled reference values and does not require any offline computation, lookup tables, or angle computation. Experimental results for steady-state operation and transient operation are also presented to validate the proposed concept. [ABSTRACT FROM PUBLISHER]

Many publications have been presented on the modulation and control of the modular multilevel converter, some of which are based on phase-shifted carrier modulation. This paper presents an analysis of how the switching frequency affects the capacitor voltages, circulating currents, and alternating voltages using phase-shifted carrier modulation. It is found that switching frequencies that are integer multiples of the fundamental frequency should be avoided as they can cause the capacitor voltages to diverge. Suitable switching frequencies are derived for which the arm and line quantities will be periodic with symmetric operating conditions in the upper and lower arms. Thus, the practical outcome of this paper is a detailed description of how the switching frequency should be chosen in order to achieve advantageous operating conditions. The theoretical results from the analysis are validated by both simulations and experimental results. [ABSTRACT FROM AUTHOR]

This paper presents a new multilevel selective harmonic elimination pulse-width modulation (MSHE-PWM) technique for transformerless static synchronous compensator (STATCOM) system employing cascaded H-bridge inverter (CHI) configuration. The proposed MSHE-PWM method optimizes both the dc-voltage levels and the switching angles, enabling more harmonics to be eliminated without affecting the structure of the inverter circuit. The method provides constant switching angles and linear pattern of dc-voltage levels over the modulation index range. This in turns eliminates the tedious steps required for manipulating the offline calculated switching angles and therefore, easing the implementation of the MSHE-PWM for dynamic systems. Although the method relies on the availability of the variable dc-voltage levels which can be obtained by various topologies, however, the rapid growth and development in the field of power semiconductor devices led to produce high-efficiency dc-dc converters with a relatively high-voltage capacity and for simplicity, a buck dc-dc converter is considered in this paper. Current and voltage closed loop controllers are implemented for both the STATCOM and the buck converter to meet the reactive power demand at different loading conditions. The technique is further compared with an equivalent conventional carrier-based pulse-width modulation to illustrate its enhanced characteristics. The effectiveness and the theoretical analysis of the proposed approach are verified through both simulation and experimental studies. [ABSTRACT FROM AUTHOR]

This paper presents the voltage- and current-limited operation of an interior permanent magnet synchronous machine (IPMSM) using deadbeat direct torque and flux control (DB-DTFC). A commanded air-gap torque and stator flux can be achieved by the end of each pulsewidth modulation (PWM) period using DB-DTFC. However, it may take several PWM periods to achieve a desired air-gap torque that is physically infeasible in one step due to voltage limits. In that case, the torque and flux command trajectories operating over multiple periods can be developed to achieve deadbeat torque and flux response for every PWM period. The torque and flux command trajectories can be developed in different shapes depending on desired objectives. In this paper, a minimum-time ramp trajectory method is proposed to achieve both simple real-time implementation and fast and stable transient dynamics of IPMSM drives. Simulation and experimental results for the minimum-time ramp trajectory method for an IPMSM drive are presented. [ABSTRACT FROM AUTHOR]

In this paper, a real-time implementation of selective harmonic elimination pulsewidth modulation (SHEPWM) using generalized Hopfield neural network (GHNN) as applied to the single-phase inverter is designed and discussed. Finding the location of the switching instants in the case of SHEPWM involves the solution of a set of nonlinear algebraic transcendental equations. The problem is redrafted as an optimization problem, and it is solved by using GHNN. Though, in principle, the $n$ number of harmonics can be eliminated using the presented methodology, this paper tries for the case of the elimination of the 5th-, 7th-, 11th-, and 13th-order harmonics while retaining the desired fundamental. An energy function is formulated for this problem and the set of ordinary differential equations (ODEs) describing the behavior of GHNN is obtained. A program in KEIL C was developed to solve these systems of ODEs by the Runge–Kutta fourth-order method to give the switching instants for continuously varying modulation indexes $(M)$. A MATLAB simulation was carried out, and an experimental setup was also constructed in order to validate the simulated results. The fast Fourier transform analysis of the simulated output voltage waveform and the experimental output voltage waveform confirms the effectiveness of the proposed method. Hence, the proposed method proves that it is much applicable in the industrial applications by virtue of its suitability in real-time applications. [ABSTRACT FROM PUBLISHER]

This paper presents a fast and generalized space vector pulse width modulation (SVPWM) scheme for any multilevel inverter. The SVPWM scheme generates all the available switching states and switching sequences based on two simple and general mappings, and calculates the duty cycles simply as if for a two-level SVPWM, thus independent of the level number of the inverter. Because the switching states, duty cycles, and switching sequences are all obtained by simple calculation in the proposed SVPWM scheme, no lookup table is needed and the scheme is computationally fast. The generalized method of generating the switching states (first mapping), calculating the duty cycles, and determining the switching sequence (second mapping) is described in this paper. The scheme is suitable for any reference vector with any modulation index, and can be conveniently extended to meet specific requirements, such as symmetric switching sequences. Compared with prior methods, the SVPWM scheme proposed in this paper provides two more degrees of freedom, i.e., the adjustable switching sequences and duty cycles, thus offering significant flexibility for optimizing the performance of multilevel inverters. The influence of redundant switching sequences in the output phase voltage of inverters is demonstrated for a nine-level inverter. This paper also thoroughly compares the proposed SVPWM scheme with prior methods. Both simulation and experimental results are given. [ABSTRACT FROM AUTHOR]

This paper presents the direct compensation of the switching interval error of the effective voltage vectors by the dead time of a pulsewidth modulation voltage source inverter (PWM-VSI). The output voltages of a three-phase PWM-VSI are distorted and have voltage errors from the dead time to avoid the shoot-through of inverter arms and the time delay of the gate drive. Voltage distortion increases the harmonics of the output voltages and decreases control performance. This paper presents a simple and direct compensation technique to solve this problem in a three-phase VSI. The practical switching output voltages are determined by the dc-link voltage, the switching signals of each phase, the dead time, the time delay, and the current polarities of each phase. For these reasons, output voltage errors are not constant. In order to analyze the dead-time effect in the actual switching voltages of each phase, the practical switching voltages in a sampling period of a space vector PWM (SVPWM) method are calculated according to the current polarity. In the calculation, the dead time, the time delay of devices, and the voltage drops on power devices are included to consider nonlinear voltage distortion. From these practical switching voltages during the switching intervals in a sampling period, the average output voltages of each phase can be derived, and the output voltage errors between the voltage commands and the average output voltages of each phase are obtained. The SVPWM switching intervals of each phase can be derived by the average output voltages that are calculated according to the current polarity and nonlinear voltage distortion to compensate for the output voltage errors. With the simple detection of the current polarity, the practical errors of the switching intervals of each phase can be compensated by the addition of the compensated switching time. Simulation and experimental results validating the proposed compensation method are presented in this paper. [ABSTRACT FROM AUTHOR]

Insertion of dead time, transfer links between micro control unit (MCU) and voltage source inverter (VSI), VSI's nonideal characteristics all lead to deviation that cannot be ignored between the actual output voltage and the command voltage, which seriously affects the performance of the ac induction motor (ACIM) control system. Among many dead-time effect compensation methods, VSI usually operates under an open-loop condition, thus making complete compensation hard to achieve. This paper studies methods to obtain the two key elements of compensation voltage amplitude and current polarity and a novel phase voltage compensation method is proposed. In this method, a simple hardware circuit is applied to obtain the actual output of the VSI as feedback with which precise compensation amplitude can be calculated. And judgment of current polarity is accurately realized by reconstructing phase current from filtered current components under M-T coordinate with a Kalman filter. The compensation in a zero-crossing region is also closely discussed in this paper. To verify the validity of the method, simulations and experiments are carried out. The experiments emphasize on the efficacy of feedback, steady-state, and transient performance of current reconstruction; and the performance of a conventional method to that of the proposed method are also compared. Results show that the proposed method proves to be effective. [ABSTRACT FROM AUTHOR]

Switch fault diagnosis is an important design aspect for pulse width modulation (PWM) dc-dc power converters. It can prevent power converters from further damage, and also make preparations for remedial actions. In this paper, a fast switch fault diagnostic method is proposed for PWM dc-dc converters operating in continuous conduction mode. The proposed method utilizes the magnetic component (inductor or transformer) voltage for fault diagnosis. Based on the real-time voltage measurement and switch gate-driver signals, characteristics of switch open-circuit faults and short-circuit faults are rapidly extracted, and thus, switch faults can be quickly detected. The magnetic component voltage can be measured by an auxiliary winding in the magnetic core, and gate-driver signals can be easily got from the control circuit. Moreover, the fault detection can be implemented by a low-cost logical hardware circuit, and this circuit can be integrated into the control circuit. The fault diagnosis principle, design considerations, and implementation are discussed in this paper. Experiments are conducted to verify the theoretical analysis. [ABSTRACT FROM AUTHOR]

A two-motor drive, supplied by a five-leg inverter, is considered in this paper. The independent control of machines with full dc-bus voltage utilization is typically achieved using an existing pulsewidth modulation (PWM) technique in conjunction with field-oriented control, based on PI current control. However, model predictive control (MPC), based on a finite number of control inputs [finite-control-set MPC (FCS-MPC)], does not utilize a pulsewidth modulator. This paper introduces three FCS-MPC schemes for synchronous current control in this drive system. The first scheme uses all of the available switching states. The second and third schemes are aimed at reducing the computational burden and utilize a reduced set of voltage vectors and a duty ratio partitioning principle, respectively. Steady-state and transient performances are analyzed and compared both against each other and with respect to the field-oriented control based on PI controllers and PWM. All analyses are experimental and use the same experimental rig and test conditions. Comparison of the predictive schemes leads to the conclusion that the first two schemes have the fastest transient response. The third scheme has a much smaller current ripple while achieving perfect control decoupling between the machines and is of low computational complexity. Nevertheless, at approximately the same switching loss, the PI-PWM control yields the lowest current ripple but with slower electrical transient response. [ABSTRACT FROM PUBLISHER]

This paper presents a comparison of two modulation methods for the seven-level switched-capacitor (SC) inverter using series/parallel conversion (SCISPC). The SCISPC is a multilevel inverter which has the less number of switching devices than the conventional multilevel inverters. The level-shifted pulsewidth modulation (PWM) (LS-PWM) was applied to the seven-level SCISPC in the previous research. In this paper, the level- and phase-shifted PWM (LPS-PWM) and the LS-PWM are applied to the seven-level SCISPC, and LPS-PWM is compared with LS-PWM for the seven-level SCISPC. The LPS-PWM has both the characteristics of the phase-shifted PWM (PS-PWM) and the LS-PWM. The voltage reduction during the discharging term of the SCs is reduced by means of the shorter discharging period compared to LS-PWM. The voltage ripple of the capacitors is also reduced, which leads to higher power conversion efficiency. The difference of the two modulation methods is confirmed by the theoretical approach, simulation with PSIM, and circuit experiment. [ABSTRACT FROM PUBLISHER]

A magnetic pulse compressor (MPC) transfers energy via $C$ – $L$ – $C$ resonance. The pulse width of the MPC is determined by the saturation inductance of the magnetic switch (MS). When using the MS, the pulse width is limited due to the stray elements. To increase the pulse compression rate, the number of stray elements must be reduced. In this paper, we propose an optimum design for an MS having the lowest impedance of stray elements, along with its analysis and experimental verification. The proposed model is designed to have a reduced magnetic path length while retaining the same saturation inductances as that of a common MS; this is accomplished by using the relationship between the magnetic field path length and the number of inductor turns. The experimental results show that the proposed MS decreases the full width at half maximum by 18% and increases the rise rate by 69%. This result demonstrates that the proposed MS increases the pulse compression rate of the MPC by reducing impedance of stray elements in the system. [ABSTRACT FROM AUTHOR]

Paralleled inverters are not only a suitable approach to increase the power capacity, but also have the capability of common mode voltage (CMV) reduction, or even elimination. The original zero CMV modulation scheme for paralleled inverters suffers from the current jump problem in phase-leg currents. This current jump phenomenon amplifies the peak values of differential-mode circulating current (DMCC) and zero-sequence circulating current (ZSCC), which is adverse for the design of coupled inductor and common-mode inductor. This paper introduces the modified modulation scheme, which can keep volt-seconds balance in whole fundamental period and mitigate the current jump in phase-leg currents. In addition, the reduction effect of the DMCC and ZSCC can be achieved. To verify the analysis, both the simulation and experimental results are presented, which validates the proposed methods and show that they are beneficial for DMCC and ZSCC reduction. [ABSTRACT FROM AUTHOR]

Three optimized pulse-width modulated (PWM) techniques for the overmodulation region of two-level inverter-fed ac drives are introduced and investigated from the harmonic loss minimization point of view. The optimization is elaborated for the lowest loss-factor, which is proportional to the square of the root mean square value of current harmonics. The loss-factors are computed for different switching numbers as the function of the motor fundamental voltage. It is shown that, with respect to the motor heating and torque ripples, the acceptable drive condition can be guaranteed by a relatively low value of an inverter switching frequency up to 96%–97% of maximal possible motor voltage. Furthermore, it is shown that the so-called three-vector methods have considerably better performance in the lower part of the overmodulation region than the so-called two-vector method for the same number of switching. The performance of the techniques is compared with other existing PWM techniques. This paper discusses the implementation details of the proposed optimal PWM techniques. The theoretical results are verified by experimental and simulation tests. [ABSTRACT FROM AUTHOR]

Conventional zero-voltage and zero-current-switching (ZVZCS) full-bridge converters are widely used because they can realize zero-voltage switching (ZVS) for the leading leg and zero-current switching (ZCS) for the lagging leg. However, the large turn-off loss of the leading leg is still unacceptable in high-voltage high-power applications where insulated-gate bipolar transistors (IGBTs) with current tailing are employed. Hence, it is preferable to achieve ZCS for all IGBTs of full-bridge converters. This paper analyzes the ZCS conditions for pulsewidth modulated (PWM) full-bridge converters and proposes a general strategy for achieving ZCS for main switches, including the control strategy and design method of the topology. Based on this theory, a novel ZCS PWM full-bridge converter with simple auxiliary circuit is derived and tested. It can achieve ZCS not only for the main switches of full-bridge converter, but for the auxiliary switch as well, and obtain high efficiency. The operation principle of the proposed ZCS PWM full-bridge converter and the design procedure are presented. The experimental results of a 600 V/2.5 kW prototype are also included to verify the theoretical analysis. [ABSTRACT FROM PUBLISHER]

One of the main drawbacks with the use of finite control set model predictive control (FCS-MPC) in power converters is the variable switching frequency. When not taken into consideration, it can vary randomly depending mainly on the operating point of the system and the sampling time. This will produce a wide distributed voltage and current spectrum, causing audible noise, resonances, and poor steady-state behavior. To address this issue, a new algorithm, based on the control of the switching period within the cost function, is proposed in this paper. The algorithm shows to be very effective in achieving a regular commutation pattern, similar to pulse width modulation (PWM) techniques, which is evidenced even by similarities in the sideband harmonics generated in the voltage spectrum. The algorithm is easy to design and implement, demanding very low computation power, and enables a combination of the advantages of FCS-MPC with the benefits of a PWM-like power quality. Simulations and experimental results are presented to validate the proposed method, which are compared to previously reported FCS-MPC techniques dealing with the same challenge. [ABSTRACT FROM PUBLISHER]

Soft switching pulse-width modulation (PWM) dc–dc full-bridge converter with controlled rectifier on the secondary side of the high-frequency power transformer is presented in this paper. An active secondary switch, including new nondissipative passive energy recovery turn-off snubber on the secondary side and modified PWM control algorithm, provide conditions for zero-voltage and zero-current turn-on and zero-current turn-off of IGBT transistors on the primary side of the high-frequency dc–dc converter. The simple passive energy recovery snubber ensures also zero-voltage turn-off of the transistor on the secondary side of the power transformer. The principle of operation is explained and analyzed and consequently verified on a 2 kW, 50 kHz laboratory model of the converter. [ABSTRACT FROM PUBLISHER]

This paper presents a general space vector modulation (SVM) method for the modular multilevel converter (MMC). Compared with earlier modulation methods, the proposed SVM method not only utilizes the maximum level number (i.e., $2n+ 1$, where $n$ is the number of submodules in the upper or lower arm of each phase) of output phase voltages, but also leads to an optimized control performance in terms of capacitor voltage balancing, circulating current suppression, and common-mode voltage reduction. The maximum level number is achieved by introducing a new equivalent circuit of the MMC, and the optimized control is obtained by selecting the optimal redundant switching states. Since the computational burden of the SVM scheme is independent of the voltage level number, the proposed method is well suited to the MMC with any number of submodules. Simulation and experimental results are presented to validate the proposed method. [ABSTRACT FROM PUBLISHER]

This paper proposes a hybrid strategy by combining fundamental pulsewidth modulation excitation (FPE) and additional test vectors, which is used in interior permanent-magnet synchronous motor (IPMSM) sensorless control. In contrast to the typical indirect flux detection by on-line reactance measurement-based methodology where the rotor position is calculated and updated in every three successive pulsewidth modulation (PWM) cycles, the proposed hybrid strategy can achieve the one-cycle acquisition of the rotor position by utilizing both response currents of FPE and additional test vectors, which makes the proposed strategy more robust and suitable in higher speed or load sudden change conditions. Meanwhile, a new PWM scheme for four-space-vector PWM (FSVPWM) is presented, which sharply simplifies the implementation process. Furthermore, for the case that the amplitude of the object fundamental voltage is so small that it cannot satisfy minimum time demand for the slopes of response currents sampling, a compensation technique is presented. In addition, the multiple-point current sampling (MPCS) technology and linear least square fitting method are used to decrease the current sampling disturbance, which improves obviously the accuracy of position estimation. Finally, the experimental results confirm that the proposed strategy can obtain the rotor position accurately and simply. [ABSTRACT FROM PUBLISHER]

This paper proposes a switched-capacitor multilevel inverter for high-frequency ac power distribution systems. The proposed topology produces a staircase waveform with higher number of output levels employing fewer components compared to several existing switched-capacitor multilevel inverters in the literature. This topology is beneficial where asymmetric dc voltage sources are available, e.g., in case of renewable energy farms based ac microgrids and modern electric vehicles. Utilizing the available dc sources as inputs for a single inverter solves the major problem of connecting several inverters in parallel. Additionally, the need to stack voltage sources, like batteries or supercapacitors, in series which demand charge equalization algorithms, are eliminated as the voltage sources employed share a common ground. The inverter inherently solves the problem of capacitor voltage balancing as each capacitor is charged to the value equal to one of the input voltage every cycle. State analysis, losses, and the selection of capacitance are examined. Simulation and experimental results at different distribution frequencies, power levels, and output harmonic content are provided to demonstrate the feasibility of the proposed multilevel inverter topology. [ABSTRACT FROM PUBLISHER]

The flying-capacitor modular multilevel converter (FC-MMC) overcomes the low/zero-speed operation issues of conventional MMC-based drive. The FC-MMC injects no common-mode voltage (CMV) to the drive system. However, the pulse width modulator (PWM) introduces switching ripples, which appear as CMV on motor stator windings. To completely get rid of the CMV, an elimination method based on a new modulation scheme is proposed in this paper. The modulation algorithm places the switching pulses end to end for upper and lower arms, respectively. The consistent switching positions between upper and lower arms lead to the complete CMV elimination for FC-MMC-based drive system in entire speed range. Although the proposed method slightly increases the switching frequency as compared to conventional phase-shifted PWM, it is still acceptable in medium-voltage applications. The validation of the proposal is proved by simulations and experiments. [ABSTRACT FROM PUBLISHER]

In this paper, a novel optimized switching repetitive control (OSRC) scheme is developed and applied to a constant-voltage constant-frequency pulse width modulation inverter to enhance the stability and tracking performance with low sampling frequency. In OSRC, a switching integral phase lead compensator is applied to enlarge the stability margin, which is impaired by the phase lag of the inverter system. With the optimized switching strategy, the stable region can be much wider, which means that a larger robust filter $Q$ can be applied to reduce the tracking error. The stability analysis and optimized design procedure are also given. Comparative experiments in different load situations are performed to demonstrate the validity of the proposed scheme. [ABSTRACT FROM PUBLISHER]

Impedance network inverters are the best alternatives for voltage-source and current-source inverters. The boosting capability and the shoot-through solution of such converters make them excellent solutions for various applications. Nevertheless, hard switching forces the converter to operate in low switching frequency, which results in a bulky impedance network. Moreover, the coupling between the shoot-through duty cycle and the inverter modulation index makes a tradeoff between the voltage gain and the modulation index (output voltage harmonics). This paper presents a novel dual switching frequency modulation to mitigate the switching losses of the converter, which results in a more compact impedance network. The proposed method combines a high-frequency pulse width modulation with a low-frequency sinusoidal pulse width modulation (SPWM). Therefore, the switching losses decrease considerably with respect to the conventional simple boost modulation. In addition, the impedance network design frequency remains high, and the network size decreases obviously. The proposed approach removes the interdependence between the shoot-through duty cycle and the inverter modulation index. A comparison between the proposed method and the conventional simple boost method is performed to show its advantages over the conventional method. Finally, experimental results are presented to validate the performance of the proposed method. [ABSTRACT FROM PUBLISHER]

In trasformerless grid-connected photovoltaic (PV) systems, common-mode voltage (CMV) fluctuations cause leakage current flow through the stray capacitance of the PV panels. Shoot-through states in a quasi-Z-source inverter (q-ZSI) increase the amplitude of high-order harmonics of CMV. In this paper, by using the modulation technique based on odd pulse width modulation and minor change in the Z network of the three-phase q-ZSI, the leakage current is blocked. No extra semiconductor element is added. By the proposed technique, CMV is kept nearly constant during switching cycles. The experimental results for CMV analysis in a \text1\;\textkW prototype are presented to verify the theoretical analysis. [ABSTRACT FROM PUBLISHER]

Multilevel inverters (MLIs) have replaced conventional two-level inverters for medium-voltage high-power industrial applications. One of the best modulation techniques for MLIs is the space vector modulation (SVM). Although SVM has its own advantages, it has been overlooked for much simpler carrier-based modulation schemes in the industry. Nearest level modulation (NLM) is a simple alternative, which is functionally similar to SVM. In this paper, a new generalized SVM algorithm is presented, in which the SVM is achieved using the concept of NLM. A generalized switch matrix is introduced to derive gate pulses for the inverter, which further simplifies the algorithm. The algorithm is tested and verified for a three-phase, three-level, and five-level neutral-point-clamped inverters in both simulation and hardware. [ABSTRACT FROM PUBLISHER]

This paper extends the trans-Z-source concept to ac–ac power conversion and proposes a novel single-phase trans-Z-source ac–ac converter. The proposed converter retains the advantages of its existing Z-source/quasi-Z-source counterparts in which the output voltage can be boosted and in-phase with the input voltage or bucked/boosted and out-of-phase with the input voltage. Meanwhile, a coupled inductor is introduced into the proposed converter, and the turns ratio of the coupled inductor become another control variable beside the duty cycle to obtain extreme voltage gain. Importantly, the input voltage and output voltage share the same ground, and the input current could be continuous, which is a benefit for reducing input current harmonics. Most important of all, the safe-commutation strategy for the proposed converter is deep developed, and analytic expression between the switches state and loop circuit voltage/current condition is derived out. Hence, the current/voltage ripple can be avoided without a loss snubber circuit, which benefits a reduced cost and enhanced reliability. The performance analysis is discussed in consideration of parasitic resistance, and system parameter design is optimized based on theoretic calculation. A laboratory prototype is fabricated, and experiments are performed to verify the validation of the proposed converter. [ABSTRACT FROM PUBLISHER]

Interleaved converter legs are typically modulated with individual carriers per leg and phase-shifted pulse width modulation (PS-PWM) as it facilitates current balancing amongst the legs. Phase-disposition PWM (PD-PWM), despite the better harmonic performance, cannot be directly used due to the resulting current imbalance that may damage the converter. This paper addresses the current sharing issue and proposes a sorting algorithm implementation that enables single-carrier PD-PWM technique for interleaved two-level converter legs. An extension of the proposed algorithm through a switching state feedback loop, limiting the average switching frequency, is also developed. In both cases, the output current is of high quality and shared amongst the phase-legs, while the deviation between the phase-leg currents is well regulated. Simulation results demonstrate the general function of method for multiple interleaved legs as well as its current sharing capabilities for high-power applications. Experimental results from a low-power laboratory prototype validate the operation of the proposed approach. [ABSTRACT FROM PUBLISHER]

This paper proposes a pulse width modulation plus phase-shift (PPS) control for nonisolated high gain soft-switching bidirectional dc–dc converter (HSBDC). The phase-shift angle is used to control the direction and amount of power flow of the bidirectional dc–dc converter, while the duty cycle is used to balance the voltage between two high voltage side (HVS) capacitors. The HSBDC with PPS control has the advantages of simple control structure and symmetrical switching patterns, ensured soft-switching in both forward and backward modes at all load under wide voltage range, and reduced voltage ratings of the HVS capacitors and switches. The operation principle of the HSBDC with PPS control is analyzed in detail. Based on the analysis the passive component is designed to achieve higher efficiency. A 3-kW prototype is implemented and tested to verify the validity of the proposed method. [ABSTRACT FROM AUTHOR]

Maximum efficiency point tracking (MEPT) control has been adopted in state-of-the-art wireless power transfer (WPT) systems to meet the power demands with the highest efficiency against coupling and load variations. Conventional MEPT implementations use dc/dc converters on both transmitting and receiving sides to regulate the output voltage and maximize the system efficiency at the expense of increased overall complexity and power losses on the dc/dc converters. Other implementations use phase-shift control or on–off control of the transmitting side inverter and the receiving side active rectifier instead of dc/dc converters but cause new problems, e.g., hard switching, low average efficiency, and large dc voltage ripples. This paper proposes a pulse density modulation (PDM) based implementation for MEPT to eliminate all the mentioned disadvantages of existing implementations. Delta-sigma modulators are used as an example to realize the PDM. A dual-side soft switching technique is proposed for the PDM. The ripple factor of the output voltage with PDM is derived. A 50 W WPT system is built to validate the proposed method. The system efficiency is maintained higher than 70% for various load resistances when the power transfer distance is 0.5 m, which is 1.67 times the diameter of the coils. [ABSTRACT FROM AUTHOR]

Neutral-point (NP) voltage imbalance is an inherent problem of three-level neutral-point clamped (NPC) converter. To solve this problem, an improved virtual space vector pulse width modulation (VSVPWM) is proposed in this paper. A new repartitioning of the space vector sectors is proposed for three-level NPC converter by considering the amplitude variations of small vectors under NP voltage imbalance. The factor k of the NP voltage imbalance is introduced. The small vector favorable to the NP voltage balance is selected based on the factor k and phase current direction to achieve precise control and balancing of NP voltage. The proposed method can effectively maintain NP voltage balance and eliminate the low frequency oscillation of the NP voltage over the whole modulation index range. The improved VSVPWM also has advantages of good dynamic performance. The method has been tested and verified by simulations and experiments. [ABSTRACT FROM AUTHOR]

The noninverting buck–boost converter has attracted significant attention in the photovoltaic (PV) module integrated application, as it offers high efficiency while maintaining a low cost and a simple topology. When this converter is employed, special care must be taken at the transition between buck and boost operating modes, as a dead-zone in the voltage transfer function can cause abrupt perturbations in the controlled voltage, decreasing the regulation quality and ultimately lowering the power conversion efficiency. In this paper, a new dead-zone compensation technique is proposed with the scope of smoothing the transition between operating modes, eliminating the voltage ripple and improving the regulation performance, while maintaining high efficiency. The converter under analysis is studied together with its gate driving circuit, which is based on a bootstrap capacitor power supply for the high-side switches. The proposed dead-zone compensation technique is deduced by using the principle of maintaining the ideal voltage gain function across the converter operating range. The technique is analyzed, implemented and tested on a purposely built PV module integrated noninverting buck–boost converter. The experiments reveal a sensible improvement of the voltage regulation during mode transition, confirming the effectiveness of the proposed technique and its fitness for the PV application. [ABSTRACT FROM AUTHOR]

Five-level hybrid-clamped (5L-HC) converter is a newly proposed topology which is suitable for high-performance medium-voltage high-power conversions without switches directly connected in series. The critical issue of this converter is that two flying capacitor voltages of each phase and two neutral-point potentials of the dc-link need to be balanced. This paper presents a decoupled voltage balancing method for this 5L-HC converter based on modified phase-shifted pulse width modulation (PS-PWM) and optimal zero-sequence voltage injection. The voltages across the central dc-link capacitor and two flying capacitors are balanced first by adjusting the width of four PWM signals. Second, the relationship between the neutral-point currents and the output phase voltage is studied and the upper and lower dc-link capacitor voltages are balanced by zero-sequence voltage injection. Both steady-state and dynamic-state simulation and experimental results are presented to confirm the validity of this method. [ABSTRACT FROM AUTHOR]

Power conversion systems based on double-delta sourced winding (DDSW) had an optimization issue in terms of pulsewidth modulation (PWM). This issue was about inefficient employments of voltage levels during PWM and had to be considered for minimizing voltage stresses and current ripples on DDSW. In this paper, a novel method has been proposed to improve the performance of PWM in DDSW-based systems. The proposed method can be simply implemented as a carrier-based PWM and its principles are neatly summarized with equations. Finally, the effectiveness of the proposed method is demonstrated with experimental results, which were obtained by using a transformer and an induction machine. [ABSTRACT FROM PUBLISHER]

This paper presents the development and performance evaluation of the wavelet modulation technique for single-phase ($1\phi$) cascaded $H$-bridge (CHB) multilevel dc–ac power electronic converters (PECs). The developed technique is based on employing sets of resolution-segmented wavelet basis functions as switching signals, where each set operates one $H$ -bridge. The number of sets of wavelet basis functions is selected to match the number of levels in the output voltage of the $1\phi$ CHB dc–ac PEC. The wavelet modulation for $1\phi$ CHB multilevel dc–ac PECs is implemented for performance evaluation both in simulation and experimentation. The performance of the developed technique is evaluated for linear, nonlinear, and dynamic loads. Simulation and experimental results show significant reduction of output harmonics, along with high magnitude of the fundamental component in the output voltage. The improvements offered by the wavelet modulation technique are further demonstrated through comparisons with the level-shifted and phase-shifted pulse-width modulation techniques under similar loading conditions. [ABSTRACT FROM PUBLISHER]

This paper discusses the use of a cascaded multilevel converter for flexible power conditioning in smart-grid applications. The main feature of the proposed scheme is the use of independent dc links with reduced voltages, which makes such a topology an ideal candidate for medium- and high-power applications with increased reliability. The developed control strategy regulates independent dc-link voltages in each H-bridge cell, and allows the selective and flexible compensation of disturbing currents under a variety of voltage conditions without requiring any reference frame transformation. The selective control strategies are based on the decompositions proposed in the conservative power theory, which result in several current-related terms associated with specific load characteristics. These current components are independent of each other and may be used to define different compensation strategies, which can be selective in minimizing particular effects of disturbing loads. Experimental results are provided to validate the possibilities and performance of the proposed control strategies, considering ideal and deteriorated voltage conditions. [ABSTRACT FROM PUBLISHER]

As for ripple-current mode control, it cannot achieve average current tracking, resulting in poor current accuracy and even current waveform distortion. Meanwhile, fast-scale instability may occur in some operating conditions. To solve these problems effectively, a current-ripple compensation (CRC) control technique is proposed in this paper. The error between the average of the controlled current and the reference current is compensated by certain compensation signal, achieving average current tracking while suppressing fast-scale instability. On this basis, the compensator in the outer-voltage loop is further simplified to a proportional part by introducing a rebuilt average reference current. The idea and design procedure of the proposed CRC control technique are discussed in detail. Accordingly, two available implementation schemes for the proposed CRC are presented, including slope compensated and parabolic compensated schemes. Finally, two application cases, respectively, to dc–dc Buck converter and Boost PFC converter, are presented to verify the proposed CRC control technique. [ABSTRACT FROM PUBLISHER]

Presently, the neutral-point potential offset is an inherent problem for three-level converters on three-phase four-wire active power filters. The conventional three-dimensional space vector pulse width modulation (3-D-SVPWM) strategy is adopted as a normal solution to the problem, but the selection of space vector sectors for four-wire converter is both abstract and complicated in practice. This paper proposes a new PWM strategy accordingly to simplify the selection process and the calculation of duration. Compared to the conventional 3D-SVPWM, the proposed method locates the sector of optimal vector directly with the polarity of three-phase reference voltage. Then, by applying voltage–second balance rule, it can perform a fast calculation of the duration and generate PWM signals to control the switching devices’ on/off. As an approach to correct the imbalance dc-link capacitor voltage, this strategy reconstructs the switching sequence. A portion of state O duration is disassembled into states P and N to suppress the neutral-point potential offset. The proposed strategy is validated with a range of experiments. The results indicate that this simplified PWM strategy can effectively reduce the computational burden, and also the dc-link capacitor voltage is well controlled. [ABSTRACT FROM PUBLISHER]

This paper introduces series work of common-mode (CM) voltage reduction for the paralleled inverters. The paralleled inverters’ phase-legs are connected through coupling inductors and the combined three-phase currents are provided to the load. Interleaving is an approach to reduce the CM voltage for the paralleled inverters but it cannot eliminate CM voltage. A novel pulse-width-modulation (PWM) method for paralleled inverters which can theoretically achieve zero CM voltage is developed. Considering the basic voltage vectors in each inverter, novel paralleled voltage vectors which have zero CM voltage are proposed to combine the reference voltage vector. The action time's distribution and voltage vectors’ sending sequence for each inverter are also introduced. The proposed PWM method can make sure the voltage of the two inverters are balanced in each switching cycle and limits the circulating current through small coupling inductors. Similar to interleaving space vector PWM, the proposed zero CM PWM also has the ability to reduce the output current ripple and electromagnetic interference (EMI). Simulation and experimental results are provided to show the advantage of paralleled inverters in CM voltage reduction and validate the proposed method has good performance to reduce CM current and CM EMI noise. [ABSTRACT FROM PUBLISHER]

This paper aims to investigate a disturbance-rejection-based model predictive control (MPC) with two flexible modes (i.e., unconstrained mode and constrained mode) for three-phase inverters with an $LC$ filter. A disturbance observer (DOB) is designed to both simplify the prediction model and achieve the robustness against uncertain parameters. First, the unconstrained mode is designed with a simple horizon-one MPC control law to precisely regulate the output voltage in the steady state. Next, the constrained mode is designed with long-horizon MPC to quickly drive the system to the unconstrained mode by further optimizing the modulation stage. Also, the proposed MPC ensures the robustness and optimality in all operating modes. Especially, the overall closed-loop stability with DOB dynamics is proven by using Lyapunov function. Unlike other MPC methods, the long-horizon MPC in the constrained mode is specialized by finite switching sequences of the sector-based space vector modulation. Comparative studies with the conventional linear quadratic regulator are conducted on a prototype test bed with a TI TMS320F28335 DSP. Then, the proposed MPC method verifies fast dynamic response and advanced voltage regulation (i.e., small steady-state errors and low total harmonic distortion) under various load conditions and uncertain parameters. [ABSTRACT FROM AUTHOR]

In this paper, dual-buck structured single-stage buck–boost inverters that use power MOSFETs to achieve high efficiency are presented. The proposed inverters require fewer switches, and half of the switches have reduced current stresses. They have no shoot-through problem; therefore, high system reliability can be obtained. The dead-time in PWM signals can be minimized or eliminated, which improving the quality of the output ac voltages and increasing the efficiency. In the proposed inverters, MOSFETs can be used without reverse-recovery issues of their body diodes to boost the efficiency and increase the switching frequency. To further improve the efficiency and stability of the proposed single-phase inverter, PWM strategies combining high- and low-frequency modulation are presented. A hardware prototype of the single-phase inverter was built and tested using resistive, inductive, and nonlinear loads. Experimental results for a 300-W prototype inverter show a 97.4% peak efficiency with a 25 kHz switching frequency. [ABSTRACT FROM AUTHOR]