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This paper presents a neutral-point deviation and ripple compensating control method applied to a three-level neutral-point-clamped (NPC) converter. The neutral-point deviation and its harmonic components are analyzed with a focus on the average current flowing through the neutral-point of the dc link. This paper also proposes a control scheme compensating for the neutral-point deviation and dominant harmonic components under generalized unbalanced grid operating conditions. The positive and negative sequence components of the switching functions and ac input currents are employed to accurately explain the behavior of three-level NPC converter. Simulation and experimental results are presented to verify the validity of the proposed method. [ABSTRACT FROM AUTHOR]

This paper proposes an active switching harmonic current reduction method within the dc-link capacitor of two-level, three-phase, back-to-back converters. This method is based on the derived analytical solution for switching harmonic currents in the dc-link. It is shown that by controlling the pulse width modulation carrier waveform's phase angles, the harmonics in the second carrier band of the rectifier and the inverter can be synchronized such that cancellation occurs in the dc-link capacitor. This synchronization is provided by harmonic phase feedback control. The feasibility of the proposed approach has been verified experimentally and results are presented in this paper. [ABSTRACT FROM PUBLISHER]

The performance of modular multilevel converters (MMCs) in medium-voltage applications, where the number of required submodules is not high, can be improved utilizing low switching frequency modulations such as (2N+1) selective harmonic elimination-pulse width modulation (SHE-PWM), which provides tight control of lower order harmonics and low switching losses. This paper proposes a calculation method, which is based on a novel formulation, to solve the SHE-PWM problem. In particular, MMCs with (2N+1) phase output voltage levels are considered, obtaining a (2N+1) SHE-PWM waveform. This method utilizes a unique system of equations that is valid for any possible waveform. Therefore, it is able to calculate simultaneously, without predefined waveforms, both the switching patterns and the associated firing angles that solve the (2N+1) SHE-PWM problem. Consequently, the search process is simplified and optimized. Furthermore, this paper also proposes a circulating current control technique, which can be applied along with (2N+1) SHE-PWM without disturbing the phase output voltage. Simulation results and experimental tests obtained with a single-phase laboratory prototype prove the validity of the novel (2N+1) SHE-PWM implementation method and the proposed circulating current control technique. [ABSTRACT FROM PUBLISHER]

The paper proposes a method of active switching harmonics current reduction in the dc-link capacitor of a two-level, three-phase, back-to-back converter. Based on the derived analytical solution for switching harmonic currents in the dc-link, it is shown that by specific control over the pulsewidth-modulated (PWM) carriers’ phase angles, the targeted harmonics of the rectifier and the inverter can be synchronized in phase such that their cancellation occurs in the dc-link capacitor. This synchronization is provided by harmonic phase feedback control. A three-step procedure to implement the method is detailed in the paper. The effectiveness of the proposed approach is verified experimentally. [ABSTRACT FROM AUTHOR]

Many publications have been presented on the modulation and control of the modular multilevel converter, some of which are based on phase-shifted carrier modulation. This paper presents an analysis of how the switching frequency affects the capacitor voltages, circulating currents, and alternating voltages using phase-shifted carrier modulation. It is found that switching frequencies that are integer multiples of the fundamental frequency should be avoided as they can cause the capacitor voltages to diverge. Suitable switching frequencies are derived for which the arm and line quantities will be periodic with symmetric operating conditions in the upper and lower arms. Thus, the practical outcome of this paper is a detailed description of how the switching frequency should be chosen in order to achieve advantageous operating conditions. The theoretical results from the analysis are validated by both simulations and experimental results. [ABSTRACT FROM AUTHOR]

This paper proposes a multilevel shunt active power filter (SAPF) to deal with either harmonic current compensation or reactive power compensation. Such a device can reduce the harmonic distortion at the grid currents provided by nonlinear loads located in stiff systems. The proposed SAPF is based on three-phase bridge converters connected to cascaded single-phase transformers. The transformer arrangement permits the compensator to use a single dc-link unit, which simplifies the control strategy and the number of sensors. The multilevel waveforms are generated by using a suitable pulse-width modulation (PWM) strategy associated with the transformer turns ratio. Modularity and simple maintenance make the proposed SAPF an attractive solution compared with some conventional configurations. The model, the PWM technique, and the control strategy are presented, as well as studies considering harmonic distortion and semiconductor losses estimation. Simulation and experimental results are presented in order to validate theoretical approaches. [ABSTRACT FROM AUTHOR]

The Z-source inverter (ZSI) employs an LC impedance network between the main inverter bridge and the power source. The unique feature of the ZSI is that it can operate either in buck or boost mode with a wide range of obtainable output voltages from a given input voltage. This topology also exhibits better electromagnetic-interference noise immunity when compared to a traditional voltage-source inverter (VSI). However, the LC impedance network of ZSI significantly increases the size and cost of the power converter and can make it unsuitable for low-power applications. This paper proposes a novel topology called switched boost inverter (SBI) which exhibits similar advantages of ZSI with lower number of passive components and more active components compared to ZSI. The steady-state and small-signal analyses of SBI, along with its pulsewidth modulation (PWM) control strategies, have been discussed in this paper. This paper also presents a comparison of SBI and ZSI with the same input and output parameters. The theoretical analysis given in this paper has been validated using a laboratory prototype of SBI, and the experimental results are presented for verification. The experimental harmonic spectrum of the inverter's output voltage with the proposed PWM technique is also plotted and compared with that of a traditional VSI. All the experimental results show good correlation between theory and experiments. [ABSTRACT FROM PUBLISHER]

The main objective of this paper is to examine the operation of a fundamental buck-based three-phase single-stage ac–dc full-bridge converter. In this paper, the operation of this fundamental converter is explained and analyzed, and a procedure for the design of its key components is derived and demonstrated with an example. The performance and characteristics of the converter are shown with experimental results that have been obtained from a prototype, and general concluding remarks comparing buck-based and boost-based three-phase single-stage ac–dc full-bridge converters are made. [ABSTRACT FROM PUBLISHER]

During the design phase of a modular multilevel converter (MMC), an accurate loss evaluation of the submodule (SM) plays an important role. In this paper, a method based on the analytical description of the MMC key waveforms that allows to directly obtain the average semiconductor and capacitor losses that each SM will experience is introduced, under different operating conditions or control schemes. To verify the proposed concept, the results are compared with the losses obtained from a switched model with closed-loop control, where the analytical MMC key waveforms are approached in steady state. The proposed method provides a great flexibility and a significant reduction of the simulation/computational time otherwise needed to evaluate SM losses under various operating conditions. [ABSTRACT FROM PUBLISHER]

This paper addresses the inverter nonlinearity of a three-level T-type inverter. The main causes of the nonlinearity are pulse shaping, pulse skipping due to narrow pulses for the dead time, and voltage drop of the switching devices. Although the same causes have existed in two-level inverters, the pulse skipping phenomenon and results are quite different in the case of the three-level T-type inverter. The effects of pulse shaping and skipping have been investigated and discussed. In addition, the voltage drop of the switching devices has been considered in conjunction with the conduction path of the T-type inverter. Compensation methods based on the pulse width modulation (PWM) of T-type inverter to alleviate the inverter nonlinearity have been proposed from research results. The proposed methods could be easily implemented by adding appropriate offset voltages to the voltage references of the inverter in PWM. Furthermore, a neutral voltage balancing method of a three-level T-type inverter has been proposed in conjunction with the proposed PWM methods using offset voltage. Through extensive experimental tests, the fifth- and seventh-harmonic components of the current are conspicuously reduced along with the even harmonics. The neutral voltage of the inverter can be balanced effectively with the proposed offset voltage adjustments as well. [ABSTRACT FROM AUTHOR]

In this paper, the near-state pulse width modulation (NSPWM), adapted to be used in dual-voltage source inverter (VSI) fed open-end load, is introduced primarily aiming to appreciably minimize the voltage total harmonic distortion (THD). Within the framework of the proposed method, the active time of pulses at the second inverter is relatively adjusted within switching interval (compared to the first VSI). The phase voltage harmonics are formulated for dual-inverter modulated by NSPWM; then, optimal adjustment is identified via a three-dimensional curve of phase voltage THD versus modulation index (MI) and phase angle displacement (PAD). Due to the limitation of MI in NSPWM, the desired output voltage is synthesized with modifying not only MI but also PAD between references of two VSIs. Furthermore, NSPWM inherently takes advantage of better efficiency compared to conventional space vector modulation due to switching only two phases within an interval (by clamping one phase to positive/negative dc-rail). The dual-VSI supplied by two isolated dc sources is assembled in the laboratory to experimentally evaluate the THD reduction feature of the proposed method; also, the simulation results obtained by means of a MATLAB/Simulink environment show close agreement with experimental data. [ABSTRACT FROM PUBLISHER]

Multilevel active neutral-point-clamped (ANPC) converter is popularly known for its higher medium voltage drives up to 6.9 kV. However, common-mode voltages (CMV) are generated when using the well-established carrier-based pulse width modulation (PWM) modulation technique. As a result, CMV will become the major cause of the premature bearing failures and the conducted electromagnetic interferences. In this paper, a reduced CMV strategy is proposed for the ANPC which employs an alternatively new hybrid carrier-based modulation named as interleaved sawtooth carrier phase-disposition PWM (ISC-PD-PWM). By doing so, enhanced harmonic profile is achieved as compared to the typically used classical phase-shifted carrier PWM (PSC-PWM). Therefore, a comparative evaluation of the seven-level (7L) ANPC performance using the proposed reduced CMV approach is made between the novel hybrid ISC-PD-PWM and the conventional PSC-PWM in terms of harmonic analysis. The experimental results have proven the feasibility of the proposed concepts with the CMV effectively reduced. Such perceived merits make ANPC be more attractive for its motor drives. [ABSTRACT FROM AUTHOR]

Although the dc/dc converter as a common power supply is compatible with the electromagnetic compatibility standard, it may still bring the peak interference generated from one nonlinear load to the other loads. In this paper, a novel filter is designed in a low-voltage buck converter to suppress some extra peak harmonics generated from a nonlinear load, i.e., a pulse width modulation switching circuit. This filter is a variable capacitance filter (VCF) whose active devices are working in the linear areas. The capacitance of the filter is controlled to vary with the change of the switching load's carrier-frequency in the scheme. The impedance of the VCF can not only be matched with the switching load, but also avoid the mismatch effect from the parameter drift caused by the aging of the components. Thus, the VCF can suppress the introductive peak harmonics from the switching load at its carrier-frequency, especially the peak harmonics in the carrier-frequency region when the carrier-frequency modulation is used as the control strategy in the switching load. The feasibility and validity of the VCF are proved by simulations and experiments in a low-voltage buck converter, in which a boost circuit is working as one of its loads. [ABSTRACT FROM AUTHOR]

Multimodule converter-based high-voltage dc (HVDC) power transmission incorporates numerous voltage-source converters (VSCs) connected in series/parallel to provide increased voltage/current and, hence, power ratings. When a selective harmonic elimination pulsewidth-modulation (SHE-PWM) technique is employed, the switching losses of the VSC modules are reduced but the voltages of the series-connected dc capacitors are not naturally balanced. In this paper, a voltage-balancing technique is reported. The technique relies on monitoring the voltage of each dc capacitor and when such voltage exceeds its preset band, the realization of the multilevel waveform reallocates the task to another VSC module to ensure that voltage balance between all capacitors is achieved. Three-phase bipolar VSC modules are considered in this paper and each one is modulated by a precalculated multilevel SHE-PWM waveform. The time-domain waveforms and their line-to-line voltage spectra are verified by simulation using PSCAD/EMTDC. The selected results are presented to confirm the viability of the proposed method. [ABSTRACT FROM PUBLISHER]

In this paper, a new inverter topology is proposed for generating a multilevel dodecagonal voltage space vector structure for open-end winding induction motor (IM) using a single dc source. Dodecagonal voltage space vector structure eliminates fifth- and seventh-order harmonic voltages from phase voltage output and hence eliminates the fifth- and seventh-order harmonic currents through the motor leading to removal of the dominant sixth-order torque ripple generation in the motor over the entire modulation range. Multilevel space vector structure generates output voltage with better THD and low dv/dt. In the proposed topology, two three-level inverters drive an open-end winding IM, one inverter from each side. DC-link of primary inverter is from a dc source which delivers the entire active power, whereas the secondary inverter dc-link is maintained by a capacitor, which is self balanced during the inverter operation. The PWM scheme implemented ensures low switching frequency for primary inverter. Secondary inverter operates at a small dc-link voltage. Hence, switching losses are small for both primary and secondary inverters. Experimental results show the elimination of fifth- and seventh-order harmonic voltages over the entire modulation range, validating effectiveness of the proposed multilevel inverter scheme. [ABSTRACT FROM PUBLISHER]

This paper provides theoretical and experimental discussions on an optimal carrier frequency for a phase-shifted pulsewidth modulation modular multilevel cascade converter for grid connections. The theoretical discussion concludes that a ratio of the optimal carrier frequency with respect to the supply (ac) frequency is 5/2. A three-phase downscaled front-to-front system is designed, constructed, and tested to confirm validity of the theoretical discussion. It consists of a pair of three-phase modular multilevel cascade converters rated at 400 Vdc and 10 kW, where the carrier frequency is set to 450 Hz and the ac frequency to 180 Hz, that is, their ratio is equal to 5/2. Moreover, simulated waveforms are compared to experimental ones under the same operating conditions. Both experimental and simulated waveforms agree well with each other not only in steady states but also in transient states. [ABSTRACT FROM AUTHOR]

The three-phase series-connected modular multilevel converter (SC-MMC) is presented as one option for high-voltage direct current (HVDC) tap to reduce the cost of an HVDC station. Compared with conventional three-phase parallel-connected MMC, the number of semiconductor switches in SC-MMC is reduced by one-third to withstand the same dc voltage. First, the paper studies the operating principle of SC-MMC, and then presents an interspacing phase-shifted pulsewidth-modulated method which could improve the waveform of the output ac voltage for a given switching frequency. Next, the control strategy based on the identical real power input of each phase is proposed to balance the dc voltage of each phase under an unbalanced grid condition. The current limit of switching devices is also taken into consideration to protect SC-MMC from overcurrent. Furthermore, a universal zero-sequence current controller is developed as one part of the control strategy. In addition, an innovative method to suppress the third harmonics of ac current is presented. With the third harmonic suppression strategy, the SC-MMC can operate with much smaller SM capacitors without deteriorating the ac current, which contributes to the cost reduction further. Finally, simulation results obtained in PSCAD/EMTDC are provided to validate the proposed control strategies. [ABSTRACT FROM PUBLISHER]

This paper proposes a resonant dual-active bridge (DAB) converter, which uses a tuned capacitor–inductor–capacitor network. In comparison to the conventional DABs, the proposed topology significantly reduces the bridge currents, lowering both conduction and switching losses and improving the bridge power factors. A mathematical model, which predicts the behavior of the proposed system, is presented to show that both the magnitude and direction of the power flow can be controlled through either relative phase angle or pulse width modulation of voltages produced by the bridges. The viability of the proposed concept is verified through simulation. Experimental results of a 4- kW prototype converter, which has an efficiency of 95% at rated power, are also presented with discussions to demonstrate the improved performance of this topology. [ABSTRACT FROM AUTHOR]

In this paper, a multilevel dodecagonal voltage space vector structure with nineteen concentric dodecagons is proposed for the first time. This space vector structure is achieved by cascading two sets of asymmetric three-level inverters with isolated H-bridges on either side of an open-end winding induction motor. The dodecagonal structure is made possible by proper selection of dc link voltages and switching states of the inverters. The proposed scheme retains all the advantages of multilevel topologies as well as the advantages of dodecagonal voltage space vector structure. In addition to that, a generic and simple method for calculation of pulsewidth modulation timings using only sampled reference values ( $v_\alpha$ and $v_\beta$) is proposed. This enables the scheme to be used for any closed-loop application such as vector control. In addition, a new method of switching technique is proposed, which ensures minimum switching while eliminating the fifth- and seventh-order harmonics and suppressing the eleventh and thirteenth harmonics, eliminating the need for bulky filters. The motor phase voltage is a 24-stepped waveform for the entire modulation range thereby reducing the number of switchings of the individual inverter modules. Experimental results for steady-state operation, transient operation, including start-up have been presented and the results of fast Fourier transform analysis is also presented for validating the proposed concept. [ABSTRACT FROM PUBLISHER]

In this paper, an analysis and calculation of the dc-link current and voltage ripples are presented for a three-phase inverter with unbalanced load. A comparison of the dc-link average and root-mean-square (rms) currents between considering and ignoring high frequency harmonics of the output current is drawn. It is shown that high frequency harmonic currents have little effect on the dc-link current, and therefore, they can be ignored. Based on the symmetrical components method, the dc-link average and harmonic rms currents are derived, and the dc-link voltage ripple is compared between the balanced and unbalanced loads. It can be found that the dc-link current and voltage ripples consist of not only high frequency harmonics but also the double fundamental frequency harmonic, and the voltage ripple is independent of the positive-sequence component and determined by the negative-sequence component, under the unbalanced load. Experimental results are shown to verify the accuracy of the theoretical analysis. [ABSTRACT FROM AUTHOR]

This paper proposes a technique to suppress low-order harmonics for an open-end winding induction motor drive for a full modulation range. One side of the machine is connected to a main inverter with a dc power supply, whereas the other inverter is connected to a capacitor from the other side. Harmonic suppression (with complete elimination of fifth- and seventh-order harmonics) is achieved by realizing dodecagonal space vectors using a combined pulsewidth modulation (PWM) control for the two inverters. The floating capacitor voltage is inherently controlled during the PWM operation. The proposed PWM technique is shown to be valid for the entire modulation range, including overmodulation and six-step mode of operation of the main inverter. Experimental results have been presented to validate the proposed technique. [ABSTRACT FROM PUBLISHER]

This paper presents input-series–output-parallel (ISOP) configuration for single-phase front-end buck rectifiers (BRs). The configuration is especially suitable for traction applications, where the complete rectification system needs to withstand high ac voltages and supply medium-power loads. The primary rectification module of the proposed configuration is based on pulsewidth-modulated BR (current source inverter topology). The desired isolation, mandatory for ISOP connection, is provided at the dc stage through a medium-frequency/high-frequency transformer. Equal power sharing by modules is achieved from the ac side through input voltage and current sharing. The proposed control scheme is configured using two loops. While the outer loop regulates the output dc voltage and active wave shaping of the source current, the inner loop ensures stable voltage sharing. The performance of the proposed ISOP configuration is verified using numerical simulation. Experimental verification is achieved through a 2-kW grid-connected laboratory prototype. [ABSTRACT FROM PUBLISHER]

In this paper, a generalized switching technique for cascaded H -bridge (CHB) converters is proposed. To take advantage of both low- and high-frequency modulation techniques, a hybrid modulation method is utilized. The proposed technique employs the low-frequency switching for voltage balancing of the dc-link capacitors, and the high-frequency sinusoidal pulse-width modulation switching for shaping the input ac current. Using the proposed technique, the stable operating region of CHB converters is extended. The proposed technique is capable of maintaining the dc voltages balanced even under critical operating conditions in which the load of one H-bridge cell is removed. The validity and effectiveness of the proposed method is confirmed by several simulation and experimental tests on a seven-level CHB rectifier. [ABSTRACT FROM AUTHOR]

This paper presents the hybrid seven-level cascaded active neutral-point-clamped (ANPC)-based multilevel converter. The converter topology is the cascaded connection of a three-level ANPC converter and an H-bridge per phase. The voltage of the H-bridge is actively maintained to the required level through selection of the switching states of the converter. The topology is operated under selective harmonic elimination pulsewidth modulation (SHE-PWM), maintaining the switching frequency of the converter to a minimum. The operating principles, voltage balancing methods, and limitations of the converter are analyzed together with extensive simulation results of the topology. Experimental results from a low-power laboratory prototype are presented that verify the operation of the hybrid converter under SHE-PWM. [ABSTRACT FROM PUBLISHER]

Cascaded H-bridge multilevel power electronic converters generally require several dc sources. An alternative option is to replace all the separate dc sources feeding the H-bridge cells with capacitors, leaving only one H-bridge cell with a real dc voltage source. This will yield a cost-effective converter. However, the required capacitor voltage balancing is challenging. In this paper, using the phase-shift modulation approach, a new control method for cascaded H-bridge multilevel converters fed with only one independent dc source is presented. The proposed method has a wide voltage regulation range for the replacement capacitors in the H-bridge cells. Experimental and simulation results support the proposed control method. [ABSTRACT FROM PUBLISHER]

This paper presents a three-phase cascaded multilevel inverter that uses five-level transistor-clamped H-bridge power cells. Multicarrier phase-shifted pulse-width modulation method is used to achieve balanced power distribution among the power cells. A new method to balance the midpoint capacitor voltage in each cell is developed and tested. The analysis of the output voltage harmonics and the total power losses covering the conduction and the switching power losses are carried out and compared with the cascaded neutral-point-clamped and the conventional cascaded H-bridge inverters. For verifications, the proposed inverter is experimentally tested on an induction motor. From the results, the proposed inverter provides higher output quality with relatively lower power loss as compared to the other conventional inverters with the same output quality. [ABSTRACT FROM PUBLISHER]

Dodecagonal (12-sided) space vector pulsewidth modulation (PWM) schemes are characterized by the complete absence of (6n ± 1)th-order harmonics (for odd n) in the phase voltages, within the linear modulation range and beyond, including overmodulation. This paper presents a new topology suitable for the realization of such multilevel inverter schemes for induction motor (IM) drives, by cascading two-level inverters with flying-capacitor-inverter fed floating H-bridge cells. Now, any standard IM may be used to get the dodecagonal operation which hitherto was possible only with open-end winding IM. To minimize the current total harmonic distortion (THD), a strategy for synchronous PWM is also proposed. It is shown that the proposed method is capable of obtaining better THD figures, compared to conventional dodecagonal schemes. The topology and the PWM strategy are validated through analysis and subsequently verified experimentally. [ABSTRACT FROM AUTHOR]

This paper further develops a model predictive control (MPC) scheme which is able to exploit the large number of redundant switching states available in a multilevel H-bridge StatCom (H-StatCom). The new sections of the scheme provide optimized methods to tradeoff the harmonic performance with converter switching losses and capacitor voltage ripple. Varying the pulse placement within the modulation scheme and modifying the heuristic model of the voltage balancing characteristics allows the MPC scheme to achieve superior performance to that of the industry standard phase shifted carrier modulation technique. The effects of capacitor voltage ripple on the lifetime of the capacitors are also investigated. It is shown that the MPC scheme can reduce capacitor voltage ripple and increase capacitor lifetime. Simulation and experimental results are presented that confirm the correct operation of the control and modulation strategies. [ABSTRACT FROM PUBLISHER]

This paper presents a multilevel inverter topology suitable for the generation of dodecagonal space vectors instead of hexagonal space vectors as in the case of conventional schemes. This feature eliminates all the 6n ± 1 (n = odd ) harmonics from the phase voltages and currents in the entire modulation range with an increase in the linear modulation range. The topology is realized by flying capacitor-based three-level inverters feeding from two ends of an open-end winding induction motor with asymmetric dc links. The flying capacitor voltages are tightly controlled throughout the modulation range using redundant switching states for any load power factor. A simple and fast carrier-based space-vector pulsewidth modulation (PWM) scheme is also proposed for the topology which utilizes only the sampled amplitudes of the reference wave for the PWM timing computation. [ABSTRACT FROM AUTHOR]

A modified single-phase quasi-Z-source ac-ac converter is proposed in this paper. The proposed converter has the main features in that the output voltage can be bucked or boosted and be both in-phase and out-of-phase with the input voltage. The input voltage and output voltage share the same ground, the size of a converter is reduced, and it operates in a continuous current mode. A safe-commutation strategy for the modified single-phase quasi-Z-source ac-ac converter is used instead of a snubber circuit. The operating principles and a steady-state analysis are presented. A laboratory prototype, tested using a resistive load, a passive load, and a nonlinear load, was constructed that used an input voltage of 70 Vrms /60 Hz in order to verify the performance of the modified single-phase quasi-Z-source ac-ac converter. The experimental results verified that the converter has a lower input current total harmonic distortion, a higher input power factor, and a higher efficiency in comparison to a conventional single-phase Z-source ac-ac converter. In addition, the experimental results show that the use of the safe-commutation strategy is a significant improvement, as it makes it possible to avoid voltage spikes on the switches. [ABSTRACT FROM AUTHOR]

A five-level flying-capacitor (FC)-based active-neutral-point-clamped (ANPC) converter is an arrangement of a three-level ANPC converter and a two-level cell. In this paper, a control strategy is proposed to regulate the voltage across the FCs at their respective reference voltage levels by swapping the switching patterns of the switches based on the polarity of the output current, the polarity of the FC voltage, and the polarity of the fundamental line-to-neutral voltage under selective harmonic elimination pulsewidth modulation. The voltage across the FCs and the dc-link capacitors are simultaneously controlled at their reference voltage levels. The proposed control strategy is applied using power system computer aided design/electromagnetic transients including dc on a static synchronous compensator operating under a power-factor-correction mode to verify its performance. Experimental results are also presented for low and high number of angles per quarter period using a low-power laboratory prototype. [ABSTRACT FROM AUTHOR]

This paper presents a comprehensive analytical investigation of the four-switch three-phase (B4) voltage source inverter. The double Fourier integral analysis is used as an analytical approach to determine the phase-leg switched voltage spectrum under condition of natural sampling. The performance of two proposed switching sequences are subsequently evaluated when the harmonic copper losses are chosen as performance criterion. For a clear identification of dc-link voltage, the spectrum of dc-link current is characterized by convolution of switching function spectrum and corresponding phase current spectrum, in which fundamental component appears causing offset and fluctuation in dc-link two-capacitor voltages. The offset can be suppressed by certain switching states, whereas the effect of fluctuation must be neutralized through analytical compensation for modulating waveforms. Otherwise, symmetry of three-phase output currents and reliable operation of the system will not be retained. Finally, the analytically calculated spectrum of output voltage and dc-link current are demonstrated by comparing with those obtained by fast Fourier transform (FFT) analysis of simulated waveforms in MATLAB/SIMULINK. The capacitor voltage offset suppression and fluctuation effect neutralization are carried out by simulations and experiments, in which the results confirm the validity of the analytical investigation. [ABSTRACT FROM AUTHOR]

This paper analyses the natural voltage-balancing characteristic of a three-phase flying capacitor multilevel converter when it is operated under the spectrally optimal Phase Disposition (PD) pulsewidth modulation (PWM) strategy. Using this analysis, it is shown that PD PWM has superior balancing characteristics compared to the phase-shifted carrier PWM strategy, because it places more spectral energy into the differential-mode sideband harmonics that drive the voltage-balancing process. From this understanding, an alternative balance booster filter network connection is proposed that significantly improves the natural balancing response of a flying capacitor converter for either PWM strategy. The analysis is confirmed by extensive simulation and experimental studies. [ABSTRACT FROM AUTHOR]

This paper presents a complete analysis of studying the impact of interleaving on the ripple current in the dc-side passive components of paralleled three-phase voltage-source converters (VSCs). The analysis considers the effects of different pulsewidth modulation scheme, the modulation index, the interleaving angle, and the power factor or displacement angle. In the analysis, the rms value of the total ripple current in the dc-side is used as figure of merit and calculated in the frequency domain. The results obtained show that all of the factors considered can strongly affect the rms value one way or another. Based on the analysis, the interleaving angle-optimization method is shown to minimize the rms in different cases. The effect of circulating currents on the ripple currents in the dc-side passive components is also taken into consideration to perform a more accurate analysis. All the analysis is based on an example system containing two VSCs, but the proposed analysis method in the frequency domain can be easily expandable for multiple paralleled VSCs. Experimental results are used to verify the analysis conducted. [ABSTRACT FROM AUTHOR]

This paper presents a neutral point voltage control strategy for the three-level active neutral point clamped (ANPC) converter using selective harmonic elimination pulsewidth modulation (SHE-PWM). The control strategy introduces a small change in the switching angles, which varies the duty cycle of the zero-level switching state, controls the neutral point current and, therefore, the neutral point voltage. The decision to vary a given switching angle takes into account the polarity of the output currents and the voltage across the lower dc-link capacitor. The effectiveness of the proposed strategy is verified through extensive simulation studies and experimentally validated using a low power laboratory prototype. [ABSTRACT FROM AUTHOR]

Presents a comments on the paper, "Nearest and non-nearest three vector modulations of NPCI using two-level space vector diagram - a novel approach," (Babu, N. and Agarwal, P.), IEEE Trans. Ind. Electron., vol. 60, no. 5, pp. 1999-2009, 2013. [ABSTRACT FROM AUTHOR]