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The novel multilevel circuit topologies are proposed in this paper. They are called multilevel circuit topologies based on switched-capacitor and diode-clamped converters (MCT-BSD). The topology structure and the operation principle, including the working states’ transitions of the diode-clamped part, the voltages balancing mechanism of the dc link capacitors, and the pulse width modulated carrier control strategy are given. The switched-capacitor circuits contribute not only to balancing the voltages of capacitors but also to boosting the output voltage with a certain input dc voltage. The validity of the MCT-BSD is verified by simulations and experiments. The results show that balancing the voltages of capacitors, boosting the output voltages, and operating under the three-phase condition are all realized effectively in the MCT-BSD. The simulations also show the generalization of the MCT-BSD for n-level topologies. [ABSTRACT FROM AUTHOR]

This paper analyses the natural voltage-balancing characteristic of a three-phase flying capacitor multilevel converter when it is operated under the spectrally optimal Phase Disposition (PD) pulsewidth modulation (PWM) strategy. Using this analysis, it is shown that PD PWM has superior balancing characteristics compared to the phase-shifted carrier PWM strategy, because it places more spectral energy into the differential-mode sideband harmonics that drive the voltage-balancing process. From this understanding, an alternative balance booster filter network connection is proposed that significantly improves the natural balancing response of a flying capacitor converter for either PWM strategy. The analysis is confirmed by extensive simulation and experimental studies. [ABSTRACT FROM AUTHOR]

The flying capacitor multicell inverter (FCMI) possesses natural balancing property. With the phase-shifted carrier-based scheme, natural balancing can be achieved in a straightforward manner. However, to achieve natural balancing with the harmonically optimal phase-disposition (PD) carrier-based scheme, the conventional approaches require (n − 1) × (n − 1) trapezoidal carrier signals for an n-level inverter, which is ( n − 1) × (n − 2) times more than that in the standard PD scheme. This paper proposes two improved natural balancing strategies for FCMI under PD scheme, which use the same (n − 1) carrier signals as used in the standard PD scheme. In the first scheme, the on-line detections are performed of (i) the band in which the modulation signal is located, (ii) corresponding period number of the carrier, and (iii) rising or falling half cycle of the carrier waveform to generate the switching signals based on certain rules. In the second strategy, the output voltage level selection is first processed and the switching signals are then generated according to a rule based on preferential cell selection algorithm. These methods are easy to use and can be simply implemented as compared to the other available methods. Simulation and experimental results are presented for a five-level inverter to verify these proposed schemes. [ABSTRACT FROM AUTHOR]

This paper presents a complete analysis of studying the impact of interleaving on the ripple current in the dc-side passive components of paralleled three-phase voltage-source converters (VSCs). The analysis considers the effects of different pulsewidth modulation scheme, the modulation index, the interleaving angle, and the power factor or displacement angle. In the analysis, the rms value of the total ripple current in the dc-side is used as figure of merit and calculated in the frequency domain. The results obtained show that all of the factors considered can strongly affect the rms value one way or another. Based on the analysis, the interleaving angle-optimization method is shown to minimize the rms in different cases. The effect of circulating currents on the ripple currents in the dc-side passive components is also taken into consideration to perform a more accurate analysis. All the analysis is based on an example system containing two VSCs, but the proposed analysis method in the frequency domain can be easily expandable for multiple paralleled VSCs. Experimental results are used to verify the analysis conducted. [ABSTRACT FROM AUTHOR]

Unipolar sinusoidal pulsewidth modulation (SPWM) full-bridge inverter brings high-frequency common-mode voltage, which restricts its application in transformerless photovoltaic grid-connected inverters. In order to solve this problem, an optimized full-bridge structure with two additional switches and a capacitor divider is proposed in this paper, which guarantees that a freewheeling path is clamped to half input voltage in the freewheeling period. Sequentially, the high-frequency common-mode voltage has been avoided in the unipolar SPWM full-bridge inverter, and the output current flows through only three switches in the power processing period. In addition, a clamping branch makes the voltage stress of the added switches be equal to half input voltage. The operation and clamping modes are analyzed, and the total losses of power device of several existing topologies and proposed topology are fairly calculated. Finally, the common-mode performance of these topologies is compared by a universal prototype inverter rated at 1 kW. [ABSTRACT FROM AUTHOR]

This paper presents a neutral point voltage control strategy for the three-level active neutral point clamped (ANPC) converter using selective harmonic elimination pulsewidth modulation (SHE-PWM). The control strategy introduces a small change in the switching angles, which varies the duty cycle of the zero-level switching state, controls the neutral point current and, therefore, the neutral point voltage. The decision to vary a given switching angle takes into account the polarity of the output currents and the voltage across the lower dc-link capacitor. The effectiveness of the proposed strategy is verified through extensive simulation studies and experimentally validated using a low power laboratory prototype. [ABSTRACT FROM AUTHOR]

In this paper, a three-level three-leg ac–dc–ac converter for single-phase applications is investigated. The operating principles and control strategies for the topology are presented. It is shown that dc-link voltage balancing and its reduction are important objectives in the system design. The proposed pulsewidth modulation (PWM) strategy permits the dc-link capacitor voltage balance and also its reduction. The three-level converter is compared to the two-level converter in terms of rms switch currents, harmonic distortion, losses, and costs. Experimental and simulation results are presented to validate the theoretical studies. [ABSTRACT FROM PUBLISHER]

This paper proposes a zero-voltage-transition (ZVT) pulsewidth-modulated (PWM) synchronous buck converter, which is designed to operate at low voltage and high efficiency typically required for portable systems. A new passive auxiliary circuit that allows the main switch to operate with zero-voltage switching has been incorporated in the conventional PWM synchronous buck converter. The operation principles and detailed steady-state analysis of the ZVT PWM synchronous converter with a passive auxiliary circuit are presented. All of the semiconductor devices aside from the main switch operate under soft-switching conditions. Thus, the auxiliary circuit provides a larger overall efficiency. The feasibility of the auxiliary circuit is confirmed by the simulation and experimental results. [ABSTRACT FROM PUBLISHER]

Presents a comments on the paper, "Nearest and non-nearest three vector modulations of NPCI using two-level space vector diagram - a novel approach," (Babu, N. and Agarwal, P.), IEEE Trans. Ind. Electron., vol. 60, no. 5, pp. 1999-2009, 2013. [ABSTRACT FROM AUTHOR]

Capacitor charging power supply (CCPS) is a developed technology that utilizes resonant converters topology for high power applications. This paper proposes new a capacitor charging power supply using leg-rotation control method within a phase-shifted PWM full-bridge dc/dc converter. The capacitor charging power supply was connected in series to increase output voltage. Also, the proposed system is designed with soft switching techniques in order to achieve high efficiency, and a leg-rotation control method was used to reduce the heat generated from the IGBTs. The operation of the converter and design methodology will be described. A simplified model of a high-voltage high-frequency transformer is given and the structure is designed to decrease high-voltage stress. The validity of the proposed system is then verified by experimental results. The performance test of the capacitor charging power supply was carried out with a 2 μF capacitive load with a 20 kV output voltage. [ABSTRACT FROM AUTHOR]

This paper describes the design of a compact and highly repetitive pulsed power modulator based on semiconductor switches. Output specifications of the proposed modulator are as follows: variable output pulse voltage, 1-10 kV; width, 1-10 μs; pulse repetition rate (PRR), 1-50,000 pps; and average output power, 10 kW. The proposed solid-state pulsed power modulator has two main parts: an IGBT stack that hasa gate drive circuit for the pulse output with a variable pulse width and repetition rate, and a capacitor charger that has a controllable output voltage. To connect all the storage capacitors in a series for high voltage pulses, a simple and reliable IGBT stack structure was proposed based on the Marx generator. In addition, the gate driver circuit, which supplies power and signals to all the IGBTs simultaneously, was introduced. This providesa superior protection function against the arc and the short. To charge the storage capacitors, a novel 10 kW (10 kV, 1 A) high voltage capacitor charger with the combined advantageof a series-loaded resonant converter and a ZVS (zero-voltage-switching) full-bridge pulse width modulation (PWM) converter was proposed and designed especially for the solid-state pulsed power modulator. Theexperiment results verified that the proposed scheme and structure can be used effectively for a high voltage pulsed power modulator that requires variable voltage, repetition rate, and pulse width, depending on the process of the applications. [ABSTRACT FROM AUTHOR]