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Enhancement of dc bus voltage utilization for a five-level inverter with single dc source and capacitor-fed H-bridge (CHB) units is investigated in this paper. A carrier-based modulation technique is used for boosting the dc bus utilization, which is established by providing detailed mathematical analysis. The five-level inverter used here is realized by cascading a CHB unit to each phase of a three-level neutral point clamped inverter. The increase in dc bus voltage utilization owes to the pole voltage redundancies offered by CHB units. The floating capacitors of H-bridge units are balanced within a quarter fundamental cycle using the switching state redundancies of pole voltage levels. The aforementioned modulation technique allows the inverter to enhance the dc bus utilization from 0.577 $\text{V}_{\text{dc}}$ to 0.63 $\text{V}_{\text{dc}}$ under unity power factor. This enhancement is obtained in the linear modulation range without increasing the dc bus voltage, and thus, the inverter can operate without the presence of low-order harmonics in its phase voltages. The strength of this paper lies in its detailed mathematical analysis for finding out the limiting modulation index and power factor condition in the light of floating capacitor voltage balancing issue. Simulation as well as experimental verification of the modulation scheme is carried out on an induction motor drive under various operating conditions. It is shown that this carrier-based modulation technique is suitable for any single source inverter topology with one CHB unit per phase. [ABSTRACT FROM AUTHOR]

To support the development of high-frequency ac microgrids in terms of compact design, high-voltage gain and low total harmonic distortion (THD), a buck–boost dual-leg-integrated step-up inverter is proposed in this paper. The inverter is formed by integrating a buck–boost converter into a conventional single-phase full-bridge inverter by sharing the upper switch and the body diode of the lower switch in both bridge-legs. Consequently, the component count is significantly reduced over the step-up inverter counterparts. In addition, to address the drawbacks of hybrid modulation methods adopted by existing dual-leg-integrated inverters, such as double-variable control, and high THD of output voltage/current at high input voltage and heavy load conditions, unipolar frequency doubling sinusoidal pulse width modulation scheme is adopted in this inverter. As a result, the modulation ratio M becomes the only control variable to regulate the output voltage/current and the control is simplified. The THD of the proposed inverter output can remain low throughout the entire input voltage range and load power range. This paper presents the topology derivation procedure, operation principle, and steady-state characteristics of the proposed inverter. To validate the effectiveness of theory, experimental results of a 400 W hardware prototype, where the output voltage frequency is at 500 Hz, are reported. [ABSTRACT FROM PUBLISHER]

This paper proposes a current-fed single-phase inverter without constant intermediate DC link. It eliminates electrolytic capacitor from the DC-link and introduces an intermediate pulsating DC bus. The proposed topology is modular with three full-bridges making it scalable for high-power applications. New pulsating-DC-modulation for back-end pulsating DC-link inverter and secondary modulation (SM) for front-end DC-to-pulsating DC converter is proposed. Soft-switching and device voltage clamping of both primary side and secondary side devices of front-end current-fed full-bridge converter is realized. A rotating partial hybrid pulsewidth modulation has been introduced. One leg of inverter is commutated at a low switching frequency, while the other leg is operated at a high switching frequency for partial period of a line frequency cycle. Thus, switching losses of the back-end inverter are considerably reduced. Rotating mechanism is used to equalize the switching losses of four switches of the inverter. This paper presents detailed operation and analysis of the topology with a proposed modulation scheme. Simulation and experimental results validate the effectiveness and accuracy of the proposed modulation scheme as well as soft-switching and performance of the converter. [ABSTRACT FROM PUBLISHER]

This paper proposes a new inverter topology based on the active neutral-point-clamped (ANPC) converter with capability to integrate one energy storage system (ESS) per inverter leg with an independent state of charge control, so that each inverter leg has two dc ports and one ac port. The primary dc port is common to all inverter legs and it is connected to the main power source. The secondary dc port is suitable for ESS connection because of its two-quadrant operation, with bidirectional current capability, so that the ESS can be charged and discharged with regulated current. Integration of a secondary dc port with independent control also allows the use of different ESS technologies for each inverter leg to compose a hybrid ESS. Redundant switching states of the proposed structure are used to balance the energy exchanged between the secondary dc port and the dc bus capacitors. Theoretical propositions were experimentally validated through a 1-kW single-phase inverter with a secondary dc port connected to a 230-V ESS and ac port connected to an LC filter feeding a linear load. Low total harmonic distortion (THD) sinusoidal current is generated at the ac port while charging or discharging the ESS with a constant current. [ABSTRACT FROM AUTHOR]

Three-level inverter has an outstanding performance and is more advantageous in the switching vector selection than two-level inverter. In particular, the neutral-point voltage unbalance and common-mode voltage (CMV) reduction of three-level inverter should be carefully regulated for the appropriate operation, both of which, however, are mutually coupled resulting that the conventional space vector modulation (SVM) scheme cannot deal with them properly. To overcome this limitation, this paper proposes an improved space vector modulation (ISVM) technique to reduce the CMV and neutral-point voltage imbalance simultaneously. The generating mechanism of neutral-point voltage oscillation is derived. Based on the analysis, the proposed ISVM method adopts four voltage vectors (large, medium, small, and zero vectors) with adjusted dwell times to eliminate the ac unbalance of the neutral-point voltage. Considering the occurrence of neutral-point voltage disturbances, the dc neutral-point unbalance voltage is controlled by selecting the P-type or N-type small vector and adjusting the dwell times of small vectors for neutral-point voltage recovery. In addition, a novel switching sequence arrangement method with the minimal number of switches transition in one switching cycles and between switching cycles is proposed to reduce the total switching loss. Theoretical analysis and verification results show that the proposed ISVM scheme can reduce the magnitude of CMV to half of value using the conventional SVM, and an accurate control of ac and dc unbalanced neutral-point voltage can be obtained. [ABSTRACT FROM AUTHOR]

In this paper, a new space vector pulse width modulation method to extend the linear modulation range of a cascaded five level inverter topology with a single dc supply is presented. Using this method, the inverter can be controlled linearly and the peak phase fundamental output voltage of the inverter can be increased from 0.577 to 0.637 V\text{dc} without increasing the dc bus voltage and without exceeding the induction motor voltage rating. This new technique makes use of cascaded inverter pole voltage redundancy and property of the space vector structure for its operation. Using this, the induction motor drive can be operated till the full speed range (0–50 Hz) with the elimination of lower order harmonics in the phase voltage and phase current. The five-level topology presented in this paper is realized by cascading a two-level inverter and two full bridge modules with floating capacitors. The inverter topology and its operation for extending the modulation range is analyzed extensively. Simulation and experimental results for both steady-state and dynamic operating conditions are presented in this paper. [ABSTRACT FROM AUTHOR]

Increasing demands for power supplies have contributed to the population of high-frequency ac (HFAC) power distribution system (PDS), and in order to increase the power capacity, multilevel inverters (MLIs) frequently serving as the high-frequency (HF) source-stage have obtained a prominent development. Existing MLIs commonly use more than one voltage source or a great number of power devices to enlarge the level numbers, and HF modulation (HFM) methods are usually adopted to decrease the total harmonic distortion (THD). All of these have increased the complexity and decreased the efficiency for the conversion from dc to HF ac. In this paper, a nine-level inverter employing only one input source and fewer components is proposed for HFAC PDS. It makes full use of the conversion of series and parallel connections of one voltage source and two capacitors to realize nine output levels, thus lower THD can be obtained without HFM methods. The voltage stress on power devices is relatively relieved, which has broadened its range of applications as well. Moreover, the proposed nine-level inverter is equipped with the inherent self-voltage balancing ability, thus the modulation algorithm gets simplified. The circuit structure, modulation method, capacitor calculation, loss analysis, and performance comparisons are presented in this paper, and all the superior performances of the proposed nine-level inverter are verified by simulation and experimental prototypes with rated output power of 200 W. The accordance of theoretical analysis, simulation, and experimental results confirms the feasibility of proposed nine-level inverter. [ABSTRACT FROM AUTHOR]

Aimed at the problem that the auxiliary commutation circuit (ACC) of auxiliary resonant commutated pole (ARCP) inverters has a high loss in commutation processes, this paper presents a novel modulation strategy with shunt dead time based on a double ARCP (DARCP) inverter. In comparison with the original modulation strategy, this modulation strategy cannot only achieve soft switching for all switches, but also avoid the superposition of resonance current and load current at commutation moments in double ACCs (DACCs) and make the maximum current through DACCs approximately equal to load current in commutation processes. So, the circulating current loss in DACCs and the current stress of auxiliary switches can be effectively reduced. According to the equivalent circuits in different operation modes under the novel modulation strategy, this paper analyzes the operation principle, soft-switching implementation condition, and optimal parameter design procedure of the DARCP inverter. Finally, a 10-kW–16-kHz DARCP inverter prototype with insulated gate bipolar transistor-based switches is built. Experimental results are given to demonstrate the validity and features of the DARCP inverter under the novel modulation strategy. [ABSTRACT FROM AUTHOR]

Paralleled inverters have the merits of high power rating, improved reliability, and convenient maintenance. However, zero-sequence circulating current (ZSCC) will occur and lead to current distortion and system loss. The ZSCC control is more complicated when three-level topology is utilized and paralleled number is increased. Therefore, this paper proposes a simplified ZSCC suppression scheme for multi-paralleled three-level T-type inverters (3LT2Is). A novel equivalent model is developed and the ZSCC controller based on the new model is easier to implement. Thus, the number of paralleled inverters can be increased without complicating the control scheme and the inverters could be switched on or off optionally. Besides, Feed-Forward (FF) strategy is adopted to eliminate the ZSCC spikes caused by symmetrical three-level space vector modulation. The effectiveness of the proposed control scheme is verified by both simulation and experimental results. [ABSTRACT FROM AUTHOR]

A variable switching frequency space vector modulation control method is proposed in this paper. It is used to achieve zero-voltage switching (ZVS) for two parallel 180° interleaved three-phase grid-connected voltage-source inverters at unity power factor. A wide range of ZVS can be achieved without any additional sensor, auxiliary circuit, or current zero-crossing detection circuit. The carrier wave frequency is easy to be calculated and updated with digital control. The current ripple is precisely predicted and controlled to minimize unnecessary circulation loss. The high current ripple at the inverter side can be considerably canceled by the parallel interleaved configuration. LCL filter is used to further attenuate the current ripple and improve the power quality at the grid side. The switching loss can be significantly reduced especially by using a wide bandgap device with low turn-off loss. The power density is greatly improved owing to the high switching frequency and low component parameters of the filter. A 4.5-kW simulation and experimental prototype interfacing 400 V dc with a three-phase 110-V ac grid is developed to verify the performance of the proposed control strategy. [ABSTRACT FROM AUTHOR]

SiC mosfets allow a higher frequency, lighter weight inverter over their Si counterparts for electric vehicle (EV) applications. However, using SiC-based EV traction inverters is likely to increase the shaft voltage in an ac motor drive system, which significantly affects the reliability of the system. This paper investigates the impact of high-speed switching of SiC devices and high switching frequency of SiC-based inverter on the common-mode voltage (CMV) and the shaft voltage. It is theoretically illustrated and experimentally demonstrated that the high switching frequency increases the amplitude of the shaft voltage, while the fast switching speed has limited influence on both CMV and the shaft voltage. Afterward, active zero state pulsewidth modulation (AZSPWM) and common-mode chokes are employed to mitigate the shaft voltage. The experimental results show that either the AZSPWM modulation scheme or common-mode chokes have the capability to minimize the shaft voltage. Better performance can be achieved by utilizing both techniques simultaneously. It is also observed that the high switching frequency enabled by the fast-speed SiC device is able to be helpful to the use of reduced shaft voltage technologies. [ABSTRACT FROM AUTHOR]

The leakage current originated from the fluctuations of the common-mode voltage (CMV) is an issue in a transformerless grid-connected photovoltaic system. In this paper, a modified space vector modulation based on the Fourier transform analysis is proposed to reduce the leakage current in a three-phase quasi-Z-source inverter (qZSI). The CMV harmonic content in a qZSI contains low- and high-frequency harmonics that cause safety and electromagnetic interference problems, respectively. By implementing the proposed modulation in a three-phase qZSI, the low-frequency harmonics of the CMV are mainly reduced. The distribution of the high-frequency harmonics is also modified in a way they can be simply filtered. Passive filtering in a qZSI using other modulation techniques is less effective than using this method. Applying the proposed modulation in the presence of a high-frequency inductive-capacitive filter results in the strong suppression of both high- and low-frequency harmonics (more than 90% in the investigated case). A reduced-voltage prototype is designed to evaluate the modulation method. The experimental results from this prototype verify the accuracy of the proposed technique. [ABSTRACT FROM AUTHOR]

This paper proposes a switching strategy for the Z-source inverter (ZSI), which has unequal short-through intervals to reduce the current ripple in the inductor of its impedance source. A size reduction of the inductor of the ZSI is one of the important issues in improving the power density of the ZSI, and the inductor current ripple reduction is required to achieve it. The proposed method can reduce the inductor current ripple by 27.8% compared with the conventional method that has equal short-through intervals without increasing the number of inverter switching. The proposed operation and ripple reduction were confirmed in experiments with a 3-kW-class laboratory prototype. Its result agreed to the calculated results, and it was confirmed that there is no increase in circuit losses caused by the application of the proposed method. [ABSTRACT FROM AUTHOR]

In this paper, a new zero-sequence current suppression control strategy for the five-phase open-winding fault-tolerant fractional-slot concentrated-winding interior-permanent-magnet (FTFSCW-IPM) motor drive system with a common dc bus is proposed. By unequal distribution of the zero voltage vector, the proposed method can well suppress the zero-sequence current caused by the dead-time effect that the conventional eliminating method cannot be achieved. First, the dead-time effect to the zero-sequence current is discussed. Then the zero-axis controller is designed to obtain the reference common-mode voltage. Last, according to the principle of the unequal zero voltage vector distribution, the switching sequence of the two inverters can be calculated, and the maximum modulation index is also first deduced in detail. The proposed method is proved by the simulation and experimental results. [ABSTRACT FROM AUTHOR]

An isolated single sourced multi-output dc/dc converter with a high-frequency link was proposed before to feed different cells of the Asymmetrical Cascaded H-bridge (ACHB) inverter. One of the fundamental advantages of the ACHB is that the main H-bridge is commutated with fundamental frequency, passing the majority of the inverter power. However, the isolated dc/dc converter needs to be connected to the main voltage source with high-voltage/high-frequency switches, which limits the power capability and the efficiency of the converter. In this paper, a switching pattern based on nearest level modulation method is proposed to command all the power to be transferred through the main H-bridge. Therefore, the power circulates between the auxiliary H-bridges with no need for high-voltage switches. As a result, a single-input single-output auxiliary converter is needed with only 5% of the power rating. This solution reduces cost and size while it improves the efficiency of the converter. Furthermore, the architecture makes the inverter more suitable for high power and high-voltage applications. The inverter switching strategy is based on programmable firing angles. The main dc-link of the grid connected inverter is controlled to achieve maximum power point tracking, while the dc/dc isolated converter is controlled to regulate the auxiliary dc-links. The proposed topology is verified by simulation and experimental results using a 1.5 kW hardware prototype. [ABSTRACT FROM AUTHOR]

This paper proposes advanced speed control for a five-leg voltage source inverter (FLVSI) that drives the dual three-phase induction motor system used in industrial manufacturing processes. The advanced speed control method consists of two controllers: 1) The first is a slip controller that satisfies the application requirement, i.e., to control the mechanical speed of two motors equally regardless of the load condition. 2) The second is an angle controller that satisfies the FLVSI requirement, i.e., to control the phase angle difference between the two motors for minimizing the common leg current because the common leg current can be twice higher than other leg's current depending on the operation condition of the dual motor. Stability analysis of the two controllers under advanced speed control is implemented, and the whole performance of the advanced speed control for the FLVSI-fed dual-motor drive system is shown to identify its feasibility through the experimental results. [ABSTRACT FROM AUTHOR]

In this paper, a modified selective harmonic mitigation pulse amplitude modulation (SHM-PAM) is presented to be capable of canceling all triplen harmonic orders and suitable for single-phase application of five-level type of voltage source inverters. To this end, a new constraint is established for the two switching angles (α1, α2) to derive the new formula for the harmonics’ amplitude, which results in self-elimination of all triplen harmonics (e.g., 3rd, 9th, 15th, …). The fifth and seventh harmonic orders are mitigated through normal operation of the proposed SHM-PAM technique. It is also shown that the proposed technique is extendable to other multilevel voltage waveforms and a flowchart of self-elimination of all triplen harmonics has been presented. Mathematical analysis supported by experimental investigations show the desired performance of the proposed SHM-PAM algorithm on a two-cell single-phase cascaded H-bridge inverter as a typical five-level configuration in dealing with linear and nonlinear loads. Then, it is demonstrated that the maximum number of harmonic orders would be controlled with the minimum number of available angles in a low switching frequency voltage waveform. [ABSTRACT FROM AUTHOR]

Although high-frequency circulating current exists in parallel-operated inverters, it has not attracted as much attention as low-frequency circulating current, and thus has not been analyzed in detail previously. In this paper, a mathematical model and analysis are presented, which reveal the spectrum components and their changing trends of the circulating currents caused by carrier phase differences. The impact of carrier phase difference on high-frequency circulating current is also analyzed and verified. A closed-loop control scheme is proposed to suppress the switching frequency circulating current caused by carrier phase difference. In addition, the deadbeat and closed-loop control are combined to suppress the low- and high-frequency circulating currents simultaneously, to improve the overall performance of circulating current suppression. The effectiveness of the proposed scheme is verified by the simulation and experimental results acquired from a laboratory platform. [ABSTRACT FROM AUTHOR]

This paper proposes a control method for a five-level hybrid flying-capacitor (5L-HFC) inverter, of which structure stems from the conventional five-level active neutral-point-clamped (5L-ANPC) topology by dividing the dc-link stage into three series-connected capacitors. In this inverter, the voltage stress on the power switches connected to the dc link is reduced by a half compared with that of the 5L-ANPC topology, thus the lower number of equally voltage-rated power devices can be employed. Also, the power losses in the 5L-HFC inverter are more evenly distributed than in the 5L-ANPC. In order to balance the dc-link capacitor voltages, a third-order harmonic offset injection is applied. When a diode rectifier is used to supply the dc bus voltage, the balancing method is not effective if the modulation index is higher than 0.64. Thus, an auxiliary circuit is needed to support the balancing of the dc-link capacitor voltages. However, the unbalancing problem can be overcome in a full-range operation without the auxiliary circuit if the back-to-back configuration is utilized. Finally, simulation and experiment results have verified the performance of the 5L-HFC inverter with the proposed control method. [ABSTRACT FROM AUTHOR]

This paper investigates the open-circuit faults of switching devices in the three-level T-Type inverter and proposes a new tolerant control method. The three-phase current and variation of the neutral-point voltage are detected to determine the fault switch. A carrier-based pulse width modulation is developed to tolerate switch fault by transiting from three-level to two-level switching. This makes the modulation scheme easier to be implemented compared to space vector modulation. For the neutral-point fault, the fault phase is operated by two-level modulation to produce the same rating voltage. On the other hand, the inverter is able to produce balanced voltage with reduced rating by keeping the phase of half-bridge fault to the neutral-point voltage. The neutral-point voltage is also able to be balanced by using two-level modulation since it does not contribute the neutral-point current. The performance and effectiveness of the proposed tolerant control are verified by a laboratory build. [ABSTRACT FROM AUTHOR]

Owing to low cost, small size, and low weight, transformerless inverters became prominent in single-phase grid connected photovoltaic (PV) systems. Key issues pertaining to these inverters include suppression of common mode (CM) leakage current and improvement of conversion efficiency. Achieving higher efficiency in single-phase grid-connected photovoltaic systems depends on the number of stages involved in feeding power to the grid, predominantly, if the PV array voltage is less than the peak value of the grid voltage. In this paper, an integrated dc–dc converter based grid-connected transformerless PV inverter is proposed which is aimed at maintaining high efficiency, even if the PV array voltage falls below the peak value of grid voltage (efficient operation at an extended input voltage range). A modulation strategy is discussed in order to minimize the flow of CM leakage current. Further, the efficiencies of certain transformerless inverter topologies are analyzed and compared with that of the proposed topology. Detailed simulation studies are carried out in MATLAB/Simulink environment to verify the analysis. Experimental results for a scaled down laboratory prototype are included as a proof-of-concept to validate the claims. [ABSTRACT FROM AUTHOR]

In this paper, angular modulation index (AMI) implemented through a modified space vector modulation for the dual voltage source inverters (VSI) is proposed with the primarily aiming to reduce switching losses. The desired voltage across the load is synthesized by applying appropriate phase-angle displacement between space vector references. The proposed approach avoids the use of a dc/dc boost converter (which imposes loss and weight/price penalty to duplicate the dc-link voltage) and results to be particularly suitable for electrical/hybrid vehicle applications. Namely, the application of saving energy to keep driving has been identified as major concern. Hence, this work focuses on the strategy to enhance efficiency. The principles of the proposed controlling method and switching loss, which is reduced at least by 50%, are theoretically evaluated. This paper proposes a pioneering mathematical approach to correctly determine total harmonic distortion (THD) value of the voltage/current for the dual-VSI structure. Furthermore, simulation and experimental results prove that the proposed method insures benefits in terms of common-mode voltage, THD of the voltage, and switching loss reduction. The dual-VSI prototype supplying 1.5-kW induction motor is assembled in the laboratory to experimentally evaluate performance of the proposed method. Also, the simulation results carried out through MATLAB/Simulink environment are given to confirm performance of this easy-to-implement and high-efficient method. [ABSTRACT FROM PUBLISHER]

This paper presents a new application of power and voltage balance control schemes for the cascaded H-bridge multilevel inverter (CHMI)-based solid-state transformer (SST) topology. To reduce load on the controller and simplify modulation algorithm, a master–slave control (MSC) strategy is designed for the dual active bridge (DAB) stage. The master controller executes all control and modulation calculations, and the slave controllers manage only device switching and protection. Due to the inherent power and dc-link voltage unbalance in cascaded H-bridge-based SST, this paper presents a compensation strategy based on three-phase dq decoupled current controller. An optimum zero-sequence component is injected in the modulation scheme so that the three-phase grid currents are balanced. Furthermore, to tightly regulate the output voltage of all the DAB modules to target value, a dynamic reference voltage method is also implemented. With this proposed control method, the three-phase grid currents and dc-link voltage in each module can be simultaneously balanced. Finally, simulation and experimental results are presented to validate the performance of the controller and its application to microgrid SST. [ABSTRACT FROM PUBLISHER]

In order to solve the neutral-point voltage unbalancing problem for three-level inverters, this paper proposes a method to balance the neutral-point voltage for three-level inverters with variable modulation wave offset sinusoidal pulse-width modulation (SPWM) control. Based on the mathematical expressions of neutral-point voltage unbalancing, the factors are studied, which affect the fluctuation of neutral-point voltage. Theoretically the mathematical expressions of the neutral-point voltage with the proposed method are derived, and the mathematical relationship between the fluctuation of neutral-point voltage and the adjusting offset of modulation wave is studied. This proposed method realizes controlling the neutral-point voltage balance by dynamically calculating the offset superimposed to the modulation wave based on SPWM (DCOSPWM). This DCOSPWM method is very simple, which has good steady-state performance and is easy for digital implementation. The simulation results verify the correctness of the theoretical analysis in this paper, and the feasibility and effectiveness of this method is verified by the experiments in the experimental platform of neutral point clamped three-level inverters based on digital signal processor (DSP)-complex programmable logic device (CPLD). [ABSTRACT FROM AUTHOR]

This paper is concerned with the use of a three-level inverter for a synchronous reluctance machine (SynRM). The SynRM suffers from a poor power factor due to poor machine saliency. This makes it harder to operate the three-level neutral-point-clamped inverter due to a strict requirement to have the two dc-link capacitor voltages balanced. This paper proposes a new nearest three vector modulation algorithm which can balance the two dc-link capacitors even at poor machine saliency ratio (poor power factor). In this paper, a method of sizing the two dc-link capacitors based on the machine power is also proposed. A comparison between two- and three-level inverters was conducted. The SynRM registered lower $d$-axis current ripple with a three-level inverter, indicating lower core losses in the machine. [ABSTRACT FROM PUBLISHER]

This paper proposes a vector control strategy for independent control of two permanent-magnet synchronous motors (PMSMs) using a single four-leg inverter (4LI). An expanded two-arm modulation to obtain a balanced three-phase output voltage is described. This paper also proposes a method to compensate for the fluctuations in the neutral point voltage of two split capacitors in the dc link. The experimental results show that independent speed and position control of two PMSMs can be achieved using a single 4LI with the proposed vector control method. [ABSTRACT FROM AUTHOR]

Multilevel inverters with dodecagonal (12-sided polygon) voltage space vector structure have advantages, such as complete elimination of fifth and seventh harmonics, reduction in electromagnetic interference, reduction in device voltage ratings, reduction of switching frequency, extension of linear modulation range, etc., making it a viable option for high-power medium-voltage drives. This paper proposes two power circuit topologies capable of generating multilevel dodecagonal voltage space vector structure with symmetric triangles (for the first time) with minimum number of dc-link power supplies and floating capacitor H-bridges. The first power topology is composed of two hybrid cascaded five-level inverters connected to either side of an open-end winding induction machine. Each inverter consists of a three-level neutral-point-clamped inverter, which is cascaded with an isolated H-bridge making it a five-level inverter. The second topology is for a normal induction motor. Both of these circuit topologies have inherent capacitor balancing for floating H-bridges for all modulation indexes, including transient operations. The proposed topologies do not require any precharging circuitry for startup. A simple pulsewidth modulation timing calculation method for space vector modulation is also presented in this paper. Due to the symmetric arrangement of congruent triangles within the voltage space vector structure, the timing computation requires only the sampled reference values and does not require any offline computation, lookup tables, or angle computation. Experimental results for steady-state operation and transient operation are also presented to validate the proposed concept. [ABSTRACT FROM PUBLISHER]

A new space vector modulation, i.e., ZSVM3, for three-phase quasi-Z-source rectifier (qZSR) is proposed. All switches in the three-phase bridge can be turned on and turned off with zero current or zero voltage using the proposed ZSVM3 with no auxiliary circuit. The current through the inductors of the quasi-Z-source network operates in a boundary conduction mode or discontinuous conduction mode to achieve all freewheeling diodes turned off with zero-current switching (ZCS). At the same time, the switch in the quasi-Z-source network can be turned on with ZCS. Besides, the voltage stress of all switches is equal to dc-link voltage. The operation principle of the qZSR is analyzed in detail, and the calculated value of the quasi-Z-source inductor is given. The proposed theory in this paper is verified by a 2-kW prototype. [ABSTRACT FROM PUBLISHER]

In this paper, a method is proposed to investigate the dc-link current and voltage ripple calculations in voltage source inverters by considering the reverse recovery of the antiparallel diodes. The impact of the diode reverse recovery transient on the dc-link current and voltage within the switching period is first analyzed. The analysis indicates that the current ripple rms value is affected by the value of inverter switching frequency, diode reverse recovery time, and current. However, the diode reverse recovery shows negligible impact on the dc-link voltage ripple calculation, since the difference between the voltage ripples calculated by the proposed and existing method is less than 1%. To evaluate the estimation accuracy of the dc-link current ripple rms value by the proposed method, the experiments are implemented and the comprehensive analysis is done under different operating conditions, including various power factors, modulation indexes, inverter output currents, and inverter switching frequencies. Experimental results show that the accuracy of dc-link rms current ripple calculation by the proposed method is in the range of $\pm$5% and increased by up to 7% compared with the existing method neglecting the antiparallel diode reverse recovery. [ABSTRACT FROM AUTHOR]

Space vector modulation (SVM) is a widely used method for multilevel inverters. Most of the SVM methods are nearest three vector (N3V) based schemes. Therefore, several researchers have proposed advanced implementation algorithms with reduced complexity for N3V methods. However, topologies like neutral point (NP) clamped inverter (NPCI) require some distinctive methods (called as non-N3V methods) to balance NP voltage for high modulation index and low power factor operations. Currently, the existing non-N3V methods exercise highly complex algorithms for duty ratio calculation and subtriangle identification. This paper presents a new approach, suitable for both N3V and non-N3V methods, with reduced implementation complexity. The proposed algorithm is based on an equivalent two-level space vector diagram and does not require any trigonometry, coordinate transformation, or volt-second balance solution. Unlike other carrier-based methods, it can change the switching sequence as well as the duration of redundant vectors. Moreover, the proposed approach does not require extra steps for implementing hybrid modulation and it can also be extended to multilevel topologies. One N3V, two non-N3V, and hybrid methods are developed using the proposed modulation algorithm, and are compared in detail. Simulation and experimentation on a three-level NPCI verify the validity of the proposed algorithm. [ABSTRACT FROM PUBLISHER]

In this paper, finite-set model-predictive control (FS-MPC) methodologies for a grid-connected three-level neutral-point-clamped converter are investigated. The proposed control strategies produce fixed switching frequency, maintaining all the advantages of predictive control such as fast dynamic response, inclusion of nonlinearities and restrictions, and multivariable control using a single control loop. The first of the proposed FS-MPC strategies is based on a multiobjective cost function, designed to regulate both the inverter currents and the balancing of the dc-link capacitor voltages. The second FS-MPC strategy is derived from the first one, and it is based on a cost function that regulates only the grid current, with the balancing of the capacitor voltages being realized by controlling the duty cycles of the redundant vectors. The proposed control systems are experimentally validated using a 5-kW prototype. The experimental results show a good performance for both strategies, in steady-state and transient response, with a total harmonic distortion lower than \text2\% for the currents supplied to the grid. [ABSTRACT FROM PUBLISHER]

The hybrid modulation strategy using both low-frequency square-wave modulation and high-frequency pulse-width modulation can extend the stable operating region of a cascaded H-bridge converter. However, it does not control accurately dc voltages of converter but balances them by charging or discharging dc capacitors based on the state of system, which could aggravate fluctuation of dc voltages. If cascaded H-bridge converter is used in photovoltaic field, the aggravated fluctuation on dc capacitor voltages will result in further losses in energy harvesting of solar cells. To address this issue, a modified hybrid modulation strategy is presented in this paper. When dc-bus measured voltages are close to their reference voltages, these H-bridges operate in a zero mode. Adding appropriate zero state can prevent grid current charging or discharging the dc capacitors whose voltages have already reached their control goals. Therefore, the proposed technique is capable of suppressing dc voltage fluctuation, and, thus, improving the output power of solar cells. Simulation and experimental results validate the effectiveness and feasibility of the proposed method. [ABSTRACT FROM PUBLISHER]

Microinverters for grid-connected photovoltaic (PV) power conversion systems often require voltage boost due to the low dc voltage of the PV panels. A high-frequency (HF) transformer-isolated differential-mode Ćuk inverter (DMCI) is an attractive topology due to its inherent voltage boost capability and high power density. One of the significant operational issue of the DMCI addressed in this paper is the presence of lower order harmonic distortion in the injected grid current. It is shown that lower order odd and even harmonic voltages are generated with this topology. This problem is accentuated due to the low damping offered by the grid to harmonic voltages. A systematic low-complexity control design is proposed to address this issue. It is shown experimentally that the DMCI operates stably with effective attenuation of the lower order harmonics using the proposed design. Practical operational issues of the DMCI with fast switching GaN field-effect transistor (FET) devices are analyzed and solutions are proposed. It is shown that there can be significant HF noise generation in the DMCI with a frequency range higher than the switching frequency. Practical solutions for resolving HF issues using a combination of circuit layout design and additional passive components are proposed and validated. All of the experimental results are demonstrated on a 500-W GaN-FET-based microinverter prototype. [ABSTRACT FROM PUBLISHER]

Several single-stage topologies have been introduced since kicking off the three-phase Z-source inverter (ZSI), and among these topologies, the quasi-ZSI (qZSI) is the most common one due to its simple structure and continuous input current. Furthermore, different modulation strategies, utilizing multiple reference signals, have been developed as well. However, prior art modulation methods have some demerits, such as the complexity of generating the gate signals, the increased number of switch commutations with continuous commutation at high current level during the entire fundamental cycle, and the multiple commutations at a time. Hence, this paper proposes two modified space vector modulation strategies, aimed at the reduction of the qZSI number of switch commutations at high current level for shorter periods during the fundamental cycle, i.e., reducing the switching loss, simplifying the generation of the gate signals by utilizing only three reference signals, and achieving a single-switch commutation at a time. These modulation strategies are analyzed and compared to the conventional ones, where a reduced-scale 1-kVA three-phase qZSI is designed and simulated using these different modulation strategies. Finally, the 1-kVA three-phase qZSI is implemented experimentally to validate the performance of the proposed modulation strategies and verify the reported analysis. [ABSTRACT FROM PUBLISHER]

This paper presents an optimized topology of 3-$\phi$ , multilevel inverter (MLI) configuration for five or higher level operation with reduced switch count. The proposed solution consists of two basic units (BUs) of multilevel converter and a T-structured 3-level inverter (3-LI). Both BUs are equally shared by the three phases maintaining symmetry among the phases. Moreover, for a higher level operation of the proposed MLI, the modifications required are at two BUs only and not at three legs of the inverter. It further helps in reducing the requirement of extra components for higher level operation compared to the conventional solutions. Furthermore, the topology also has the benefits of reduced switching and conduction loss. An algorithm is also devised to generate the switching pulses for the BUs and the 3-LI, using a carrier-based space vector modulation technique. Presented topology is compared with other existing topologies to prove its advantage. All the details regarding the operating modes and pulse width modulation techniques employed for the proposed system are given and supported by the simulation and experimental results. [ABSTRACT FROM AUTHOR]

Adding the auxiliary switches to the conventional H-bridge inverter is an effective way to eliminate the leakage current for transformerless PV systems, such as H5, H6, etc. Inspired by the newly developed embedded-switch H6 topology, a novel embedded-switch inverter (ESI) is proposed in this paper for three-phase transformerless PV systems. First, the operation principle and characteristics of the proposed ESI are analyzed. Second, the common-mode model of the three-phase ESI is established, based on which the main factors that affect the leakage current are discussed. The finding reveals that the switching states with conventional modulation strategy result in high-frequency common-mode voltage, which is the source of leakage current. In order to solve the problem, a new modulation strategy is presented for ESI to eliminate the high-frequency leakage current. Finally, the time-domain simulation and the experimental tests are carried out. The results verify the effectiveness of the proposed solution. [ABSTRACT FROM AUTHOR]

This paper aims to investigate a disturbance-rejection-based model predictive control (MPC) with two flexible modes (i.e., unconstrained mode and constrained mode) for three-phase inverters with an $LC$ filter. A disturbance observer (DOB) is designed to both simplify the prediction model and achieve the robustness against uncertain parameters. First, the unconstrained mode is designed with a simple horizon-one MPC control law to precisely regulate the output voltage in the steady state. Next, the constrained mode is designed with long-horizon MPC to quickly drive the system to the unconstrained mode by further optimizing the modulation stage. Also, the proposed MPC ensures the robustness and optimality in all operating modes. Especially, the overall closed-loop stability with DOB dynamics is proven by using Lyapunov function. Unlike other MPC methods, the long-horizon MPC in the constrained mode is specialized by finite switching sequences of the sector-based space vector modulation. Comparative studies with the conventional linear quadratic regulator are conducted on a prototype test bed with a TI TMS320F28335 DSP. Then, the proposed MPC method verifies fast dynamic response and advanced voltage regulation (i.e., small steady-state errors and low total harmonic distortion) under various load conditions and uncertain parameters. [ABSTRACT FROM AUTHOR]

Traditional model predictive control cost functions, when utilizing long prediction horizons ( $N\geq 10$) in power inverter applications, have demonstrated harmonic performances approaching that of schemes based on offline-generated optimal pulse patterns. However, long prediction horizons often prohibitively increase computational load. A different approach to maximizing harmonic performance is taken in this paper. It is shown that shaping the output voltage spectra using a simple feedback mechanism can significantly reduce the length of the required prediction horizon, facilitating a feasible computational load. When a short-horizon cost function is augmented by the feedback mechanism an excellent tradeoff between harmonic performance and switching loss is achieved, even with a prediction horizon of one. It is also shown that the feedback mechanism can be used to improve input reference tracking. Experimental verification of the proposed modulator is performed on a two-level three-phase inverter. [ABSTRACT FROM AUTHOR]

This paper proposes a family of novel flying capacitor transformerless inverters for single-phase photovoltaic (PV) systems. Each of the new topologies proposed is based on a flying capacitor principle and requires only four power switches and/or diodes, one capacitor, and a small filter at the output stage. A simple unipolar sinusoidal pulse width modulation technique is used to modulate the inverter to minimize the switching loss, output current ripple, and the filter requirements. In general, the main advantages of the new inverter topologies are: 1) the negative polarity of the PV is directly connected to the grid, and therefore, no leakage current; 2) reactive power compensation capability; and 3) the output ac voltage peak is equal to the input dc voltage (unlike neutral-point-clamped and derivative topologies, which requires twice the magnitude of the peak ac voltage). A complete description of the operating principle with modulation techniques, design guidelines, and comprehensive comparisons is presented to reveal the properties and limitations of each topology in detail. Finally, experimental results of 1-kVA prototypes are presented to prove the concept and theoretical analysis of the proposed inverter family for practical applications. [ABSTRACT FROM PUBLISHER]

Four-level nested neutral-point clamped (NNPC) inverters experience severe voltage balancing problems under low output-frequency conditions when the conventional four-level space vector modulation (4L-SVM) technique is applied, which limits their wider application. In order to get a complete control of the flying-capacitor voltages, and to alleviate the calculation burden of conventional 4L-SVM, a simplified but effective 4L-SVM technique along with the voltage balance control (VBC) function is proposed in this paper. For low modulation indexes, zero and small vectors are selectively utilized and distributed to force the average charging and discharging time of flying capacitors to be equal to each other during every switching period, so that voltage ripples are greatly reduced to be within an acceptable level under low output-frequency conditions. For high modulation indexes, the simplification of conventional 4L-SVM for NNPC inverters into two-level SVM is proposed to reduce the computation complexity. Principles of the proposed 4L-SVM and VBC are elaborated in detail. The steady-state, transient-state, and VBC performances are investigated and compared with the case where the conventional 4L-SVM is applied. Simulation results of a 5 MVA inverter system and experimental results of a scaled-down 5 kVA inverter system are presented to validate the proposed method. [ABSTRACT FROM PUBLISHER]

This paper proposes a new nine-level inverter for medium- and high-power applications. The proposed topology comprises of a three-level (3L) active neutral-point-clamped (ANPC) inverter connected in series with a floating capacitor (FC) fed H-bridge. Besides, two additional switches operating at line frequency are appended across the dc link of the 3L ANPC structure. Compared with conventional hybrid cascaded inverters, the primary advantage of this addition is doubling of the resulting root mean square output voltage. This amelioration is achieved while preserving the standard 3L ANPC and H-bridge structures with minimum topological modification. A simple logic-gate-based voltage balancing scheme is developed to regulate the FC voltage. The proposed voltage balancing method is independent of load power factor, inverter modulation index, and can balance the voltage across FC instantaneously. The step-by-step formulation of logical expressions for the generation of gating pulses is deliberated in detail and can be generalized for any $n$-level inverter. Further, simulation results as well as the experimental measurements obtained from the laboratory prototype are presented to validate the effectiveness and practicability of the proposed configuration. Finally, the notable merits of the proposed inverter over the prior art topologies is established through a comprehensive comparative study. [ABSTRACT FROM PUBLISHER]

Three-phase inverters in uninterrupted power supply, electric vehicles, and hybrid electric vehicles use an intermediate dc-link electrolytic capacitor, which has reliability issues and is one prominent cause of inverter failure and limited life. The large volume of an electrolytic capacitor increases the size and cost of the system. Recent research on electrolytic capacitorless inverters using six-pulse modulation technique along with high-frequency power conversion has attempted to address this issue. However, closed-loop operation and control has some issues due to capacitorless dc-link. In this paper, closed-loop operation, design, and implementation of an electrolytic capacitorless inverter is presented. A proof-of-concept 1-kW hardware prototype has been built and tested in a laboratory under different loading conditions. In total, 98% rated efficiency of the inverter is obtained with total harmonic distortion within 2%. Transient results during start-up and load change are smooth, demonstrating safe operation of the inverter. [ABSTRACT FROM AUTHOR]

The cascaded H-bridge converter has been widely used in industry. The ability of dealing with unequal power generation among dc links is necessarily required in many applications, such as large-scale photovoltaic power plants and electric vehicles. In this paper, a novel dc-power control method (PCM) is proposed to keep the ac-current balance and maintain power generation ratios of each dc source at their expected values. A simplified modulation strategy is introduced to implement the proposed method, in which the duration times are modified directly by the correction value derived from the PCM method. To calculate and adjust the power generation ratios, a method based on first-in first-out (FIFO) data queue is utilized. The limitation and ranges of power generation ratio are analyzed in detail. DC power per phase can be controlled accurately by the proposed method in variable-frequency condition, even under larger power generation ratios. Results obtained from simulations and experiments are presented to verify the feasibilities and superiorities of the proposed method. [ABSTRACT FROM PUBLISHER]

When employed as a modulator in power inverters, model predictive control has an equivalence to a recently proposed modulation technique known as feedback quantizer modulation (FBQM). Both schemes produce a random-like switching pattern that can facilitate explicit control over the shape of frequency spectra associated with inverter output voltages and currents. This is useful to satisfy electromagnetic interference and acoustic noise requirements, and to avoid excitation of external system resonances. However, it will be shown in this paper that inverter deadtime introduces a disturbance into FBQM that significantly degrades the ability to shape the frequency spectra. Several compensation techniques, designed to model the effect of deadtime inside the formulation of FBQM, are proposed and experimentally verified on a two-level three-phase inverter. [ABSTRACT FROM PUBLISHER]

This paper presents a single-phase ac power supply circuit that based on modified voltage-fed quasi-Z-source inverter topology; it suits to the light or the heavy load and is fit for the resistive, inductive, or capacitive load. The topology, operating principle, voltage gain, control method, and its realization by DSP are described in this paper. The feasibility and rationality of the system is verified by the simulation and experimental results. [ABSTRACT FROM PUBLISHER]

Multilevel inverters are receiving more attentions nowadays as one of preferred solutions for medium- and high-power applications. As one of the most popular hybrid multilevel inverter topologies, the five-level active-neutral-point-clamped inverter (5L-ANPC) combines the features of the conventional flying-capacitor type and neutral-point-clamped (NPC) type inverter and was commercially used for industrial applications. In order to further decrease the number of active switches, this paper proposes a seven-switch 5L-ANPC (7S-5L-ANPC) topology, which employs only seven active switches and two discrete diodes. The analysis has shown a lower current rating can be selected for the seventh switch under high power factor condition, which is verified by simulation results. The modulation strategy for 7S-5L-ANPC inverter is discussed. A 1 kVA single-phase experimental prototype is built to verify the validity and flexibility of the proposed topology and modulation method. [ABSTRACT FROM AUTHOR]

Large-scale photovoltaic (LSPV) energy conversion systems have been installed at many places across the world. The essential component of the LSPV system is the dc–ac conversion stage. The usage of multilevel converters is one of the recent advances in the dc–ac conversion stage of the LSPV system to enable transformer-less inversion. Current-fed multilevel inverter has been chosen in this paper as it provides high power inversion with inherent voltage boosting, and thus, avoids the usage of transformer. High power conversion necessitates low device switching frequency operation in order to satisfy thermal constraint of semiconductor devices and also to improve efficiency. However, low device switching frequency operation leads to higher harmonic distortion of inverter output currents. Synchronous optimal pulsewidth modulation (SOP) technique is an emerging low device switching frequency modulation technique that has been successfully implemented for voltage-source multilevel inverters. However, the state-of-the-art SOP technique cannot be directly applied to modulate current-source multilevel inverter topologies due to additional constraints on the switching commutations. Therefore, the purpose of our study was to propose a modified SOP technique to achieve: low device switching frequency and minimal harmonic distortion of inverter output currents. The topology of current-fed five-level inverter was used for demonstrating the performance of proposed technique. A generalized conversion method was introduced in the modified SOP technique for including switching constraints of the current-fed inverter. In addition, a state-sequencing machine was developed by utilizing redundant inverter states to produce equal switching commutation among all semiconductor devices at minimal switching frequency of 350 Hz. The experimental results obtained from the five-level current-source inverter of 1.2 kW demonstrated the effectiveness of the proposed SOP technique. [ABSTRACT FROM AUTHOR]

A new concept of dual-dc-port asymmetrical multilevel inverter (DP-AMI), which is able to interface a low-voltage dc port, a high-voltage dc port, and an ac port simultaneously using only one topology, is presented in this paper. A systematic method to derive the DP-AMI is proposed. With the proposed DP-AMI, a low-voltage dc source, e.g., photovoltaic (PV) modules or battery, can directly supply power to the ac load within single-stage power conversion. Therefore, in comparison with a traditional two-stage dc/ac power conversion system, the power conversion stages are reduced and the voltage/current stress of the front-end dc/dc converter can be significantly alleviated, which can improve the overall conversion efficiency dramatically. Furthermore, by using the low-voltage dc source as a new voltage level, asymmetrical multiple voltage levels are generated by the proposed DP-AMI, which is beneficial for the reducing switching losses and the size/volume of the output filter. The topology derivation method of the DP-AMIs is presented. The operation principles, modulation schemes, and characteristics of one of the proposed DP-AMIs are analyzed in detail. A 1-kW prototype is built and tested to verify the effectiveness and advantages of the proposed method. [ABSTRACT FROM PUBLISHER]

For power conversion systems interfaced to four-wire supplies, four-leg converters have become a standard solution. A four-leg converter allows good compensation of zero-sequence harmonics and full utilisation of the dc-link voltage. These are very important features when unbalanced and/or nonlinear loads are connected to the system. This paper proposes a three-dimensional space vector modulation (SVM) algorithm and provides a comprehensive analysis of the algorithm implemented on a three-level, four-leg neutral-point-clamped converter. The algorithm allows a simple definition of the different switching patterns and enables balancing of the dc-link capacitor voltages using the redundancies of the converter states. A resonant controller is selected as the control strategy to validate the proposed SVM algorithm in a 6 kW experimental rig. [ABSTRACT FROM AUTHOR]

The modulation strategy LMZVM (large, middle, and zero vector modulation) can be widely adopted in the three-level 7 photovoltaic (PV) inverter, because it reduces the ground current and produces little neutral-point (NP) voltage in normal operation. However, in low-voltage ride-through (LVRT) operation, the NP voltage fluctuation becomes large and has not been researched nowadays. In this paper, according to this problem, four critical weighing factors about the NP voltage based on symmetrical component method are proposed. We can see that the maximum peak-to-peak value among all dip types happens when the single-phase grid voltage dips to 0. Then, an original balancing strategy, which replaces the zero vector with two opposite P-type or N-type small vectors of equal duty cycle, is put forward. Experimental results are provided to validate that the proposed strategy can reduce the NP voltage fluctuation in LVRT operation. [ABSTRACT FROM AUTHOR]