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This paper is concerned with the use of a three-level inverter for a synchronous reluctance machine (SynRM). The SynRM suffers from a poor power factor due to poor machine saliency. This makes it harder to operate the three-level neutral-point-clamped inverter due to a strict requirement to have the two dc-link capacitor voltages balanced. This paper proposes a new nearest three vector modulation algorithm which can balance the two dc-link capacitors even at poor machine saliency ratio (poor power factor). In this paper, a method of sizing the two dc-link capacitors based on the machine power is also proposed. A comparison between two- and three-level inverters was conducted. The SynRM registered lower $d$-axis current ripple with a three-level inverter, indicating lower core losses in the machine. [ABSTRACT FROM PUBLISHER]

The planned China fusion engineering test reactor (CFETR) needs one or more negative-ion-based neutral beam injectors (N-NBIs) with a beam energy of 500 or even 1000 keV. In order to prepare for CFETR, a prototype of CFETR N-NBI is being designed. The prototype needs an acceleration grid power supply (AGPS) rated at 200 kV/25 A with a maximum pulselength reaches to 3600 s. The AGPS adopted a single-stage inverter-type high-voltage power supply (HVPS). The output voltage ripple is an important specification of the AGPS, which can affect the efficiency and stability of N-NBI system by influencing the beam divergence. However, the conventional methods cannot be used to limit the output voltage ripple of the inverter-type HVPS used as AGPS of CFETR N-NBI prototype. This paper simplified the AGPS to an insulated three-phase three-level (TPTL) dc–dc converter connected with a dual dc link. The working process of the TPTL dc–dc converter with duty-cycle modulation has been analyzed, and two main continuous conduction modes are described. The influence of key parameters such as duty cycle of inverter, leakage inductance of transformer, and output current on output voltage ripple is analyzed. Based on the analysis results, a so-called combined control strategy was proposed to keep the output voltage ripple at a level. The proposed strategy is suitable for the cases where the object output voltage is below 175 kV. Some simulations were carried out by using MATLAB/Simulink. The results showed that the analysis in this paper is reliable and the proposed control strategy has a good performance. [ABSTRACT FROM AUTHOR]

This paper proposes a vector control strategy for independent control of two permanent-magnet synchronous motors (PMSMs) using a single four-leg inverter (4LI). An expanded two-arm modulation to obtain a balanced three-phase output voltage is described. This paper also proposes a method to compensate for the fluctuations in the neutral point voltage of two split capacitors in the dc link. The experimental results show that independent speed and position control of two PMSMs can be achieved using a single 4LI with the proposed vector control method. [ABSTRACT FROM AUTHOR]

Multilevel inverters with dodecagonal (12-sided polygon) voltage space vector structure have advantages, such as complete elimination of fifth and seventh harmonics, reduction in electromagnetic interference, reduction in device voltage ratings, reduction of switching frequency, extension of linear modulation range, etc., making it a viable option for high-power medium-voltage drives. This paper proposes two power circuit topologies capable of generating multilevel dodecagonal voltage space vector structure with symmetric triangles (for the first time) with minimum number of dc-link power supplies and floating capacitor H-bridges. The first power topology is composed of two hybrid cascaded five-level inverters connected to either side of an open-end winding induction machine. Each inverter consists of a three-level neutral-point-clamped inverter, which is cascaded with an isolated H-bridge making it a five-level inverter. The second topology is for a normal induction motor. Both of these circuit topologies have inherent capacitor balancing for floating H-bridges for all modulation indexes, including transient operations. The proposed topologies do not require any precharging circuitry for startup. A simple pulsewidth modulation timing calculation method for space vector modulation is also presented in this paper. Due to the symmetric arrangement of congruent triangles within the voltage space vector structure, the timing computation requires only the sampled reference values and does not require any offline computation, lookup tables, or angle computation. Experimental results for steady-state operation and transient operation are also presented to validate the proposed concept. [ABSTRACT FROM PUBLISHER]

Enhancement of dc bus voltage utilization for a five-level inverter with single dc source and capacitor-fed H-bridge (CHB) units is investigated in this paper. A carrier-based modulation technique is used for boosting the dc bus utilization, which is established by providing detailed mathematical analysis. The five-level inverter used here is realized by cascading a CHB unit to each phase of a three-level neutral point clamped inverter. The increase in dc bus voltage utilization owes to the pole voltage redundancies offered by CHB units. The floating capacitors of H-bridge units are balanced within a quarter fundamental cycle using the switching state redundancies of pole voltage levels. The aforementioned modulation technique allows the inverter to enhance the dc bus utilization from 0.577 $\text{V}_{\text{dc}}$ to 0.63 $\text{V}_{\text{dc}}$ under unity power factor. This enhancement is obtained in the linear modulation range without increasing the dc bus voltage, and thus, the inverter can operate without the presence of low-order harmonics in its phase voltages. The strength of this paper lies in its detailed mathematical analysis for finding out the limiting modulation index and power factor condition in the light of floating capacitor voltage balancing issue. Simulation as well as experimental verification of the modulation scheme is carried out on an induction motor drive under various operating conditions. It is shown that this carrier-based modulation technique is suitable for any single source inverter topology with one CHB unit per phase. [ABSTRACT FROM AUTHOR]

An isolated single sourced multi-output dc/dc converter with a high-frequency link was proposed before to feed different cells of the Asymmetrical Cascaded H-bridge (ACHB) inverter. One of the fundamental advantages of the ACHB is that the main H-bridge is commutated with fundamental frequency, passing the majority of the inverter power. However, the isolated dc/dc converter needs to be connected to the main voltage source with high-voltage/high-frequency switches, which limits the power capability and the efficiency of the converter. In this paper, a switching pattern based on nearest level modulation method is proposed to command all the power to be transferred through the main H-bridge. Therefore, the power circulates between the auxiliary H-bridges with no need for high-voltage switches. As a result, a single-input single-output auxiliary converter is needed with only 5% of the power rating. This solution reduces cost and size while it improves the efficiency of the converter. Furthermore, the architecture makes the inverter more suitable for high power and high-voltage applications. The inverter switching strategy is based on programmable firing angles. The main dc-link of the grid connected inverter is controlled to achieve maximum power point tracking, while the dc/dc isolated converter is controlled to regulate the auxiliary dc-links. The proposed topology is verified by simulation and experimental results using a 1.5 kW hardware prototype. [ABSTRACT FROM AUTHOR]

This paper presents a novel single-stage soft-switched high-frequency-link three-phase dc–ac converter topology. The topology supports unidirectional dc to ac power flow and is targeted for applications like grid integration of photovoltaic sources, fuel cell, etc. The high frequency magnetic isolation results in reduction of system volume, weight, and cost. Sine-wave pulsewidth modulation is implemented in dc-side converter. Though high-frequency switched, dc-side converter is soft switched for most part of the line cycle. The ac-side converter active switches are line frequency switched incurring negligible switching loss. The line frequency switching of ac-side converter facilitates use of high voltage blocking inherently slow semiconductor devices to generate high voltage ac output. In addition, a cascaded multilevel structure is presented in this paper for direct medium-voltage ac grid integration. A detailed circuit analysis considering nonidealities like transformer leakage and switch capacitances, is presented in this paper. A 6-kW three-phase laboratory prototype is built. The presented simulation and experimental results verify the operation of the proposed topologies. [ABSTRACT FROM AUTHOR]

This paper presents a single-phase ac power supply circuit that based on modified voltage-fed quasi-Z-source inverter topology; it suits to the light or the heavy load and is fit for the resistive, inductive, or capacitive load. The topology, operating principle, voltage gain, control method, and its realization by DSP are described in this paper. The feasibility and rationality of the system is verified by the simulation and experimental results. [ABSTRACT FROM PUBLISHER]

This paper proposes a new fault-tolerant strategy to revamp performance of three-phase multilevel converters with a single faulty switch. The proposed fault-tolerant strategy is based on the application of a modified selective harmonic elimination (SHE) technique in conjunction with the fundamental phase-shift compensation method. The proposed fault-tolerant strategy makes the most use of the converter capacity in the faulty condition, generates balanced line voltages, and eliminates a wide range of lower order harmonics to limit the total harmonic distribution of the converter voltages in the faulty condition. In this paper, first, a brief background about cascaded H-bridge multilevel converters and SHE technique is provided. Then, the proposed fault-tolerant strategy and the modified SHE technique are presented. Finally, several experimental results are provided to validate the operation of the proposed strategy. [ABSTRACT FROM PUBLISHER]

Back-to-back converters have been typically used to interconnect microgrids. For a back-to-back current-source converter, the dc-link current ripple is one of the important parameters. A large ripple will cause electromagnetic interference, undesirable high-frequency losses, and system instability. Conventionally, with a given switching frequency and rated voltage, the current ripple can be reduced by increasing the dc-link inductor, but it leads to bulky size, high cost, and slow dynamic response. To solve this problem, this paper reveals that the current ripple can be significantly reduced by adjusting the gate patterns of space vector modulation between the rectifier and the inverter in a back-to-back converter. The experimental results verify the effectiveness of the proposed method. [ABSTRACT FROM PUBLISHER]

To support the development of high-frequency ac microgrids in terms of compact design, high-voltage gain and low total harmonic distortion (THD), a buck–boost dual-leg-integrated step-up inverter is proposed in this paper. The inverter is formed by integrating a buck–boost converter into a conventional single-phase full-bridge inverter by sharing the upper switch and the body diode of the lower switch in both bridge-legs. Consequently, the component count is significantly reduced over the step-up inverter counterparts. In addition, to address the drawbacks of hybrid modulation methods adopted by existing dual-leg-integrated inverters, such as double-variable control, and high THD of output voltage/current at high input voltage and heavy load conditions, unipolar frequency doubling sinusoidal pulse width modulation scheme is adopted in this inverter. As a result, the modulation ratio M becomes the only control variable to regulate the output voltage/current and the control is simplified. The THD of the proposed inverter output can remain low throughout the entire input voltage range and load power range. This paper presents the topology derivation procedure, operation principle, and steady-state characteristics of the proposed inverter. To validate the effectiveness of theory, experimental results of a 400 W hardware prototype, where the output voltage frequency is at 500 Hz, are reported. [ABSTRACT FROM PUBLISHER]

This paper proposes a current-fed single-phase inverter without constant intermediate DC link. It eliminates electrolytic capacitor from the DC-link and introduces an intermediate pulsating DC bus. The proposed topology is modular with three full-bridges making it scalable for high-power applications. New pulsating-DC-modulation for back-end pulsating DC-link inverter and secondary modulation (SM) for front-end DC-to-pulsating DC converter is proposed. Soft-switching and device voltage clamping of both primary side and secondary side devices of front-end current-fed full-bridge converter is realized. A rotating partial hybrid pulsewidth modulation has been introduced. One leg of inverter is commutated at a low switching frequency, while the other leg is operated at a high switching frequency for partial period of a line frequency cycle. Thus, switching losses of the back-end inverter are considerably reduced. Rotating mechanism is used to equalize the switching losses of four switches of the inverter. This paper presents detailed operation and analysis of the topology with a proposed modulation scheme. Simulation and experimental results validate the effectiveness and accuracy of the proposed modulation scheme as well as soft-switching and performance of the converter. [ABSTRACT FROM PUBLISHER]

This paper investigates and evaluates the performance of a single-phase split-source inverter (SSI), where an alternative unidirectional dc–ac configuration is used. Such configuration is utilized in order to use two common-cathode diodes in a single device instead of using two separate diodes, resulting in minimum parasitic inductance in the commutation paths. In this paper, the analysis and modulation of the single-phase SSI using this alternative configuration is discussed, and the analysis of the low-frequency component in the dc side is introduced. Moreover, the features behind employing the triangular, the trailing-edge sawtooth, and the leading-edge sawtooth carriers with the single-phase SSI are discussed, and the differences among these carriers are highlighted. In order to highlight the performance of the proposed SSI, a comparative study is conducted with the two-stage architecture and the single-phase quasi-Z-source inverter (qZSI). The introduced analysis is enhanced with simulation results using MATLAB/PLECS models, where a 1-kVA single-phase SSI is designed and simulated. Finally, the designed 1-kVA single-phase SSI is implemented experimentally and tested at different operating points, i.e., at different voltage gains, and a maximum efficiency of $95.5\%$ is obtained. [ABSTRACT FROM PUBLISHER]

Finite state model predictive control (MPC) has been recently applied to several converter topologies, as it can provide many advantages over other MPC techniques. The advantages of MPC include fast dynamics, multitarget control capability, and relatively easy implementation on digital control platforms. However, its inherent variable switching frequency and lower steady-state waveform quality with respect to standard control, which includes an appropriate modulation technique, represent a limitation to its applicability. Modulated model predictive control (M2 PC) combines all the advantages of MPC with the fixed switching frequency characteristic of pulse-width modulation algorithms. The work presented in this paper focuses on the indirect matrix converter (IMC), where the tight coupling between rectifier stage and inverter stage has to be taken into account in the M2PC design. This paper proposes an M2PC solution, suitable for IMC, with a switching pattern that emulates the desired waveform quality features of space vector modulation for matrix converters. The switching sequences of the rectifier stage and inverter stage are rearranged in order to always achieve zero-current switching on the rectifier stage, thus simplifying the current commutation strategy. [ABSTRACT FROM AUTHOR]

Connecting legs in parallel in a voltage source inverter is a way to increase the output current and, thus, its rated power. The connection can be made using either coupled or uncoupled inductors, and achieving an even contribution to the output current from all the legs is a crucial issue. Circulating currents produce additional losses and stress to the power devices of the converter. Therefore, they should be controlled and minimized. An efficient technique to attain such balance when coupled inductors are used is presented in this paper. The proposed technique can also be used when the inductors are uncoupled, since it is a particular case where the coupling coefficients are zero. This technique does not include proportional–integral controllers and does not require any parameter tuning either. The exact control action needed to reach current balance is straightforwardly calculated and applied. Experimental results are shown in this paper to verify the efficiency of the proposed balancing method. [ABSTRACT FROM PUBLISHER]

Efficient power conversion technologies are strategic to the advancement of fuel cell vehicles (FCVs). This paper presents an overview of power conditioning system (PCS) architectures for an FCV propulsion system. Two new power conversion topologies to obtain variable ac from the fuel cell system are proposed. The switching of the power devices are based on the proposed hybrid modulation technique that minimizes the switching losses in the inverter. The proposed converters do not use the dc-link filter capacitors. Elimination of the dc-link capacitor not only reduces the size and volume but also helps in retaining the sine wave modulated information at the input of a three-phase inverter. Bidirectional converter topologies are proposed for interfacing low-voltage battery and fuel cell dc bus. Experimental results are presented for the proposed topologies. [ABSTRACT FROM AUTHOR]

This paper presents an asymmetrical cascaded multilevel inverter based on a five-level transistor-clamped H-bridge power cell. A two-cell configuration with a dc link voltage ratio of 4 : 1 is presented. The modulation method is based on the fundamental frequency switching. An analysis of the inverter output voltage and harmonics is presented. Injection of the third harmonic voltage as to maximize the output voltage and the issue of the inverse power flow or regeneration in the low-voltage cell are presented. The prototype of the proposed inverter was built, and its functionality was verified through experimental results. [ABSTRACT FROM AUTHOR]

In this paper, a new T-type inverter topology based on multistate switching cell is proposed. The topology presents five-level voltage before the output $LC$ filter, providing high-order harmonics that are easily filtered. In this topology, the output filter ripple frequency is twice the switching frequency, therefore reducing the magnetic weight and volume. Other characteristics of the inverter are current sharing through the devices, facilitating its losses' dissipation, due to increased contact area and few involved components in the current flow path. In order to verify its feasibility, a design example, as well as experimental results, for a 5-kW prototype is presented in this paper. [ABSTRACT FROM AUTHOR]

This paper proposes an analytical procedure for computation of all pairs of valid switching angles used in pattern generation in five-level H-bridge cascaded inverters. The proposed procedure eliminates harmonic components from inverter output voltage and, for each harmonic, returns the exact boundaries of all valid modulation index intervals. Due to its simple mathematical formulation, it can be easily implemented in real time using a digital signal processor or a field-programmable gate array. In this paper, after a detailed description of the method, simulation and experimental results demonstrate the high quality of achievable results. [ABSTRACT FROM PUBLISHER]

This paper proposes a new inverter topology based on the active neutral-point-clamped (ANPC) converter with capability to integrate one energy storage system (ESS) per inverter leg with an independent state of charge control, so that each inverter leg has two dc ports and one ac port. The primary dc port is common to all inverter legs and it is connected to the main power source. The secondary dc port is suitable for ESS connection because of its two-quadrant operation, with bidirectional current capability, so that the ESS can be charged and discharged with regulated current. Integration of a secondary dc port with independent control also allows the use of different ESS technologies for each inverter leg to compose a hybrid ESS. Redundant switching states of the proposed structure are used to balance the energy exchanged between the secondary dc port and the dc bus capacitors. Theoretical propositions were experimentally validated through a 1-kW single-phase inverter with a secondary dc port connected to a 230-V ESS and ac port connected to an LC filter feeding a linear load. Low total harmonic distortion (THD) sinusoidal current is generated at the ac port while charging or discharging the ESS with a constant current. [ABSTRACT FROM AUTHOR]

In this paper, a new space vector pulse width modulation method to extend the linear modulation range of a cascaded five level inverter topology with a single dc supply is presented. Using this method, the inverter can be controlled linearly and the peak phase fundamental output voltage of the inverter can be increased from 0.577 to 0.637 V\text{dc} without increasing the dc bus voltage and without exceeding the induction motor voltage rating. This new technique makes use of cascaded inverter pole voltage redundancy and property of the space vector structure for its operation. Using this, the induction motor drive can be operated till the full speed range (0–50 Hz) with the elimination of lower order harmonics in the phase voltage and phase current. The five-level topology presented in this paper is realized by cascading a two-level inverter and two full bridge modules with floating capacitors. The inverter topology and its operation for extending the modulation range is analyzed extensively. Simulation and experimental results for both steady-state and dynamic operating conditions are presented in this paper. [ABSTRACT FROM AUTHOR]

Increasing demands for power supplies have contributed to the population of high-frequency ac (HFAC) power distribution system (PDS), and in order to increase the power capacity, multilevel inverters (MLIs) frequently serving as the high-frequency (HF) source-stage have obtained a prominent development. Existing MLIs commonly use more than one voltage source or a great number of power devices to enlarge the level numbers, and HF modulation (HFM) methods are usually adopted to decrease the total harmonic distortion (THD). All of these have increased the complexity and decreased the efficiency for the conversion from dc to HF ac. In this paper, a nine-level inverter employing only one input source and fewer components is proposed for HFAC PDS. It makes full use of the conversion of series and parallel connections of one voltage source and two capacitors to realize nine output levels, thus lower THD can be obtained without HFM methods. The voltage stress on power devices is relatively relieved, which has broadened its range of applications as well. Moreover, the proposed nine-level inverter is equipped with the inherent self-voltage balancing ability, thus the modulation algorithm gets simplified. The circuit structure, modulation method, capacitor calculation, loss analysis, and performance comparisons are presented in this paper, and all the superior performances of the proposed nine-level inverter are verified by simulation and experimental prototypes with rated output power of 200 W. The accordance of theoretical analysis, simulation, and experimental results confirms the feasibility of proposed nine-level inverter. [ABSTRACT FROM AUTHOR]

This paper proposes a new fault-tolerant strategy for the purpose of revamping the performance of three-phase multilevel (ML) converters with faulty switches. The proposed fault-tolerant strategy is based on an adaptation of the modified space vector modulation (SVM) technique to the fundamental phase-shift compensation method. The proposed fault-tolerant strategy generates balanced line-to-line voltages with increased voltage levels in the faulty condition. In this paper, first a brief background about cascaded H-bridge (CHB) ML converters and SVM technique is provided. Then the proposed fault-tolerant strategy and the modified SVM technique are presented. Finally, several experimental results are provided to validate operation of the proposed strategy. [ABSTRACT FROM AUTHOR]

Aimed at the problem that the auxiliary commutation circuit (ACC) of auxiliary resonant commutated pole (ARCP) inverters has a high loss in commutation processes, this paper presents a novel modulation strategy with shunt dead time based on a double ARCP (DARCP) inverter. In comparison with the original modulation strategy, this modulation strategy cannot only achieve soft switching for all switches, but also avoid the superposition of resonance current and load current at commutation moments in double ACCs (DACCs) and make the maximum current through DACCs approximately equal to load current in commutation processes. So, the circulating current loss in DACCs and the current stress of auxiliary switches can be effectively reduced. According to the equivalent circuits in different operation modes under the novel modulation strategy, this paper analyzes the operation principle, soft-switching implementation condition, and optimal parameter design procedure of the DARCP inverter. Finally, a 10-kW–16-kHz DARCP inverter prototype with insulated gate bipolar transistor-based switches is built. Experimental results are given to demonstrate the validity and features of the DARCP inverter under the novel modulation strategy. [ABSTRACT FROM AUTHOR]

Common-mode voltage (CMV) in voltage-source inverters (VSIs) has been well defined and is frequently referred to in the literature. While often referred to, there is no real consistency with respect to how the CMV properties of an individual modulation scheme are evaluated, lacking tools to assess the relative merits or disadvantages of a certain topology or modification of a control scheme. The way that it is analyzed is still mostly a matter of the different authors' foci. In this paper, we propose a metric for the analysis of the CMV, aiming to fill the aforementioned gap. Thereby, the CMV in VSIs is quantified by the number of possible levels and the step sizes between different levels, as well as the respective frequencies of occurrence. The first two are given by the number of levels and the number of phases of the inverter. Depending on the modulation (control) schemes, all possibly available levels or a few of these levels are present in the CMV. We illustrate the use of the tool by applying it to thoroughly study the CMV properties intrinsic to the topologies of multilevel multiphase single- as well as double-ended diode-clamped VSI drive systems. As part of this analysis, we uncover new relationships concerning the existence of zero CMV level. Furthermore, we exemplarily apply the developed tool to the assessment of the CMV properties of selected pulse width modulation (PWM) control schemes and translate the findings into an interpretation of the endangerment of a given drive to suffer damage from inverter-induced bearing currents. The theoretical findings are supported by measurements. This paper also reviews the literature on CMV in multilevel multiphase VSI systems. With the proposed metric in mind, the CMV being mostly discussed as an element of different foci becomes even clearer, confirming again the need for the development of such a tool. [ABSTRACT FROM AUTHOR]

A variable switching frequency space vector modulation control method is proposed in this paper. It is used to achieve zero-voltage switching (ZVS) for two parallel 180° interleaved three-phase grid-connected voltage-source inverters at unity power factor. A wide range of ZVS can be achieved without any additional sensor, auxiliary circuit, or current zero-crossing detection circuit. The carrier wave frequency is easy to be calculated and updated with digital control. The current ripple is precisely predicted and controlled to minimize unnecessary circulation loss. The high current ripple at the inverter side can be considerably canceled by the parallel interleaved configuration. LCL filter is used to further attenuate the current ripple and improve the power quality at the grid side. The switching loss can be significantly reduced especially by using a wide bandgap device with low turn-off loss. The power density is greatly improved owing to the high switching frequency and low component parameters of the filter. A 4.5-kW simulation and experimental prototype interfacing 400 V dc with a three-phase 110-V ac grid is developed to verify the performance of the proposed control strategy. [ABSTRACT FROM AUTHOR]

Leakage current reduction is one of the important issues for transformerless photovoltaic (PV) systems. Many interesting solutions have been reported to reduce the leakage current for three-phase PV inverters. However, most of them are limited to two-level inverters. Moreover, there is a potential risk of the overcurrent phenomenon. In order to solve the problem, a Z-source three-level four-leg inverter with a new modulation strategy is proposed in this paper. First, the mathematical modeling of the three-level four-leg Z-source inverter for leakage current reduction is established for the first time. Second, a new carrier-based modulation strategy is proposed by utilizing the effective large, medium, small, and zero vectors, instead of the invalid vectors, to achieve the constant common-mode voltage, as well as the leakage current suppression. Finally, the proposed solution is carried out on the Texas Instruments TMS320F28335 DSP + Xilinx XC3400 field-programmable gate array digital control hardware platform. The experimental results verify the effectiveness of the proposed solution. [ABSTRACT FROM AUTHOR]

This paper explores the issue of the neutral-point oscillation in the four-leg neutral-point clamped inverter. Such an issue is closely associated with the neutral-point current, so this study models the inverter on the dc side to clarify its relationship and presents a three-dimension pulsewidth modulation to eliminate the neutral-point oscillation. In addition, an offset-injection approach to reducing the neutral-point oscillation is also investigated and discussed. The laboratory test results will validate the analysis of the proposed approach, and a discussion will be presented to evaluate the effectiveness of eliminating the neutral-point oscillation. [ABSTRACT FROM AUTHOR]

Paralleled inverters have the merits of high power rating, improved reliability, and convenient maintenance. However, zero-sequence circulating current (ZSCC) will occur and lead to current distortion and system loss. The ZSCC control is more complicated when three-level topology is utilized and paralleled number is increased. Therefore, this paper proposes a simplified ZSCC suppression scheme for multi-paralleled three-level T-type inverters (3LT2Is). A novel equivalent model is developed and the ZSCC controller based on the new model is easier to implement. Thus, the number of paralleled inverters can be increased without complicating the control scheme and the inverters could be switched on or off optionally. Besides, Feed-Forward (FF) strategy is adopted to eliminate the ZSCC spikes caused by symmetrical three-level space vector modulation. The effectiveness of the proposed control scheme is verified by both simulation and experimental results. [ABSTRACT FROM AUTHOR]

This paper presents new space vector pulsewidth modulation (PWM) strategies for a single-phase three-level buck-boost neutral point clamped inverter coupled with impedance-source (IS) network. These strategies can be implemented for systems with any IS network with neutral point. The case study system is based on the quasi-Z-source inverter with continuous input current. To demonstrate an improved performance, the strategies are compared with a traditional PWM strategy. The advantages lie in reduced switching number, without output voltage quality distortion. The simulation and experimental results confirm the theoretical predictions. [ABSTRACT FROM AUTHOR]

In this paper, a new zero-sequence current suppression control strategy for the five-phase open-winding fault-tolerant fractional-slot concentrated-winding interior-permanent-magnet (FTFSCW-IPM) motor drive system with a common dc bus is proposed. By unequal distribution of the zero voltage vector, the proposed method can well suppress the zero-sequence current caused by the dead-time effect that the conventional eliminating method cannot be achieved. First, the dead-time effect to the zero-sequence current is discussed. Then the zero-axis controller is designed to obtain the reference common-mode voltage. Last, according to the principle of the unequal zero voltage vector distribution, the switching sequence of the two inverters can be calculated, and the maximum modulation index is also first deduced in detail. The proposed method is proved by the simulation and experimental results. [ABSTRACT FROM AUTHOR]

In this paper, a modified selective harmonic mitigation pulse amplitude modulation (SHM-PAM) is presented to be capable of canceling all triplen harmonic orders and suitable for single-phase application of five-level type of voltage source inverters. To this end, a new constraint is established for the two switching angles (α1, α2) to derive the new formula for the harmonics’ amplitude, which results in self-elimination of all triplen harmonics (e.g., 3rd, 9th, 15th, …). The fifth and seventh harmonic orders are mitigated through normal operation of the proposed SHM-PAM technique. It is also shown that the proposed technique is extendable to other multilevel voltage waveforms and a flowchart of self-elimination of all triplen harmonics has been presented. Mathematical analysis supported by experimental investigations show the desired performance of the proposed SHM-PAM algorithm on a two-cell single-phase cascaded H-bridge inverter as a typical five-level configuration in dealing with linear and nonlinear loads. Then, it is demonstrated that the maximum number of harmonic orders would be controlled with the minimum number of available angles in a low switching frequency voltage waveform. [ABSTRACT FROM AUTHOR]

This paper proposes advanced speed control for a five-leg voltage source inverter (FLVSI) that drives the dual three-phase induction motor system used in industrial manufacturing processes. The advanced speed control method consists of two controllers: 1) The first is a slip controller that satisfies the application requirement, i.e., to control the mechanical speed of two motors equally regardless of the load condition. 2) The second is an angle controller that satisfies the FLVSI requirement, i.e., to control the phase angle difference between the two motors for minimizing the common leg current because the common leg current can be twice higher than other leg's current depending on the operation condition of the dual motor. Stability analysis of the two controllers under advanced speed control is implemented, and the whole performance of the advanced speed control for the FLVSI-fed dual-motor drive system is shown to identify its feasibility through the experimental results. [ABSTRACT FROM AUTHOR]

In this paper, a novel space vector modulation (SVM) strategy is proposed and designed for dual three-phase three-level motor drives based on vector space decomposition (VSD), which could be applied for high-power and high-reliability applications. The key of the proposed method is to design two decoupled groups of voltage vector candidates for synthesis on α − β subspace and x − y subspace, respectively. The two decoupled groups of voltage vectors will synthesize respective voltage references on α − β subspace and x − y subspace, while having no impact on each other. The redundant small voltage vectors and zero-sequence voltage vectors are utilized to mitigate voltage oscillation in midpoint of dc link and suppress zero-sequence current component for dual three-phase windings with a common neutral. For comparison, another VSD-SVM strategy is designed based on traditional solution, which cannot offer closed-loop control on x − y subspace. Both simulation and experiments have been given to verify that the proposed decoupled VSD-SVM can suppress harmonic components on x − y subspace besides tracking torque components on α − β subspace. Furthermore, the harmonic performance of the proposed decoupled VSD-SVM has been compared with the traditional VSD-SVM strategy and the carrier disposition based pulsewidth modulation. [ABSTRACT FROM AUTHOR]

This paper investigates the open-circuit faults of switching devices in the three-level T-Type inverter and proposes a new tolerant control method. The three-phase current and variation of the neutral-point voltage are detected to determine the fault switch. A carrier-based pulse width modulation is developed to tolerate switch fault by transiting from three-level to two-level switching. This makes the modulation scheme easier to be implemented compared to space vector modulation. For the neutral-point fault, the fault phase is operated by two-level modulation to produce the same rating voltage. On the other hand, the inverter is able to produce balanced voltage with reduced rating by keeping the phase of half-bridge fault to the neutral-point voltage. The neutral-point voltage is also able to be balanced by using two-level modulation since it does not contribute the neutral-point current. The performance and effectiveness of the proposed tolerant control are verified by a laboratory build. [ABSTRACT FROM AUTHOR]

In this paper, angular modulation index (AMI) implemented through a modified space vector modulation for the dual voltage source inverters (VSI) is proposed with the primarily aiming to reduce switching losses. The desired voltage across the load is synthesized by applying appropriate phase-angle displacement between space vector references. The proposed approach avoids the use of a dc/dc boost converter (which imposes loss and weight/price penalty to duplicate the dc-link voltage) and results to be particularly suitable for electrical/hybrid vehicle applications. Namely, the application of saving energy to keep driving has been identified as major concern. Hence, this work focuses on the strategy to enhance efficiency. The principles of the proposed controlling method and switching loss, which is reduced at least by 50%, are theoretically evaluated. This paper proposes a pioneering mathematical approach to correctly determine total harmonic distortion (THD) value of the voltage/current for the dual-VSI structure. Furthermore, simulation and experimental results prove that the proposed method insures benefits in terms of common-mode voltage, THD of the voltage, and switching loss reduction. The dual-VSI prototype supplying 1.5-kW induction motor is assembled in the laboratory to experimentally evaluate performance of the proposed method. Also, the simulation results carried out through MATLAB/Simulink environment are given to confirm performance of this easy-to-implement and high-efficient method. [ABSTRACT FROM PUBLISHER]

This paper presents a new application of power and voltage balance control schemes for the cascaded H-bridge multilevel inverter (CHMI)-based solid-state transformer (SST) topology. To reduce load on the controller and simplify modulation algorithm, a master–slave control (MSC) strategy is designed for the dual active bridge (DAB) stage. The master controller executes all control and modulation calculations, and the slave controllers manage only device switching and protection. Due to the inherent power and dc-link voltage unbalance in cascaded H-bridge-based SST, this paper presents a compensation strategy based on three-phase dq decoupled current controller. An optimum zero-sequence component is injected in the modulation scheme so that the three-phase grid currents are balanced. Furthermore, to tightly regulate the output voltage of all the DAB modules to target value, a dynamic reference voltage method is also implemented. With this proposed control method, the three-phase grid currents and dc-link voltage in each module can be simultaneously balanced. Finally, simulation and experimental results are presented to validate the performance of the controller and its application to microgrid SST. [ABSTRACT FROM PUBLISHER]

In this paper, two modulation strategies called Mod-1 and Mod-2 are compared for a three-level diode neutral-point-clamped (NPC) inverter synchronous reluctance machine (SynRM) drive. These modulation strategies do not operate at a fixed switching frequency. A new modulation strategy which operates at a fixed switching frequency is proposed called Mod-3. The SynRM suffers from a poor power factor which makes it harder to archive capacitor voltage balancing for a three-level NPC inverter. These modulation strategies are of the nearest three vector (NTV) family. Mod-1 and Mod-3 choose certain vector states to achieve capacitor voltage balancing, whereas Mod-2 strategy makes use of the inverter vector state’s dwell time. The parameters of interest are the torque ripple, the neutral point (NP) voltage ripple, the inverter efficiency, and the $d$-axis current ripple. Though lower torque ripple and better power quality are registered on Mod-2 strategy. Mod-1 strategy has 14% improvement in inverter efficiency at lower modulation index ($m_i = 0.4$). Mod-2 strategy has 11% more NP voltage ripple at a modulation index of 0.4. One of the disadvantages of Mod-1 strategy is the varying switching frequency. Mod-3 scheme produced higher inverter efficiency, better balancing of the capacitor voltages, and guaranteed fixed inverter switching frequency. The disadvantage with Mod-3 strategy is that it generated higher torque ripple, $d$-axis current ripple, and current total harmonic distortion when compared to Mod-1 and Mod-2 at the same load conditions. [ABSTRACT FROM AUTHOR]

A digital dead-beat current controller for voltage source converters is presented in this paper. The control structure is specified in a digital hardware description language, synthesized, and deployed on a field-programmable gate array chip. By updating, with negligible computation delay, the duty cycle twice in a switching period, the reference current error is nulled in half a modulation period, so that the controller's small-signal bandwidth is maximized. In addition, due to a simple transient detection circuit, the large-signal response delay is reduced to a small fraction of the modulation period, which is determined by the chosen current signal oversampling rate. The controller can effectively support different voltage-source inverter applications, such as active filters, uninterruptible power supplies, microgrid distributed energy resource controllers, and dc–dc converter applications, including interface converters for renewable energy sources, laboratory battery chargers, and electronic welding machines. [ABSTRACT FROM AUTHOR]

A virtual space vector modulation technique reducing both magnitude and third-order harmonic component of the common-mode voltage (CMV) in a two-level voltage-source inverter (VSI) is proposed in this paper. The presented method employs a set of virtual space vectors constructed from original stationary space vectors to conduct modulation. Since the created virtual vectors have the lowest instantaneous and zero average CMVs, both the magnitude and third-order harmonic component of the generated CMV are reduced, contributing to better overall CMV performance and common-mode filter design in VSI applications. Three variants of the proposed modulation method using different virtual space vector combinations are presented. The concept of the virtual space vector modulation technique demonstrated with two-level inverter in this paper can also be extended to multilevel inverters. Simulation and experimental results, as well as comparisons with existing methods are provided to verify the proposed technique. [ABSTRACT FROM AUTHOR]

Multiphase machines are well known for their fault-tolerant capability. Star-connected multiphase machines have fault tolerance in an open circuit. For an inverter switch short-circuit fault, it is possible to keep a smooth torque of a permanent magnet synchronous machine if the currents of the faulty phases are determined and their values are acceptable. This paper investigates fault-tolerant operations of an open-end five-phase drive, i.e., a multiphase machine fed with a dual-inverter supply. Inverter switch short-circuit fault is considered and handled with a simple solution. Original theoretical developments are presented. Simulation and experimental results validate the proposed strategy. [ABSTRACT FROM AUTHOR]

In order to solve the neutral-point voltage unbalancing problem for three-level inverters, this paper proposes a method to balance the neutral-point voltage for three-level inverters with variable modulation wave offset sinusoidal pulse-width modulation (SPWM) control. Based on the mathematical expressions of neutral-point voltage unbalancing, the factors are studied, which affect the fluctuation of neutral-point voltage. Theoretically the mathematical expressions of the neutral-point voltage with the proposed method are derived, and the mathematical relationship between the fluctuation of neutral-point voltage and the adjusting offset of modulation wave is studied. This proposed method realizes controlling the neutral-point voltage balance by dynamically calculating the offset superimposed to the modulation wave based on SPWM (DCOSPWM). This DCOSPWM method is very simple, which has good steady-state performance and is easy for digital implementation. The simulation results verify the correctness of the theoretical analysis in this paper, and the feasibility and effectiveness of this method is verified by the experiments in the experimental platform of neutral point clamped three-level inverters based on digital signal processor (DSP)-complex programmable logic device (CPLD). [ABSTRACT FROM AUTHOR]

Common-mode voltage (CMV) is one of the most important issues for the power electronics inverters. An interesting space vector modulation of the three-leg current-source inverter has been reported for the CMV reduction recently. However, it has the disadvantages of the bipolar current pulses and modulation index range limitation. In order to solve these problems, a four-leg current-source inverter with a new space vector modulation is proposed in this paper. With the proposed method, the system CMV can be significantly reduced without bipolar current pulses and modulation index range limitation. Finally, the experimental tests are carried out on a four-leg current-source inverter, and the experimental results verify the effectiveness of the proposed method. [ABSTRACT FROM PUBLISHER]

This paper proposes a method to reduce the low-frequency neutral-point voltage oscillations. The neutral-point voltage oscillations are considerably reduced by adding a time offset to the three-phase turn-on times. The proper time offset is simply calculated considering the phase currents and dwell time of small- and medium-voltage vectors. However, if the power factor is lower, there is a limitation to eliminate neutral-point oscillations. In this case, the proposed method can be improved by changing the switching sequence properly. Additionally, a method for neutral-point voltage balancing is also proposed. The change in switching frequency by the proposed method and its effects on the outputs are negligible. Simulation and experimental results verify the validity and feasibility of the proposed strategy. [ABSTRACT FROM PUBLISHER]

Space vector modulation (SVM) of a Z-source ultrasparse matrix converter (ZSUSMC) can be realized by either using or not using a zero state in the space vector rectification. In this paper, these two modulation schemes are investigated for a cascaded ZSUSMC. It is demonstrated that the input current under the modulation scheme without a zero state is nonsinusoidal, and its harmonics content depends on the output and impedance network inductor currents. In addition, restrictions on operation of the ZSUSMC with low voltage gains are unveiled. Next, aiming at improving the input current quality and suppressing the harmonics content to an acceptable level, an approach for design of the cascaded Z-source network is proposed. Furthermore, an optimal switching pattern, which results in minimum possible number of changes in the switching states of the ZSUSMC, is developed. Using the developed switching pattern, an approach for digital implementation of the SVM schemes on a single conventional digital signal processor (DSP) without employing an additional field programmable gate array is proposed. Hardware-in-the-loop studies of the ZSUSMC modulated under the proposed SVM schemes are carried out to verify their digital implementation feasibility on a conventional single DSP, as well as effectiveness in producing high-quality input/output currents. [ABSTRACT FROM AUTHOR]

Microinverters for grid-connected photovoltaic (PV) power conversion systems often require voltage boost due to the low dc voltage of the PV panels. A high-frequency (HF) transformer-isolated differential-mode Ćuk inverter (DMCI) is an attractive topology due to its inherent voltage boost capability and high power density. One of the significant operational issue of the DMCI addressed in this paper is the presence of lower order harmonic distortion in the injected grid current. It is shown that lower order odd and even harmonic voltages are generated with this topology. This problem is accentuated due to the low damping offered by the grid to harmonic voltages. A systematic low-complexity control design is proposed to address this issue. It is shown experimentally that the DMCI operates stably with effective attenuation of the lower order harmonics using the proposed design. Practical operational issues of the DMCI with fast switching GaN field-effect transistor (FET) devices are analyzed and solutions are proposed. It is shown that there can be significant HF noise generation in the DMCI with a frequency range higher than the switching frequency. Practical solutions for resolving HF issues using a combination of circuit layout design and additional passive components are proposed and validated. All of the experimental results are demonstrated on a 500-W GaN-FET-based microinverter prototype. [ABSTRACT FROM PUBLISHER]

Several single-stage topologies have been introduced since kicking off the three-phase Z-source inverter (ZSI), and among these topologies, the quasi-ZSI (qZSI) is the most common one due to its simple structure and continuous input current. Furthermore, different modulation strategies, utilizing multiple reference signals, have been developed as well. However, prior art modulation methods have some demerits, such as the complexity of generating the gate signals, the increased number of switch commutations with continuous commutation at high current level during the entire fundamental cycle, and the multiple commutations at a time. Hence, this paper proposes two modified space vector modulation strategies, aimed at the reduction of the qZSI number of switch commutations at high current level for shorter periods during the fundamental cycle, i.e., reducing the switching loss, simplifying the generation of the gate signals by utilizing only three reference signals, and achieving a single-switch commutation at a time. These modulation strategies are analyzed and compared to the conventional ones, where a reduced-scale 1-kVA three-phase qZSI is designed and simulated using these different modulation strategies. Finally, the 1-kVA three-phase qZSI is implemented experimentally to validate the performance of the proposed modulation strategies and verify the reported analysis. [ABSTRACT FROM PUBLISHER]

Space vector modulation (SVM) is a widely used method for multilevel inverters. Most of the SVM methods are nearest three vector (N3V) based schemes. Therefore, several researchers have proposed advanced implementation algorithms with reduced complexity for N3V methods. However, topologies like neutral point (NP) clamped inverter (NPCI) require some distinctive methods (called as non-N3V methods) to balance NP voltage for high modulation index and low power factor operations. Currently, the existing non-N3V methods exercise highly complex algorithms for duty ratio calculation and subtriangle identification. This paper presents a new approach, suitable for both N3V and non-N3V methods, with reduced implementation complexity. The proposed algorithm is based on an equivalent two-level space vector diagram and does not require any trigonometry, coordinate transformation, or volt-second balance solution. Unlike other carrier-based methods, it can change the switching sequence as well as the duration of redundant vectors. Moreover, the proposed approach does not require extra steps for implementing hybrid modulation and it can also be extended to multilevel topologies. One N3V, two non-N3V, and hybrid methods are developed using the proposed modulation algorithm, and are compared in detail. Simulation and experimentation on a three-level NPCI verify the validity of the proposed algorithm. [ABSTRACT FROM PUBLISHER]

In this paper, finite-set model-predictive control (FS-MPC) methodologies for a grid-connected three-level neutral-point-clamped converter are investigated. The proposed control strategies produce fixed switching frequency, maintaining all the advantages of predictive control such as fast dynamic response, inclusion of nonlinearities and restrictions, and multivariable control using a single control loop. The first of the proposed FS-MPC strategies is based on a multiobjective cost function, designed to regulate both the inverter currents and the balancing of the dc-link capacitor voltages. The second FS-MPC strategy is derived from the first one, and it is based on a cost function that regulates only the grid current, with the balancing of the capacitor voltages being realized by controlling the duty cycles of the redundant vectors. The proposed control systems are experimentally validated using a 5-kW prototype. The experimental results show a good performance for both strategies, in steady-state and transient response, with a total harmonic distortion lower than \text2\% for the currents supplied to the grid. [ABSTRACT FROM PUBLISHER]