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This paper presents an approach to handle with elements from GF(2n), in hardware implementation with minimum costs of area. The method is described by exemplifying with minimum costs of area. The method is described by exemplifying the practical implementation of the BCH(n,k,t) scheme over GF(2n), where n is large (n > 6), on reconfigurable FPGA hardware with minimum costs of area. There are many papers in the open literature which presents hardware implementations of algorithms over GF(2n) but none of them addresses the problem of hardware resources employed. There are many situations in which an area optimized implementation is more suitable than a speed optimized implementation. [ABSTRACT FROM AUTHOR]