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This article presents an introduction to research papers presented at the ARCS02 Conference. Future processors become smaller, provide higher performance and consume less power than today's devices. Such processors will spark off new applications in particular in the area of everyday consumer devices. The International Conference on Architecture of Computing Systems ARCS02 was held in Karlsruhe, Germany from April 8-11, 2002, with the special focus on "Trends in Network and Pervasive Computing."

Information about upcoming events of interest to Computer Society members. [ABSTRACT FROM PUBLISHER]

This work exposes a new paradigm for the creation and publication of textbooks: open source. The phrase open source is borrowed from the computer software industry, where the word source has a technical meaning explained in this paper; open source software is software which has been developed by many collaborators using the internet to produce a final product. The contributors receive no financial compensation, yet there have been many successful open source software projects (Linux, Open Office, Apache, etc.). Open source textbooks use a similar financial model; the authors and contributors receive no direct financial compensation for their work. Contributors are listed in the produced work as primary author(s), co-authors, contributors, minor contributors, etc. according to the magnitude of their contribution. The produced work is available free for users on the internet. This paper will explain the open source process and will provide justification for open source as an effective paradigm; it will also present some existing open source textbook projects, as well as the author's own open source textbook project. [ABSTRACT FROM AUTHOR]

When making a schedule in a home help station the scheduler has to ensure each service can be provided on time by an appropriate helper. The scheduler must consider the working hours and intensity of the work, the traveling time to and from the users' home and the availability of each helper to complete a schedule. This scheduling is known to be difficult and time consuming due to the quantity of such constraints. Although computer-aided support systems are commercially available, it was found that such systems are not being utilized to obtain feasible schedules. In this paper, in order to understand what kind of system is needed, we made observations of the schedulers creating schedules on paper by hand. We then observed schedulers using a computer-aided support system in order to capture the issues involved using the computer systems. From the observations, we summarize several requirements that are needed to develop a useful computer system. [ABSTRACT FROM AUTHOR]

Software reuse can be defined as the process of creating software products from the existing ones rather than developing software from scratch. Thus, software reuse is normally proposed to increase software productivity and quality and leads to economic benefits. In this sense, the reuse of software requirements has received important attention because it provides a solid support to develop quality software through obtaining and reusing quality software requirements [i.e., software product line (SPL) approach used in large-sized software enterprises]. However, the small-sized enterprises-which represent up to 85 % of all software organizations in many countries around the world-cannot implement a SPL approach because it does not fit with the context, properties, and complexity of their software projects. Moreover, the software engineering community has not adequately explored a more proper approach in the context of small-sized software enterprises. The use of a software requirements catalog could be this proper approach. In this context, the aim of this paper was to introduce the requirements reuse model for software requirements catalog (RRMSRC). Also, a set of guidelines to perform the main activities defined for reusing functional requirements within small-sized software enterprises is provided. As evidence of its feasibility, RRMSRC has been used in an industrial context, and the obtained results and learned lessons are summarized. [ABSTRACT FROM AUTHOR]

ess control is an important security issue. It has been addressed since the late 1960s in the early time-sharing computer systems. Many access control models have been proposed since than but of particular interest is Ferraiolo and Khun's role-based access control model (RBAC). It is a simple and yet general model which has been deeply studied and applied both in industry and in academia. A variety of industrial standards have been proposed based on this model. Generating code for an access control policy is an interesting challenge. Understanding access control as a non-functional concern that cross-cuts the functional part of a system raises difficulties quite suitable for a solution based on aspect-oriented programming. In this paper, we address the problems of specification and validation of code generation for access control policies targeting an aspect-based infra-structure. We propose an MDA approach. The code generator is a transformation from SecureUML, an RBAC-based modeling language, to the language Aspects for Access Control (AAC), an aspect-oriented modeling language proposed in this paper. Metamodels are used to represent the languages and to specify the transformation. A metamodel is used to represent the abstract syntax of a language and the constraints that a given instance model of the metamodel must fulfill. We also use a metamodel to specify the code generator. This transformation metamodel, together with all the constraints, that is, from both languages and those constraints regarding the merge of the two languages, we call a transformation contract. It merges and conservatively extends the source and target metamodels of the model transformation it represents. In the context of code-generation for access control policies, the transformation contract specifies the relationships between the abstract syntaxes of SecureUML and AAC and constrains the two languages. The validation of the code generator also uses the transformation contract. For a given access control policy and aspect, represented as instances of the appropriate metamodels, with aspects produced by the code generator, the constraints of the transformation contract must hold. We have prototyped a transformer from SecureUML to aspects on top of ITP/OCL, an OCL interpreter that automatically validates the generated aspect code by applying the constraints of the transformation contract. [ABSTRACT FROM AUTHOR]

Purpose - The purpose of this paper is to propose a new taxonomy for intrusion detection systems as a way of generating further research topics focussed on improving intrusion system performance. Design/methodology/approach - The paper shows that intrusion systems are characterised by the type of output they are capable of producing, such as intrusion/non-intrusion declarations, through to intrusion plan determination. The output type is combined with the data scale used to undertake the intrusion determination, to produce a two-dimensional intrusion matrix. Findings - The paper finds that different approaches to intrusion detection can produce different footprints on the intrusion matrix. Qualitative comparison of systems can be undertaken by examining the area covered within the footprint and the footprint overlap between systems. Quantitative comparison can be achieved in the areas of overlap. Research limitations/implications - The paper shows that the comparison of systems based on their footprint on the intrusion matrix may allow a deeper understanding of the limits of performance to be developed. The separation of what was previously understood as "detection" into the three areas of Detection, Recognition and Identification may provide further impetus for the development of a theoretical framework for intrusion systems. Practical implications - The paper shows that the intrusion matrix can be divided into areas in which the achievement of arbitrarily high performance is relatively easily achievable. Other areas within the matrix, such as the Prosecution and Enterprise regions, present significant practical difficulties and therefore are opportunities for further research. Originality/value - The use of a taxonomy based on the type of output produced by an intrusion system is new to this paper, as is the combination with data scale to produce an intrusion matrix. The recognition that the network data scale should also be split to differentiate trusted and untrusted networks is new and presents challenging opportunities for further research topics. [ABSTRACT FROM AUTHOR]

Purpose - The purpose of this paper is to propose a model for sharing network capacity on demand among different underloaded and overloaded P2P ROME-enabled networks. The paper aims to target networks of nodes with highly dynamic workload fluctuations that may experience a burst of traffic andlor massive nodes' failure rates. Design/methodology/approach - The paper shows that when locally available network capacity is not adequate for the workload requirements, the excessive capacity needs to be sought into other networks with more availability. A random flat P2P overlay of the ROME servers is used for the discovery and movement of nodes between two networks. Centralised or decentralised DHT-based directories of available nodes cannot cope with high workload fluctuations and frequent join/leave actions of nodes. The paper also introduces semantics to refine the answers to the ones with the most appropriate nodes for the requesting network and to find the requested capacity faster and more efficiently. The behaviour of the model is simulated to evaluate with several experiments the model based on some metrics. Findings - The paper finds that all the user queries of an overloaded underlying network are dropped if G-ROME is not used but as G.ROME overlay satisfies the requested capacity of a ROME server, its Chord ring size increases. In case of uniformly distributed and/or plentiful capacity over the overlay, shallow searches may give very good results. On the contrary, deeper searches are required for scarce capacity but the number of messages increases almost exponentially. Originality/value - This paper provides a model for moving the required resources to the requesting job environment rather than the job and its context to the resource. [ABSTRACT FROM AUTHOR]

This paper presents an analytical method for evaluating the reliability improvement for any size of multi-computer system based on Software-Implemented Fault-Tolerance (SIFT). The method is based on the equivalent failure rate r, the single node failure rate A, the number of nodes in the system, N, the repair rate Λ, the fault coverage factor c, the reconfiguration rate 6, and the percentage of blocking faults b1 and b2. The impact of these parameters on the reliability improvement has been evaluated for a gracefully degradable multi-computer system using our proposed analytical technique based on Markov chains. To validate our approach, we used the SIFT method which implements error detection at the node level, combined with a fast reconfiguration algorithm for avoiding faulty nodes. It is worth noting that the proposed method is applicable to any multi-computer systems' topology. The evaluation work presented in this paper focuses on the combination of analytical and experimental approaches, and more precisely on Markov chains. The SIFT method has been successfully implemented for a multi-computer system, nCube. The time overhead (reconfiguration & recomputation time) incurred by the injected fault, and the fault coverage factor c, are experimentally evaluated by means of a parallel version of the Software Object-Oriented Fault-Injection Tool (nSOFIT). The implemented SIFT approach can be used for real-time applications, when the time constraints should be met despite failures in the gracefully degradable multi-computer system. [ABSTRACT FROM AUTHOR]

Purpose - The purpose of this paper is to propose the use of priority-based incentives for collaborative hiding of confidential information in dynamic environments, such as self-organized networks, peer-to-peer systems, pervasive and grid computing applications. Design/methodology/approach - The paper documents the necessity of ISSON (Incentives for Secret-sharing in Self-Organised Networks); it provides functional and technical details on the proposed architecture; and, it assesses its feasibility in mobile ad-hoc networks through real experiments. The paper elaborates on the availability of the hidden information through an analytical framework. Findings - Through the real experiments, ISSON was found to be efficient in terms of communication and processing costs. Additionally, it avoids collusions for unauthorized revealing of the hidden information, and ensures the unlinkability and availability of the secret when it is divided and stored to peers. Originality/value - The proposed, incentive-based, privacy enforcement architecture is novel and applies to distributed, dynamic, and self-configured computing environments. [ABSTRACT FROM AUTHOR]

This paper describes the electrical architecture and design of the IBM eServer™ BladeCenter® midplane and media interface card. The midplane provides the redundant interconnects among processor blades, switch modules, media interface card, and management modules. It also serves as the redundant power distribution medium from the power modules to all blades and other devices. A major attribute of the BladeCenter electrical design is the redundant nature of the interconnects, which gives this product superior reliability and availability. The media interface card provides the interface between the CD-ROM and floppy disk drives and the blades that share these devices. The sharing of these devices was a key BladeCenter innovation. Also, to ensure that the architecture will be flexible enough to support multiple input/output fabric protocols, SerDes (serialized/deserialized) is used as the internal high-speed communication electrical interface. Since highspeed designs can easily result in higher implementation costs, a significant predesign simulation effort was undertaken to analyze and prioritize design guidelines in order to develop a high-speed midplane at a competitive cost. This paper highlights how we reduced board costs by finding solutions that overcame some of the challenges of 2.5-Gb/s data transmission over multiple printed circuit boards and connectors. [ABSTRACT FROM AUTHOR]

The management software for the IBM eServer™ BladeCenter® platform combines multiple management tools and technologies to create an integrated solution for managing, configuring, and deploying the chassis components and attached storage area networks. The IBM software also integrates BladeCenter platform management capabilities with other enterprise system management tools. This paper describes the architecture and capabilities of the IBM Director, Cluster Systems Manager, and Virtualization Enginee tools, which enable customers to configure, manage, and provision the BladeCenter system. These tools configure and monitor the chassis using out-of-band communications with the BladeCenter management module. Management agents installed on each processor blade provide in-band operating system monitoring and integration into enterprise management applications, such as IBM Tivoli® software. This paper includes a description of the management technologies and design innovations that assist the system administrator with management tasks such as discovery, blade and switch module configuration, asset inventory, out-of-band control, alerting and event actions, storage configuration, operating system installation, application deployment, and provisioning. [ABSTRACT FROM AUTHOR]

Software Process Technology evolved to support software processes management by assisting the modeling, enacting and evolution of complex process models. This paper presents a contribution to this field, describing a mechanism to formally model Static Policies, which are useful to automate the verification of user-defined process syntactical properties. The proposed mechanism acts during software process modeling, promoting the reuse of policy instances across different processes in a software organization. In this text, the language for Static Policy definition is presented first through its informal description, followed by examples. This paper also discusses some of the main issues related to the formal (algebraic) semantics defined for the Policy interpreter, which based the implementation of a Java-based prototype. [ABSTRACT FROM AUTHOR]

A recent trend in software engineering is the shift from a focus on laboratory-oriented software engineering to a more industry-oriented view of software engineering processes. This complements preceding ideas about software engineering in terms of organization and process-orientation. From the domain coverage point of view, many of the existing software engineering approaches have mainly concentrated on the technical aspects of software development. Important areas of software engineering, such as the technical and organizational infrastructures, have been left untouched. As software systems increase in scales, issues of complexity and professional practices become involved. Software development as an academic or laboratory activity, has to engage with software development as a key industrialized process. This expanded domain of software engineering exposes the limitations of existing methodologies that often address only individual subdomains. There is, therefore, a demand for an overarching approach that provide a basis for theoretical and practical infrastructures capable of accommodating the whole range of modern software engineering practices and requirements. One approach is provided by Process-Based Software Engineering (PBSE); part of the more general trend towards a focus on process. This paper provides a review of process techniques for software engineering and a high-level perspective on PBSE. Typical approaches and techniques for the establishment, assessment, improvement and bench-marking of software engineering process systems are introduced in this paper, and many are developed further in other contributions to this volume. [ABSTRACT FROM AUTHOR]

Programs for software reliability improvement based on measurements require the collection and analysis of comprehensive and consistent data sets on several software projects. In this paper, we put emphasis on data collection and analysis programs for software reliability improvement. We first present the objectives of data collection programs, report some success stories related to software reliability improvement, then discuss the practical aspects of data collection, validation and processing before giving recommendations for successful data collection and analysis programs. The success stories show that the gain in productivity and reliability is obtained at almost no extra cost, and even with an overall cost reduction most of the time. Data processing consists in performing statistical treatments. For reliability purposes, we consider three main activities: descriptive analysis, trend analysis, and reliability evaluation. The recommendations and examples of results, given at the end of the paper, are based on our experience in processing failure data collected on real-life software systems. We discuss in particular, the relevance of software reliability evaluation according to the life-cycle phase considered. [ABSTRACT FROM AUTHOR]

Several cost models have been proposed in the past for estimating, predicting, and analyzing the costs of software reuse. In this paper we propose an integrated ROI-based cost model which attempts to encompass existing models. Our approach is to analyze existing models, identify their dimensions of variance, classify the models along these dimensions, then provide an integrated cost model that makes explicit provisions for these dimensions of variance. In this paper, we also discuss in what sense our model encompasses existing models, present a prototype that supports the cost model, and illustrate the model with a sample example. [ABSTRACT FROM AUTHOR]

The development of complex distributed systems demands for the creation of suitable architectural styles (or paradigms) and related runtime infrastructures. An emerging style that is receiving increasing attention is based on the notion of event. In an event-based architecture, distributed software components interact by generating and consuming events. An event is the occurrence of some state change in a component of a software system, made visible to the external world. The occurrence of an event in a component is asynchronously notified to any other component that has declared some interest in it. This paradigm (usually called "publish/subscribe," from the names of the two basic operations that regulate the communication) holds the promise of supporting a flexible and effective interaction among highly reconfigurable, distributed software components. In the past two years, we have developed an object-oriented infrastructure called JEDI (Java Event-Based Distributed Infrastructure). JEDI supports the development and operation of event-based systems and has been used to implement a significant example of distributed system, namely, the OPSS workflow management system (WFMS). The paper illustrates the main features of JEDI and how we have used them to implement OPSS. Moreover, the paper provides an initial evaluation of our experiences in using the event-based architectural style and a classification of some of the event-based infrastructures presented in the literature. [ABSTRACT FROM AUTHOR]

Many safety-critical computer systems are required to monitor and control physical processes. The four-variable model, which has been used successfully in industry for almost four decades, helps to clarify the behaviors of, and the boundaries between the physical processes, input/output devices, and software. In this model, the acceptable behaviors of the software are constrained by the physical environment, system requirements, and input/output devices. If acceptable software behaviors are possible, then the system requirements are said to be implementable with respect to these constraints. The only acceptability condition proposed in the literature deems as acceptable software behaviors that can lead to undesirable system behaviors, in particular, nondeterministic system behaviors that for the same input sometimes do not produce any results and some other times produce expected results. In this sense, the acceptability condition can be seen as angelic. In this paper we strengthen the acceptability condition using the demonic calculus of relations such that no undesirable system or software behaviors are allowed and prove a necessary and sufficient implementability condition for the system requirements. As a byproduct, we also obtain a mathematical characterization of the least restrictive software specification, which, for all intents and purposes, can play the role of the software requirements. [ABSTRACT FROM AUTHOR]

Methodology of estimating the Hurst exponent using rescaled range method by use of Computer Algebra System "Mathematica" is presented. Depending of its value this measure of persistence indicates a random walk, "mean-reverting" series or trend reinforcing series. In this paper long-term memory of a time series of S&P500 index weekly returns is tested based on the Hurst exponent value. [ABSTRACT FROM AUTHOR]

The paper discusses the requirements and presents an architectural overview of a new general-purpose framework for real-time control, currently under development at the RFX laboratory. This represents the third generation of control framework developed at RFX. It takes into account the experience gained in the development of the previous frameworks and exploits the evolution of computer technology, in particular, the evolution of Linux towards real-time functionality and the availability of multicore CPUs in most general-purpose computing boards. The framework will supervise data flow among the participating components, which may produce data, consume data, or apply some sort of computation. Some system components have been already developed, while the architecture of others is still being refined. In particular, we are going to integrate the infrastructure layer of the new framework with a real-time framework recently in use at JET. The aim of this collaboration is a general purpose real-time system which can be used on both experiments. [ABSTRACT FROM AUTHOR]

Computer systems that can act autonomously and adapt to their environments pose questions of responsibility needing to be addressed in practice. Designers cannot fully control their learning systems, and design proactive systems not to be controlled except on a very superficial level. This leads to a "responsibility gap" between what one can hold the designer responsible for and what not. This paper discusses the responsibility gap and argues that it is an inevitable result of autonomous systems. We suggest a model of prospective and retrospective responsibility that applies to proactive systems. This model allows one to shift retrospective responsibility for harm caused by factors outside the programmer's control to the guilty party or to the proactive system itself. [ABSTRACT FROM AUTHOR]

The problem of allocating and scheduling precedence-constrained tasks on the processors of a distributed real-time system is NP-hard. As such, it has been traditionally tackled by means of heuristics, which provide only approximate or near-optimal solutions. This paper proposes a complete allocation and scheduling framework, and deploys an MPSoC virtual platform to validate the accuracy of modelling assumptions. The optimizer implements an efficient and exact approach to the mapping problem based on a decomposition strategy. The allocation subproblem is solved through Integer Programming (IP) while the scheduling one through Constraint Programming (CP). The two solvers interact by means of an iterative procedure which has been proven to converge to the optimal solution. Experimental results show significant speed-ups w.r.t. pure IP and CP exact solution strategies as well as high accuracy with respect to cycle-accurate functional simulation. Two case studies further demonstrate the practical viability of our framework for real-life applications. [ABSTRACT FROM AUTHOR]

We present an approach to the analysis and optimisation of heterogeneous multiprocessor embedded systems. The systems are heterogeneous not only in terms of hardware components, but also in terms of communication protocols and scheduling policies. When several scheduling policies share a resource, they are organised in a hierarchy. In this paper, we first develop a holistic scheduling and schedulability analysis that determines the timing properties of a hierarchically scheduled system. Second, we address design problems that are characteristic to such hierarchically scheduled systems: assignment of scheduling policies to tasks, mapping of tasks to hardware components, and the scheduling of the activities. We also present several algorithms for solving these problems. Our heuristics are able to find schedulable implementations under limited resources, achieving an efficient utilisation of the system. The developed algorithms are evaluated using extensive experiments and a real-life example. [ABSTRACT FROM AUTHOR]

Structured adaptive mesh refinement (SAMR) techniques provide an effective means for dynamically concentrating computational effort and resources to appropriate regions in the application domain. However, due to their dynamism and space-time heterogeneity, scalable parallel implementation of SAMR applications remains a challenge. This paper investigates hybrid runtime management strategies and presents an adaptive hierarchical multipartitioner (AHMP) framework. AHMP dynamically applies multiple partitioners to different regions of the domain, in a hierarchical manner, to match the local requirements of the regions. Key components of the AHMP framework include a segmentation-based clustering algorithm (SBC) that can efficiently identify regions in the domain with relatively homogeneous partitioning requirements, mechanisms for characterizing the partitioning requirements of these regions, and a runtime system for selecting, configuring, and applying the most appropriate partitioner to each region. Further, to address dynamic resource situations for long-running applications, AHMP provides a hybrid partitioning strategy (HPS) that involves application-level pipelining, trading space for time when resources are sufficiently large and underutilized, and an application-level out-of-core strategy (ALOC), trading time for space when resources are scarce in order to enhance the survivability of applications. The AHMP framework has been implemented and experimentally evaluated on up to 1,280 processors of the IBM SP4 cluster at the San Diego Supercomputer Center. [ABSTRACT FROM AUTHOR]

Application-level multicast is a promising alternative to IP multicast due to its independence from the IP routing infrastructure and its flexibility in constructing the delivery trees. The existing overlay multicast systems either support a single data source or have high maintenance overhead when multiple sources are allowed. They are inefficient for applications that require any-source multicast with varied host capacities and dynamic membership. This paper proposes ACOM, an any-source capacity-constrained overlay multicast system, consisting of three distributed multicast algorithms on top of a non-DHT overlay network with simple structures (random overlay with a non-DHT ring) that are easy to manage as nodes join and depart. The nodes have different capacities, and they can support different numbers of direct children during a multicast session. No explicit multicast trees are maintained on top of the overlay. The distributed execution of the algorithms naturally defines an implicit, roughly balanced, capacity-constrained multicast tree for each source node. We prove that the system can deliver a multicast message from any source to all nodes in expected O(logC n) hops, which is asymptotically optimal, where c is the average node capacity and m is the number of members in a multicast group. [ABSTRACT FROM AUTHOR]

Amdahl’s Law is based upon two assumptions – that of boundlessness and homogeneity – and so it can fail when applied to single chip heterogeneous multiprocessor designs, and even microarchitecture. We show that a performance increase in one part of the system can negatively impact the overall performance of the system, in direct contradiction to the way Amdahl’s Law is instructed. Fundamental assumptions that are consistent with Amdahl’s Law are a heavily ingrained part of our computing design culture, for research as well as design. This paper points in a new direction. We motivate that emphasis should be made on holistic, system level views instead of divide and conquer approaches. This, in turn, has relevance to the potential impacts of custom processors, system-level scheduling strategies and the way systems are partitioned. We realize that Amdahl’s Law is one of the few, fundamental laws of computing. However, its very power is in its simplicity, and if that simplicity is carried over to future systems, we believe that it will impede the potential of future computing systems. [ABSTRACT FROM AUTHOR]

The article explores on the marbling process and illustrates the simulation of the traditional art through the presentation of an interactive computer system for creating various marble textures. This traditional marbling process involves three steps wherein the final step contributes to the quality of the final design coming out on the paper or fabric. It also involves 2-dimensional fluid dynamics simulation, a physically based marbling simulation process which enables realistic marble designs. Modern graphic processing units show significantly higher performance because of the large amount of parallelism in graphics hardware. More importantly, the computer marbling system can integrate the design process into modern computer-aided design/computer-aided manufacturing systems.

As networking systems have become more complex and expensive, hands-on experiments based on networking simulation have become essential for teaching the key computer networking topics to students. The simulation approach is the most cost effective and highly useful because it provides a virtual environment for an assortment of desirable features such as modeling a network based on specific criteria and analyzing its performance under different scenarios with no cost. In this paper, we present our approach to develop an OPNET simulation networking laboratory that complements classroom lectures. Our simulation labs emphasize the understanding of the dynamics of network protocols instead of configuration and management. Students learn, through these experiments, a wide range of networking aspects including the design and the limitations of protocols, simulation and performance evaluation techniques, interpretation of data and packet analysis. Furthermore, we try to ensure that labs contain some extension or development of the topic beyond the lecture/reading and provide students additional active learning opportunities to discover knowledge. We have been using OPNET simulation in an introductory computer networks course for the past three years. Feedback from the students has been very positive. Overwhelmingly, students have indicated that the OPNET labs help them better understand the intricate details of actual networking protocols, and they generally indicate that they enjoy these labs as well. In summary, students benefit from the OPNET simulation laboratory in the following three ways. First, the OPNET simulation labs reinforce the networking theory taught by regular lectures. Second, the open design of the labs encourages active learning. Third, students gain the knowledge of modeling and simulation techniques for performance evaluation of networking systems. This active learning approach gives students experience in the subtleties of the design of a complex system, as well as prepares them for the networking industry. [ABSTRACT FROM PUBLISHER]

Abstract: In this paper, we propose the use of Versioned Boxes, which keep a history of values, as the basis for language-level memory transactions. Unlike previous work on software transactional memory, in our proposal read-only transactions never conflict with any other concurrent transaction. This may improve significantly the concurrency on applications which have longer transactions and a high read/write ratio. Furthermore, we discuss how we can reduce transaction conflicts by delaying computations and re-executing only parts of a transaction in case of a conflict. We propose two language-level abstractions to support these strategies: the per-transaction boxes and the restartable transactions. Finally, we lay out the basis for a more generic model, which better supports fine-grained restartable transactions. The goal of this new model is to generalize the previous two abstractions to reduce conflicts. [Copyright &y& Elsevier]

The dynamic distributed real-time applications run on clusters with varying execution time, so re-allocation of resources is critical to meet the applications's deadline. In this paper we present two adaptive recourse management techniques for dynamic real-time applications by employing the prediction of responses of real-time tasks that operate in time sharing environment and run-time analysis of scheduling policies. Prediction of response time for resource reallocation is accomplished by historical profiling of applications's resource usage to estimate resource requirements on the target machine and a probabilistic approach is applied for calculating the queuing delay that a process will experience on distributed hosts. Results show that as compared to statistical and worst-case approaches, our technique uses system resource more efficiently. [ABSTRACT FROM AUTHOR]

The paper analyzes the problem of rational replacement of computing systems. Such systems, especially high-performance computers, are expensive, but quickly become obsolete. A system analysis of the replacement problem is provided and the relevant modeling problems are identified and studied. The obtained results give certain rules for calculating the optimal lifetime of computing systems, which are based on the given rates of technological change in the related computer industry. Two simulation examples estimate the optimal lifetime of PCs and high-performance computers in the current US economy. The results are in good agreement with other recommendations and existing business practice. [ABSTRACT FROM AUTHOR]

A number of recent studies have revealed that the Optical Transpose Interconnection Systems (or OTIS) are promising candidates for future high-performance parallel computers. In this paper, we present and evaluate two general methods for algorithm development on the OTIS. The proposed methods are general in the sense that no specific factor network or problem domain is assumed. The proposed methods allow efficient mapping of a wide class of algorithms into the OTIS. These methods are based on grids and pipelines as popular structures that support a vast body of parallel applications including linear algebra, divide-and-conquer type of algorithms, sorting, and FFT computation. Timing models for measuring the performance of the proposed methods are also provided. Through these models, the performance of various algorithms on the OTIS are evaluated and compared with their counterparts on conventional electronic interconnection systems. This study confirms the viability of the OTIS as an attractive alternative for large-scale parallel architectures. Finally, we show how the proposed methods can be used to design parallel algorithms for linear algebra on the OTIS. [ABSTRACT FROM AUTHOR]

Enterprise applications are often business critical but lack effective synthetic workload generation techniques to evaluate performance, These workloads are characterized by sessions of interdependent requests that often cause and exploit dynamically generated responses. Interrequest dependencies must be reflected in synthetic workloads for these systems to exercise application functions correctly. This poses significant challenges for automating the construction of representative synthetic workloads and manipulating workload characteristics for sensitivity analyses. This paper presents a technique to overcome these problems. Given request logs for a system under study, the technique automatically creates a synthetic workload that has specified characteristics and maintains the correct interrequest dependencies. The technique is demonstrated through a case study involving a TPC-W e-commerce system. Results show that incorrect performance results can be obtained by neglecting interrequest dependencies, thereby highlighting the value of our technique. The study also exploits our technique to investigate the impact of several workload characteristics on system performance. Results establish that high variability in the distributions of session length, session idle times, and request service times can cause increased contention among sessions, leading to poor system responsiveness. To the best of our knowledge, these are the first results of this kind for a session-based system. We believe our technique is of value for studies where fine control over workload is essential. [ABSTRACT FROM AUTHOR]

Trillions of dollars are annually spent on the development and implementation of information technology within the United States and around the world. On average, roughly 50% of such systems are considered failures or fall short of meeting the expectations set forth by management. The lost productivity and high costs associated with these shortcomings necessitate the identification of alternative frameworks for facilitating the successful acceptance and continued internalization of new technologies. Internalization is defined as the effective and continued use of a technology over time. As such, this paper introduces a conceptual model for examining the effect of trust and planned change initiatives on technology adoption behavior. We propose that technology trust and interpersonal trust, when coupled with planned change initiatives, lead to greater technology adoption and internalization. A series of propositions are introduced and examined between trust, planned change, technology adoption, and internalization. Implications and recommendations for future explorations and development are presented. [ABSTRACT FROM AUTHOR]

Purpose — The goal of this research is to demonstrate how web-based applications improve the effectiveness of a very important human resource (HR) function. It proposes a framework of a web-based training needs assessment system for HR professionals to effectively assess employee needs for competency-based training. Design/methodology/approach — A conceptual framework of a survey-based training needs assessment using the Internet was developed. A use case detailing a walkthrough of a prototype system developed under this proposed framework was created to illustrate how this system works. A two-phased operation test of the prototype system was then conducted to assess how well human resource (HR) managers would accept and adopt this technology to develop organizational competencies. The first phase involved demonstrating the use case to a group of experienced HR managers and polling their opinion toward the system. The second phase involved one-on-one interviews with three select HR managers who were asked to experience the prototype system hands-on. Findings - HR managers from both phases of validation demonstrated positive acceptance of both the needs assessment model and the process improvement generated from the web-based prototype system. Research limitations/implications — The qualitative validation test was conducted to a small sample of Taiwan's HR managers. Caution is advised when generalizing the positive results to other regions or countries with more advanced IT applications in HR practices. Practical implications — This study contributes to the HR practice in several ways. First, it qualitatively confirms that HR professionals accept a competence-based approach to build company's training curriculum. Second, it observes a lack of effective tools to help HR professionals in the task of training needs assessment. Third, it shows that HR professionals do recognize the power of web technology in helping them become more efficient. Originality/value — Formal competency-based training programs are rarely implemented in the real world because the process required is both tedious and time-consuming. This paper adopts Internet technologies in a conceptual model for effective competency-based training needs assessment, and presents an efficient web-based tool to assist HR professionals in the needed analysis. [ABSTRACT FROM AUTHOR]

This paper presents a new methodology for predicting software reliability in the field environment. Our work differs from some existing models that assume a constant failure detection rate for software testing and field operation environments, as this new methodology considers the random environmental effects on soft- ware reliability. Assuming that all the random effects of the field environments can be captured by a unit-free environmental factor, η, which is modeled as a random-distributed variable, we establish a generalized random field environment (RFE) software reliability model that covers both the testing phase and the operating phase in the software development cycle. Based on the generalized RFE model, two specific random field environmental reliability models are proposed for predicting software reliability in the field environment: the γ-RFE model, and the β-RFE model. A set of software failure data from a telecommunication software application is used to illustrate the proposed models, both of which provide very good fittings to the software failures in both testing and operation environments. This new methodology provides a viable way to model the user environments, and further makes adjustments to the reliability prediction for similar software products. Based on the generalized software reliability model, further work may include the development of software cost models and the optimum software release policies under random field environments. [ABSTRACT FROM AUTHOR]

Deadlock detection scheduling is an important, yet often overlooked problem that can significantly affect the overall performance of deadlock handling. Excessive initiation of deadlock detection increases overall message usage, resulting in degraded system performance in the absence of deadlocks, while insufficient initiation of deadlock detection increases the deadlock persistence time, resulting in an increased deadlock resolution cost in the presence of deadlocks. The investigation of this performance trade-off, however, is missing in the literature. This paper studies the impact of deadlock detection scheduling on the overall performance of deadlock handling. In particular, we show that there exists an optimal deadlock detection frequency that yields the minimum long-run mean average cost, which is determined by the message complexities of the deadlock detection and resolution algorithms being used, as well as the rate of deadlock formation, denoted as λ. For the best known deadlock detection and resolution algorithms, we show that the asymptotically optimal frequency of deadlock detection scheduling that minimizes the overall message overhead is ...((λn)1/3) when the total number n of processes is sufficiently large. Furthermore, we show that, in general, fully distributed (uncoordinated) deadlock detection scheduling cannot be performed as efficiently as centralized (coordinated) deadlock detection scheduling. [ABSTRACT FROM AUTHOR]

Modern superscalar microprocessors need sizable register files to support a large number of in-flight instructions for exploiting instruction level parallelism (ILP). An alternative to building large register files is to use a smaller number of registers, but manage them more effectively. More efficient management of registers can also result in higher performance if the reduction of the register file size is not the goal. Traditional register file management mechanisms deallocate a physical register only when the next instruction writing to the same destination architectural register commits. In this paper, we propose several techniques for deallocating physical registers much earlier. Our designs rely on the use of a checkpointed register file (CRF), where a local shadow copy of each bitcell is used to temporarily save the values of the early deallocated registers should they be needed to recover from branch mispredictions or to reconstruct the precise state after exceptions or interrupts. The proposed techniques try to release registers as soon as possible and are more aggressive than the previously proposed schemes for early deallocation of registers. [ABSTRACT FROM AUTHOR]

Up to now, the power problems which could be caused by the huge amount of hardware resources present in modern systems have not been a primary concern. More recently, however, power consumption has begun limiting the number of resources which can be safely integrated into a single package, lest the heat dissipation exceed physical limits (before actual package meltdown). At the same time, new architectural techniques such as Simultaneous MultiThreading (SMT), whose goal it is to efficiently use the resources of a superscalar machine without introducing excessive additional control overhead, have appeared on the scene. In this paper, we present a new resource management scheme which enables an efficient low power mode in SMT architectures. The proposed scheme is based on a modified pipeline throttling technique which introduces a throttling point at the last stage of the processor pipeline in order to reduce power consumption. We demonstrate that resource utilization plays an important role in efficient power management and that our strategy can significantly improve performance in the power-saving mode. Since the proposed resource management scheme tests the processor condition cycle by cycle, we evaluate its performance by setting a target IPC as one sort of immediate power measure. Our analysis shows that an SMT processor with our dynamic resource management scheme can yield significantly higher overall performance. [ABSTRACT FROM AUTHOR]

In this paper, we propose a scalable multicast protection scheme based on a dual-homing architecture where each destination host is connected to two edge routers. Under such an architecture, there are two paths from the source of a multicast session to each destination host, which provides a certain level of protection for the data traffic from the source to the destination host. The protection level varies from 0 percent to 100 percent against a single link failure, depending on the number of shared links between these two paths. The major advantage of the proposed scheme lies in its scalability due to the fact that the protection is provided by constructing a dual-homing architecture at the access network while keeping the routing protocols in the core network unchanged. The selection of dual edge routers plays an important role in enhancing the protection level. Two problems arise for the proposed dual-homing partial multicast protection scheme. One is to calculate the survivability from the source to any pair of edge routers. The other is to assign a pair of edge routers for each destination host such that the total survivability is maximized for the multicast session subject to the port number constraint of each edge router. We propose an optimal algorithm to solve the first problem. We prove the decision version of the second problem is NP-complete and propose two heuristic algorithms to solve it. Simulation results show that the proposed heuristic algorithms achieve performance close to the calculated lower bound. [ABSTRACT FROM AUTHOR]

All known real-time proportional fair scheduling mechanisms either have high scheduling overheads (O(lg n) per time-slot) or do not efficiently handle dynamic task sets. This paper presents Frame-Based Proportional Round-Robin (FBPRR), a real-time fair scheduler providing high and bounded proportional fairness accuracy and O(1) scheduling overhead with the ability to efficiently handle a set of dynamic tasks. FBPRR achieves this by applying the benefits of Virtual-Time Round-Robin (VTRR) scheduling mechanism within a frame-based scheduling approach. Simulation results show that the algorithm gains a speedup of 5 to 20 times (over O(lg n) complexity schedulers) with fairly high fairness. [ABSTRACT FROM AUTHOR]

Nowadays, Side Channel Attacks allow an attacker to recover secrets stored in embedded devices more efficiently than any other kind of attack. Among the former, Fault Attacks (FA) and Single Power Analysis (SPA) are probably the most effective: When applied to straightforward implementations of the RSA cryptosystem, only one execution of the algorithm is required to recover the secret key. Over recent years, many countermeasures have been proposed to prevent Side Channel Attacks on RSA. Regarding Fault Attacks, only one countermeasure offers effective protection and it can be very costly. In this paper, we focus on a means to counteract Fault Attacks by presenting a new way of implementing exponentiation algorithms. This method can be used to obtain fast FA-resistant RSA signature generations in both the Straightforward Method and Chinese Remainder Theorem modes. Moreover, as it has been shown that Fault Attacks can benefit from the weaknesses introduced by some SPA countermeasures, we ensure that our method resists SPA and, thus, does not require supplementary SPA countermeasures. [ABSTRACT FROM AUTHOR]

This paper presents hardening techniques against fault attacks and the practical evaluation of their efficiency. The circuit technology investigated to improve the resistance against fault attacks is asynchronous logic. Specific properties of asynchronous circuits make them inherently resistant against a large class of faults. An analysis of their behavior in the presence of faults shows that they are an interesting alternative to design robust systems. A behavior diagnosis enables us to propose hardening techniques that improve fault tolerance and resistance. They are applied at design time and aim at exploiting quasi-delay insensitive (QDI) circuit properties to significantly harden the architecture with a very low area overhead and a reasonable performance penalty. To validate these techniques, a hardened DES crypto-processor is presented. The countermeasures are evaluated using laser beam fault injection. [ABSTRACT FROM AUTHOR]

In many cryptographic schemes, the most time consuming basic arithmetic operation is the finite field multiplication and its hardware implementation for bit parallel operation may require millions of logic gates. Some of these gates may become faulty in the field due to natural causes or malicious attacks, which may lead to the generation of erroneous outputs by the multiplier. In this paper, we propose new architectures to detect erroneous outputs caused by certain types of faults in bit-parallel and bit-serial polynomial basis multipliers over finite fields of characteristic two. In particular, parity prediction schemes are developed for detecting errors due to single and certain multiple stuck-at faults. Although the issue of detecting soft errors in registers is not considered, the proposed schemes have the advantage that they can be used with any irreducible binary polynomial chosen to define the finite field. [ABSTRACT FROM AUTHOR]