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This brief proposes a complementary common gate frequency doubler with a cross-coupling technique for conversion gain enhancement. The proposed frequency doubler enables a low-power and high-conversion-gain operation by implementing a current-reuse technique through a complementary architecture and a transconductance enhancement technique based on cross-coupling. The cross-coupling technique increases the effective input voltage by two times, resulting in a four-fold increase in the conversion gain. In this manner, the proposed technique can achieve a high conversion gain with low power consumption. A prototype frequency doubler is fabricated in a 28-nm CMOS SOI. Measurement results show a peak conversion gain of −1.41 dB at an output frequency of 79 GHz with a power consumption of 9.23 mW. [ABSTRACT FROM AUTHOR]

A 6-bit full-span programmable vector-sum phase shifter was presented in this brief. A transformer-based matching network is used to match the PPF-based I/Q generator to the variable gain amplifier-based vector-modulator (VGA-based VM), which eliminates the performance degradation due to impedance mismatch. The proposed phase shifter integrated in a two-channel transmitter was implemented in a 180-nm CMOS process. A program-assisted method was used to select the desired 6-bit (64) phase states from the total 4096 measured states of the chip, to realize a highly accurate phase tuning. The center frequency of the phase tuning can be set in the program, for different operation frequency points. An ultra-low root-mean-square (rms) phase/gain error less than 0.5°/0.15 dB are obtained at corresponding single frequency points. Moreover, a “band” mode is available as well, and rms phase/gain errors less than 2.25°/0.56 dB and 1.1°/0.32 dB are obtained at 4–10 GHz and 5.5-7.5 GHz, respectively. [ABSTRACT FROM AUTHOR]

A comprehensive analysis is derived to understand the mechanism of phase errors in cascode CMOS variable gain amplifiers (VGAs). According to the analysis, source–drain parasitic capacitors ($C_{\mathrm {ds}}$) of common gate (CG) transistors in off-region are the main causes for phase errors. An independent cascode current canceling (ICCC) VGA is proposed to relax phase errors by minimizing the effect of $C_{\mathrm {ds}}$ within a broadband. The proposed VGA achieves a 16-dB gain control with a 1.6° phase error and a 0.2-dB gain error from 15 to 25 GHz by 40-nm CMOS technology. Owing to the cascode structure, the peak gain of the VGA is 12 dB with only one stage including input–output pads consuming 16-mW power from 1.1-V voltage. Besides, the VGA can also serve as a 180° phase shifter (PS) due to ICCC structure with a 1.5° phase error and a 0.2-dB gain error from 15 to 25 GHz. The measured −3-dB bandwidth is 5 GHz, and output 1-dB compression point (OP1dB) is over 2.5 dBm in the maximum gain state. The core area is 0.065 mm2 excluding input–output pads. [ABSTRACT FROM AUTHOR]

Currently, the semiconductor industry requires test escape levels that approach the ppb level for application domains, such as automotive. Such quality levels, however, can only be reached if latent defects are screened out, as they have become the major bottleneck in analog and mixed-signal IC testing. Latent defects can be activated using accelerated aging, but this procedure has several drawbacks. Most notably, activation can move latent defects to the product lifetime that, otherwise, would not even have expressed themselves. Therefore, methods are needed that allow the detection of these defects without using activation. Developing such methods, however, has been hampered by the lack of compact latent defect models that allow simulating circuits affected by this type of defect. This article alleviates this problem by experimentally validating a recently presented compact model for latent defects and establishing the practical range of model values that should be used in simulations. The experiments performed on a 0.35- $\mu \text{m}$ technology consist of characterizing transistors containing latent defects that have been artificially introduced by etching pinholes in their gate. The measurement results corroborate that the drain current in transistors with defects increases with the area and depth of the defect, and that this behavior can be accurately modeled using an effective ${t}_{ox}$ value. [ABSTRACT FROM AUTHOR]

Cross-linking polymer gate dielectric is an efficient strategy to improve its intrinsic properties for high-performance flexible organic field-effect transistors (OFETs). However, the detail optimization process of the polymer films with the various cross-linking degrees is often ignored, which can bring a significant effect on the electrical performance of OFETs. In this work, the cross-linked poly (vinylalcohol) (CPVA) is introduced as the gate dielectrics for the high-performance ultraflexible OFETs. The dielectric property and the surface property of CPVA thin films with various cross-linking degrees are investigated in detail. The OFETs with a high average mobility of 7.3 cm $^{2}\cdot V^{-1}\cdot s^{-1}$ , a current ON/ OFF ratio of over 107, and a lower density of trap states of $8.7\times10$ 11 eV $^{-1}\cdot cm^{-2}$ are achieved successfully. Moreover, the ultraflexible OFET presents a high mobility of over 5.1 cm $^{2}\cdot V^{-1}\cdot s^{-1}$ even bending around a copper wire with a small radius of $400 ~\mu \text{m}$ , due to the ultrathin thickness of the device. These results demonstrate that the CPVA thin film is a promising candidate dielectric material for flexible organic transistors, presenting huge potential for the next-generation flexible electronic devices. [ABSTRACT FROM AUTHOR]

A very detailed investigation of high-speed silicon–germanium (SiGe) heterojunction bipolar transistors (HBTs) showed an underestimation of the measured peak cutoff frequency by simulations with a hydrodynamic (HD) model. It was speculated that this might be due to a breakdown of the HD approximation or unknown additional mechanical stress. We repeated those simulations with the more fundamental Boltzmann transport equation (BTE) based on the same device model (doping profiles, 2-D geometry, parasitics, and so on) and obtained almost similar results showing that this failure was not due to a breakdown of the HD approximation. Since additional uniaxial stress along the direction of the lateral base has been shown to increase the cutoff frequency, we investigated this effect. We found by 2-D device simulations that the increase in the peak cutoff frequency is rather small, and at high stress levels, it even decreases, if the uniaxial stress is applied homogenously. This is due to the reduction of the conductivity of the highly doped collector layer by the stress. If the stress is limited to the intrinsic transistor, the increase in the cutoff frequency is monotonic with growing stress. On the other hand, the collector current for a given base–emitter voltage also increases with stress leading to an overestimation of the collector current compared with the measurements. If this increase is corrected by a slight decrease in the germanium profile, the gain in the peak cutoff frequency is lost. Thus, the underestimation of the peak cutoff frequency cannot be explained by an additional homogeneous uniaxial stress in the intrinsic transistor. [ABSTRACT FROM AUTHOR]

We demonstrate nonvolatile and area-efficient ternary content-addressable memories (TCAMs) featuring amorphous indium–gallium–zinc–oxide (a-IGZO) ferroelectric field-effect transistors (FeFETs) with excellent electrical characteristics. An extremely large sensing margin of the TCAM array is achieved due to the large current ON/OFF ratio ($I_{ \mathrm{\scriptscriptstyle ON}}/I_{ \mathrm{\scriptscriptstyle OFF}})$ of the a-IGZO FeFETs. Our HfxZr $_{\text {1-x}}\text{O}$ 2 (HZO)-based a-IGZO FeFETs have a metal–ferroelectric–metal–insulator–semiconductor (MFMIS) structure. By engineering the area ratio of the ferroelectric layer (${A}_{Fe}$) and the metal–oxide–semiconductor layer (${A}_{MOS}$), a large memory window (MW) of 2.9 V is realized. Reliability test results, including retention, endurance, and positive bias temperature instability, show long-term retention of more than ten years and high endurance of 108 cycles. In addition, by scaling the channel length down to 40 nm, ON current of $77 ~\mu \text{A}/ \mu \text{m}$ (${V}_{\mathrm{GS}} - {V}_{\mathrm{TH}}$ = 5 V and ${V}_{\mathrm{DS}}$ = 2 V) and ${I}_{ \mathrm{\scriptscriptstyle ON}} / {I}_{ \mathrm{\scriptscriptstyle OFF}}$ of more than eight orders can be obtained for the ultrascaled a-IGZO FeFETs while maintaining an MW of 2.8 V. [ABSTRACT FROM AUTHOR]

FPGAs are increasingly becoming sensitive to aging effects mainly through BTI phenomena in the latest technology nodes. This phenomenon can be modeled as a shift in the threshold voltage of transistors which leads to performance degradation and reduction in SNM of SRAM cells. To reduce the aging effects on FPGA building blocks, we propose FIFA, a fully invertible FPGA architecture. In this architecture, two small modules are introduced to make the bitstream of logic and routing resources of the FPGA tiles fully invertible. Accordingly, to insert recovery cycles in the lifetime of the transistors, the bitstream stored in the configuration SRAM cells can be inverted occasionally without any changes in the functionality of the design. Using the proposed architecture, it is neither required to repeat the placement and routing procedures to generate multiple configuration bitstreams, nor extra memory is needed to save alternative bitstreams for changing the SRAM cells’ contents. Our experimental results over a set of industrial benchmarks show that by choosing an appropriate switch block arrangement and an optimized flipping frequency, the proposed architecture can improve the aging induced performance degradation by up to 62.5% with acceptable power and area overheads on logic and routing resources. [ABSTRACT FROM AUTHOR]

With the rapid development of wireless communication, the requirements of high-integration and low-cost radio frequency (RF) front-end modules in mobile phones result in more usage of silicon-on-insulator field effect transistors (SOIFETs) for the manufacturing of RF switches. However, the nonlinear behavior of SOIFET switches in off-state always produces unwanted harmonics distortion interference when they are excited by a large signal. In this article, we simplify the well-known physics-based surface potential model to an interelectrode nonlinear capacitance (INC) model since it adequately describes the harmonic effects produced by the transistor. The INC model, referred to as the coarse model, cannot match the behavior of the real switch, since many parameters of the switch cannot be accurately determined. This article proposes a novel dynamic neuro-space mapping network model, referred to as the fine model, to optimize the INC model. The proposed model takes advantage of the high accuracy of the fine model and the fast speed of the coarse model. Ultimately, the proposed method can accurately predict the harmonics interference for SOIFET switches in the complex RF front-end environment and provides an intuitive guideline under the design stage to prevent EMI problems. [ABSTRACT FROM AUTHOR]

The success of artificial neural networks (ANNs) in machine vision techniques has driven hardware researchers to explore more efficient computing elements for energy-expensive operations such as vector-matrix multiplication (VMM). In this work, InP-based floating-gate photo-field-effective transistors (FG-PFETs) are demonstrated as computing elements that integrate both photodetection and initial signal processing at the sensor level. These devices are fabricated from semiconductor channels grown via a back-end CMOS compatible templated-liquid phase (TLP) approach. Individual devices are shown to exhibit programmable responsivity, mimicking the effect of a synapse connecting the photodetector to a neuron. Using these devices, a simulated optical neural network (ONN) where the experimentally measured performance of FG-PFETs is used as an input shows excellent image recognition accuracy for color-mixed handwritten digits. [ABSTRACT FROM AUTHOR]

In this article, a load-modulation enhanced wideband compact high-efficiency millimeter-wave (mm-wave) gallium nitride (GaN) monolithic microwave integrated circuit (MMIC) synchronous Doherty power amplifier (DPA) is presented. A synchronous DPA architecture is used to ensure the optimal saturation performance at the mm-wave band. Based on the analysis of load-modulation behavior, the bandwidth of the DPA can be extended by decreasing the phase dispersion factor $\alpha $. A simple optimal tuning-based method is proposed to design an equivalent $\lambda $ /4 transmission line (EQWTL) with the minimal $\alpha $ for a given topology. Furthermore, the influence of the power division ratio $\sigma $ on the proposed DPA’s load-modulation behavior has also been analyzed and a proper load modulation can be realized by splitting more power to the peaking branch properly. For verification, a 24–28-GHz GaN MMIC synchronous DPA has been designed using a 0.15- $\mu \text{m}$ GaN on silicon carbide high-electron-mobility transistor process. Both the load modulation and the matching of the fundamental and the second harmonic load impedances can be realized by a modified bandpass-type EQWTL with a minimal $\alpha $ easily. Experimental results show that the fabricated DPA can achieve the output power of 35.4–36 dBm and the power-added efficiency (PAE) of 27.8%–36.8% at saturation. The PAE at 6-dB power back-off (PBO) is 18.3%–30.1% and the 9-dB PBO PAE is higher than 14.3% in the whole frequency band. An average PAE of 27.4% with good linearity is obtained when excited by a 400-MHz modulated signal after linearization. [ABSTRACT FROM AUTHOR]

The potential for negative-capacitance field-effect transistors (NCFETs) to enhance the unity-current-gain cutoff frequency ${f}_{T}$ and ${g}_{m}{f}_{T}/{I}_{D}$ ratio through a technique that mitigates the impacts of extrinsic parasitic capacitances is investigated, where ${g}_{m}$ is the transconductance and ${I}_{D}$ is the dc drain current and where “extrinsic” refers to elements arising outside an “intrinsic” or core transistor structure. We explain the technique and show that NCFETs can provide significant gains in extrinsic ${f}_{T}$ and ${g}_{m}{f}_{T}/{I}_{D}$ from this mitigation effect. However, an inherent degradation of intrinsic ${f}_{T}$ needs to be addressed to maximize these benefits, and this degradation can be alleviated through channel-length scaling as well as supply- and threshold-voltage tuning. The relative influences of different extrinsic parasitic elements are also evaluated, and it is found that improvements to ${f}_{T}$ and ${g}_{m}{f}_{T}/{I}_{D}$ increase as extrinsic parasitic capacitance increases and decrease as extrinsic parasitic resistance increases. Overall, this work finds that NCFET structures are promising candidates to mitigate the impacts of extrinsic parasitics in aggressively scaled transistors for the next-generation RF applications. [ABSTRACT FROM AUTHOR]

Hardware implementation of Bienenstock–Cooper–Munro (BCM) learning rules would be of great implications toward artificial intelligent systems. In this work, amorphous indium gallium zinc oxide (a-IGZO)-based photoelectronic neuromorphic transistors were proposed for mimicking BCM learning rules. A SiO2 electrolyte film with a large electric-double-layer capacitance ($0.33~\mu \text{F}$ /cm2) was used for the gate dielectric film. Light induced short-term synaptic plasticity can be mimicked by such device, including excitatory postsynaptic current (EPSC), paired-pulse facilitation (PPF), and high-pass temporal filtering. More importantly, BCM learning rules are realized based on this photoelectronic neuromorphic transistor. These results would provide a step forward the development of photoelectronic neuromorphic systems with sophisticated learning rules. [ABSTRACT FROM AUTHOR]

In this article, a novel step field plate (SFP) laterally diffused metal–oxide–semiconductor (LDMOS) structure is proposed for improved breakdown voltage- ON resistance tradeoff and better RF performance. The proposed structure could be easily integrated into the CMOS process flow using four additional noncritical masks. The known materials like fully silicided polysilicon and silicon nitride (SiN) are used as FP and dielectric, respectively. The proposed design improves the device performance by uniformly distributing the electric field in the drift region. The higher drift doping for the same OFF-state breakdown voltage improves the ON resistance by $\sim 2.5\times $ and ON-state breakdown voltage by $\sim 2\times $. Significant improvements in frequency behavior and flat power response are also observed. The device physics behind different observations are explained using detailed TCAD simulations. [ABSTRACT FROM AUTHOR]

In this article, we have evaluated the merits of monolithically cointegrated alternate channel complementary metal-oxide-semiconductor (CMOS) device architecture, utilizing tensile strained germanium ($\boldsymbol {\varepsilon }$ -Ge) for the p-channel FinFET and variable indium (In) compositional InxGa1-xAs ($0.10\le {x} \le0.53$) for the n- channel FinFET. The device simulation models were calibrated using the experimental results of Ge and InGaAs FinFETs and subsequently transferred to the cointegrated Ge and InxGa1-x As structure while keeping the device simulation parameters fixed. The device parameters, such as ${V}_{\text {T}}$ , ${I}_{\text {on}}$ , ${I}_{\text {off}}$ , and subthreshold-swing (SS), were determined for identical fin dimensions for n- and p-channel FinFETs as a function of In composition that alters the tensile strain in Ge. These parameters are controllable during the heteroepitaxial growth by varying In composition in InxGa1-xAs. $\boldsymbol {\varepsilon }$ -Ge p-FinFET is shown to be superior in terms of SS and ${I}_{\text {on}}/{I}_{\text {off}}$ ratio compared with other competing architectures. The cointegrated architecture of CMOS inverter exhibited an optimum performance over a range of In compositions from 20% to 40% while driving fan-out fan-out 1 (FO-1) and FO-4 load configurations. In addition, the CMOS inverter with symmetric rise and fall times as well as noise-immune functionality demonstrated 150 GHz of operating frequency with 30-nW total power dissipation at 20% In composition, and hence a superior power-delay-product comparable with International Technology Roadmap for Semiconductors (ITRS) standards. Moreover, the three-stage CMOS ring oscillator performance was evaluated with various In compositions to be stable and power efficient. Thus, the cointegrated approach has a potential to: 1) simplify large-scale CMOS integration and 2) be compatible with optoelectronic materials. [ABSTRACT FROM AUTHOR]

This work aims at proposing an analytical model for the variability of the threshold voltage and drain current in junctionless nanowire transistors. The model is continuous in all operation regions and has been validated through Monte Carlo simulations using a physically based drain current model and 3-D numerical simulations. A discussion about the influences of each variability source based on the proposed model is carried out. Finally, the modeled results are compared to the experimental data for a fully physical validation. [ABSTRACT FROM AUTHOR]

The design and manufacturing steps of a chip typically involve several parties. For example, a chip may comprise several third-party intellectual property (IP) cores and the integrated circuit (IC) fabrication may be outsourced to a third-party foundry. IP cores and ICs are shared with potentially untrusted third parties and, as a result, are subject to piracy attacks. Even more, any legally purchased chip may be reverse engineered to retrieve the design down to transistor level and, thereby, it is also subject to piracy attacks. In this article, we propose MixLock, an anti-piracy countermeasure for mixed-signal IP cores and ICs. MixLock protection is based on inserting a lock mechanism into the design such that correct functionality is established only after applying a key which is the designer’s secret. The lock mechanism acts on the mixed-signal performances by leveraging logic locking of the digital part. MixLock presents several key attributes. It is generally applicable, it is nonintrusive to the sensitive analog section, it incurs no performance penalty and has very low area and power overheads, it is fully automated, and it is capable of co-optimizing security in both the analog and digital domains. We demonstrate MixLock on a $\Sigma \Delta $ analog-to-digital converter (ADC) using hardware measurements and an audio demonstrator. [ABSTRACT FROM AUTHOR]

Data movement overheads caused by the recent explosion in big data applications have made traditional von Neumann architecture fails to tackle big data workloads. Processing in Memory (PIM), where computational tasks are performed within the memory, has drawn increasing attention. To present meaningful insights to readers, we divide current PIM paradigm into charge-based and resistance-based categories according to different memory devices. This mini tutorial aims to provide a concise overview of the implementation of PIM schemes, highlighting important macro prototypes in artificial intelligence applications that have been released in the past five years. [ABSTRACT FROM AUTHOR]

This tutorial focuses on memory elements and analog/digital (A/D) interfaces used in mixed-signal accelerators for deep neural networks (DNNs) in machine learning (ML) applications. These very dedicated systems exploit analog in-memory computation (AiMC) of weights and input activations to accelerate the DNN algorithm. The co-optimization of the memory cell storing the weights with the peripheral circuits is mandatory for improving the performance metrics of the accelerator. In this tutorial, four memory devices for AiMC are reported and analyzed with their computation scheme, including the digital-to-analog converter (DAC). Moreover, we review analog-to-digital converters (ADCs) for the quantization of the AiMC results, focusing on the design trade-offs of the different topologies given by the context. [ABSTRACT FROM AUTHOR]

In this work, a digital predistortion (DPD) model for the linearization of RF power amplifiers (PAs) is presented. The model provides a linearized gain (DPD + PA) independent of the instantaneous transistor channel temperature within a predefined temperature window. Channel temperature variations due to varying ambient temperatures or changes in the signal probability density function (PDF) cause long-term memory effects, which results in dispersed (dynamic) AM/AM and AM/PM characteristics. The presented model is used to compensate for the memory effects due to self-heating and external temperature changes by estimating the transistor channel temperature through a linear single-pole Foster thermal network. The DPD model uses a first-order Taylor approximation to cancel out temperature-based nonlinearities. Gaussian pulses are used to extract the PA intrapulse gain at different temperatures without being affected by the signal PDF, thus allowing temperature- and signal-independent PA characterization. The model is validated from $20~^\circ \text{C}$ to $80~^\circ \text{C}$ and by considering a class-B 3.75-GHz 10-W gallium nitride (GaN)-on-SiC PA. The DPD performance is evaluated by considering the normalized root-mean-squared error (NRMSE), the output spectra, and adjacent channel power ratio (ACPR) with and without DPD for multiple signals bandwidths and peak-to-average power ratio (PAPR) and finally compared with other approaches. [ABSTRACT FROM AUTHOR]

This article presents a temperature compensated transmitter for phased-array applications. The high-temperature effects on each individual transmitter building block are studied and compensated to mitigate the performance variations. Furthermore, a new active, tunable, and variable gain phase shifter VGPS) architecture is proposed, which features low-performance variation with temperature and high gain without compromising the phase shift range. A temperature sensor is designed to adaptively adjust the critical dc bias voltages to minimize the variation of the active devices. A class- $\text{F}^{-1}$ power amplifier PA) is designed, as the last stage in the transmitter chain, and its performance variation is compensated through the VGPS stage by adaptively tuning its characteristics. Gallium-nitride (GaN)-on-silicon-carbide (SiC) high-electron-mobility transistors (HEMTs) are adopted as the active devices and a voltage-controlled capacitor (varactor) used in the VGPS stage. The transmitter is prototyped on a piece of Rogers 4003C substrate, and the system performance is measured. The transmitter has the minimum and the maximum small-signal gain of 5.2 and 31.5 dB, respectively, with the maximum variation of < 2.3 dB across the temperature range and the frequency range of 2–2.1 GHz. The insertion phase variation also remains below 6.5° across the phase shift, temperature, and frequency range. The maximum output power and power added efficiency (PAE) are measured to be 33 dBm and 58%, respectively, at the maximum ambient temperature of 220 °C. The measurement results also show that the transmitter is able to transmit 64-QAM signals with the data rate of 120 Mb/s at the maximum ambient temperature of 220 °C. [ABSTRACT FROM AUTHOR]

In this article, a temperature-dependent threshold voltage extraction method based on noise measurement is proposed. This method induces a mathematical solution for acquiring channel temperatures ($T$) of transistors in the saturation region to extract threshold voltages. In order to gain accurate channel temperature, a small-signal equivalent circuit model was established to determine transconductance ($g_{m}$). Then, the extracted transconductance and measured noise power spectral density (NPSD) were used to obtain channel temperatures. On this basis, the temperature-dependent threshold voltage ($V_{\mathrm {th}}$) was derived. To validate the reliability of this method, a four-Fin six-finger N-FinFET and a four-Fin eight-finger N-FinFET were fabricated using the 14-nm bulk FinFET technology. In this study, the scattering parameters were obtained from 0.2 to 40.2 GHz. Also, the NPSDs were measured from 1 to 500 Hz, while gate voltage and drain voltage were set as 0.3, 0.49, and 0.75 V. Besides, the transistor $I_{\mathrm {ds}}$ – $V_{\mathrm {ds}}$ characteristics was also investigated when drain–source bias voltage changed from 0.05 to 0.9 V. Compared with the measurement results, the calculation results of drain–source current model using temperature-dependent threshold voltage achieved higher accuracy. Also, the root mean square errors (RMSEs) were less than 0.60% for four-Fin six-finger N-FinFET and less than 0.51% for four-Fin eight-finger N-FinFET. Therefore, the proposed extraction method can be applied to accurately predict transistor temperature-dependent threshold voltage. [ABSTRACT FROM AUTHOR]

A high-data-rate $D$ -band transmitter (TX) module cointegrating a dual-channel TX integrated circuit (IC) in 45-nm CMOS partially deplated silicon-on-insulator (PDSOI) technology and an antenna is presented. The proposed system-in-package is based on an innovative channel-bonding technique and is fabricated using a low-cost printed circuit board process. The IC consists of two upconversion chains, including on-chip millimeter-wave local oscillator generators. The emitted signal is composed of eight channels, each one having 2.16-GHz bandwidth, organized in two sets of four channels at the intermediate frequency (IF) band (around 61.56 GHz) that are upconverted to two adjacent subbands centered at 148 GHz. Then, the two subband signals are combined off-chip using a substrate integrated waveguide diplexer and radiated by a patch antenna array realized on the same package. The output spans from 139.3 to 156.6 GHz. The total equivalent isotropic radiated power is 8.3 dBm. An 84.48-Gb/s data rate is achieved with 64-QAM. The module consumes 600 mW from a 1-V supply and occupies a compact area of 12 $\times $ 6 mm2. [ABSTRACT FROM AUTHOR]

This article presents a new approach to automate the setup of the design equations of the manual analog design process. Its main contribution is a comprehensive hierarchical performance equation library (HPEL) for op-amps. The HPEL makes the setup of design equations independent of the topology. Based on the library and the functional block recognition method in Abel et al. (2020), analytical performance models for various op-amp topologies are automatically instantiated. The method is currently designed for basic op-amps. In this article, we use the method to size different op-amp topologies. Experimental results featuring four circuits are presented. The HPEL has also been integrated into a structural synthesis method featuring several thousand op-amp topologies (Abel and Graeb, 2021). [ABSTRACT FROM AUTHOR]

Ferroelectric field-effect transistor (FeFET)-based circuit implementation mimicking FitzHugh-Nagumo neuron is proposed in this work. The proposed circuit is shown to mimic biological neuron properties, such as excitation block and anodal break excitation which are not mimicked by an integrate and fire neuron model. We also show a winner-take-all circuit that can be used with this proposed neuron implementation. The neuron implementation requires just one FeFET, three baseline field-effect transistors, and one capacitor, making it area and energy-efficient. The neuron circuit, with minimum sized transistors, consumes approximately 10 pJ per spike. The neuron’s energy consumption per spike can be reduced to as low as 100 fJ by designing some of the transistors with aspect ratio less than one. [ABSTRACT FROM AUTHOR]

Noise probably the single most important performance metric of the high-speed transimpedance amplifier (TIA), which directly sets the sensitivity of optical receiver. The transimpedance limit which dictates the maximum achievable transimpedance gain of the TIA also turns out to fundamentally limit the TIA noise performance. In this tutorial, we analyze and explore two circuit design approaches to overcome the transimpedance limit. The first approach (Type I) realizes a divide-and-conquer methodology to separate the noise-bandwidth problem and solve them individually. The second approach (Type II) employs a multi-stage stagger-tuned amplifier. Both approaches can overcome the transimpedance limit, forming an effective toolkit for the design of low-noise high-speed TIA for high-sensitivity CMOS optical receivers in current and future applications. [ABSTRACT FROM AUTHOR]

This brief gives an overview of recent advancements in CMOS automotive radar sensors, focusing on the most critical circuit design at mm-wave frequencies. Highly scaled CMOS technologies enable very low-power consumption, reduced costs, and higher data processing capacity and integration compared to state-of-the-art SiGe BiCMOS chip-set solutions commonly adopted in commercial products. The very bottleneck is still represented by the radio front-end due to the challenging requirements of long-range radars. Circuit topologies and design tradeoffs are here discussed with reference to critical building blocks of the mm-wave radar front-end, reporting circuit implementations for a 77-GHz long-range radar sensor in a 28-nm fully-depleted silicon-on-insulator CMOS technology. [ABSTRACT FROM AUTHOR]

This tutorial presents the holistic modeling concept in the context of metal-oxide-semiconductor field-effect-transistors (MOSFETs). First, the standard MOSFET modeling approaches will be comparatively discussed. Subsequently, several factors impacting the operation of MOSFETs will be explained in terms of their physical origins and their modeling, as already undertaken in the literature. These factors include process variations, time-based degradation, as well as extreme environmental conditions, such as low or high temperatures and ionizing radiation. Subsequently, the need for considering these phenomena in joint configurations is demonstrated through experimental data. Finally, an implementation strategy for holistic modeling will be proposed by introducing ‘extreme corners’, which represent the combinations of conventional process corners with the mentioned factors at various values of interest. [ABSTRACT FROM AUTHOR]

This brief proposes a novel power amplifier (PA) topology which can realize PA operation with high power back-off range (OBO) and wide bandwidth. Here a short-circuit reactance instead of an additional PA branch is introduced into the isolated port of a coupler to provide the frequency dependency required for broadband load impedance modulation. In addition, the corresponding complex load impedances at each normalized frequency are given to achieve high OBO based on the use of the same transistor in both the carrier PA and peak PA branches. The behaviors of the proposed PA as a function of input power are also derived based on the appropriate complex load impedance. To validate the proposed topology, a PA with 9 dB OBO operating across 1.0-3.0 GHz is designed, fabricated, and tested. Measurements illustrate that the PA can deliver a saturated output power from 44 dBm to 45 dBm over 1.0-3.0 GHz, with a drain efficiency ranging from 62% to 71%. Drain efficiencies are from 41% to 48% at the OBO of 9 dB. [ABSTRACT FROM AUTHOR]

In this article, novel single- and dual-band reconfigurable microwave component (RMC) designs with very compact circuit sizes are proposed, which can be reconfigured into multiple functions, including a bandpass filter, a bandstop filter, and a quadrature coupler. The proposed RMCs with filter and coupler functions are based on lumped elements and transistor-based switches such that they are very suitable for on-chip implementation. Specifically, the proposed 10-GHz RMC in GaAs can achieve the functions of a bandpass filter, a bandstop filter, and a quadrature coupler with a circuit size of only 1.8 mm $\times1.35$ mm. On the other hand, the proposed 9.5/24-GHz RMC in GaAs can be reconfigured as either a dual-band bandpass filter or a dual-band quadrature coupler, while the circuit size is only 1.36 mm $\times1.15$ mm. In addition, to demonstrate the possible application of the proposed RMC designs, a proof-of-concept 2.45-GHz radar system prototype based on a proposed 2.45-GHz RMC is implemented in PCB, which successfully integrates the functions of target speed detection and transmission in a single hardware. [ABSTRACT FROM AUTHOR]

Low-frequency mymargin noise, thermal noise, and dc characteristics of nanoscale MOS transistors with dimensions close to the process minimum are highly variable. This article demonstrates a phase noise (PN) reduction technique for LC voltage-controlled oscillators (VCOs) that use an intelligent post-fabrication selection of a subset of an array of near minimum-size cross-coupled transistor pairs with reduced low-frequency noise and thermal noise. Using the technique, the PN of a VCO is lowered from the maximum by 3.5 dB at 600-kHz, 1-MHz, and 3-MHz offsets from a 3.8-GHz carrier. The lowest PN of −122, −129, and −139.5 dBc/Hz at 600-kHz, 1-MHz, and 3-MHz offsets, respectively, from a 3.8-GHz carrier has been measured using the PLL method of the Keysight E5052B Signal Source Analyzer. The VCO prototype was fabricated in a 65-nm CMOS process and dissipates 7 mW of dc power. The maximum figure of merit (FoM), including PN, carrier frequency, and power consumption, is 193 dBc/Hz, and the FoM, including the VCO core area, ${\mathrm {FoM}}_{A}$ , is 209 dBc/Hz. [ABSTRACT FROM AUTHOR]

Junctionless transistors (JLTs) have promising strengths such as extremely simple structures without p-n junctions, better reliability, and low flicker noise, for overcoming scaling challenges for advanced sub-5-nm nodes. In this article, channel-width-dependent operation in the partially depleted regime of tri-gate JLTs was investigated in comparison to conduction in conventional inversion-mode (IM) transistors. A large difference in transconductance (${g} _{m}$) against gate-to-channel capacitance (${C} _{gc}$) and the reduced amplitude of the first peak on $dg_{m}$ / $dV_{g}$ were identified under the partially depleted regime in JLTs, due to a severe transverse ${E}$ -field near-threshold voltage (${V} _{th}$). However, the impact of ${E}$ -field was weakened as decreasing channel width of JLTs. These works provide key information for a better understanding of the channel-width-dependent performance of JLTs and for implementing practical applications with them. [ABSTRACT FROM AUTHOR]

The a-InGaZnO (a-IGZO) thin-film transistors (TFTs) in elevated-metal metal-oxide (EMMO) architecture was found to exhibit high stability against photo-bias stresses. In contrast to the common photo-enhanced degradation, an abnormal self-compensation effect of photo-bias instabilities was first observed for amorphous oxide semiconductor (AOS) TFTs. By analyzing the defect states and element distributions in both channel and source/drain (S/D) regions, the unique migration of thermally generated metal interstitials in a-IGZO S/D was clarified to be the origin. More specifically, the positive bias stress (PBS)-induced negative shift of threshold voltage (${V}_{\text{th}}$) originates from the ionization of positive metal ions near the backchannel, while these positively charged ions can be compensated by the illumination-excited electrons, resulting in photo-stable AOS TFTs. This also provides a flexible way to implement the electrically stable depletion-mode AOS TFTs. [ABSTRACT FROM AUTHOR]

The polycrystalline silicon vertical thin-film transistors (TFTs) with different active layer thicknesses of 150 and 300 nm were fabricated by a five-mask process and electrically characterized. The vertical TFT with 150-nm active layer thickness shows comprehensive advantages over its counterpart with 300-nm active layer, especially with a higher ON/OFF current ratio $I_{\mathrm{ON}}/I_{\mathrm{OFF}}$ of more than 106 and higher field-effect mobility, excluding the access resistance effect. The electrical parameters were analyzed by the density of states (DOS) calculation, and smaller DOS is deduced for the device with 150-nm active layer for the same energy level. The detailed elucidation of the DOS was analyzed by introducing the intrinsic mobility and the grain boundary barrier height at the flat-band state, which gives the detailed expressions for the DOS. Polycrystalline silicon lateral TFT was also introduced to verify this evaluation method. [ABSTRACT FROM AUTHOR]

An extended write-ability methodology of static random-access memory (SRAM) in advanced technology nodes is proposed in this article. Increased bitline (BL) resistance in sub-10 nm node has hindered BL from fully discharge during a write operation. Furthermore, the write ability is degraded by an increased leakage current of half-selected bitcells on BL and BL capacitance operated in high frequency. In a realistic write operation, BL parasitics also cause 30% SRAM yield loss in interconnect resistance-dominated technology nodes. Thus, this proposed method analyzes the time-dependent impacts of BL parasitic resistors, capacitors, and pass-gate (PG) transistors on write margin considering the negative BL (NBL) assist technique. [ABSTRACT FROM AUTHOR]

An overview of different charge and voltage storage global shutter (GS) pixel arrays developed over the last 15 or so years reflects the advancement of CMOS technology. High dynamic range and multitap GS pixels found their applications in automotive and other emerging fields. Both front side illuminated and back side illuminated (BSI) pixel structures are covered with highlights on the impact to the GS pixel performance including near-infrared and visual sensitivity, GS efficiency, pixel crosstalk, and angular response improvements. Proliferation of BSI per pixel stacked GS pixels pushed sizes into the 2.2- $\mu \text{m}$ range and promised even further pixel size reduction. [ABSTRACT FROM AUTHOR]

Linear transformations are the dominating computation within many important applications. The natural multiply-and-accumulate feature of memristor crossbar arrays promise unprecedented processing capabilities to resistive dot-product engines (DPEs), which can accelerate approximate matrix–vector multiplication (MVM). Unfortunately, the precision of the analog computation may be degraded by parasitics, nonlinear device characteristics, and variations. In this article, we propose a framework, called XMAP, for mapping an arbitrary matrix into appropriate memristor conductance values (or state variables for nonlinear devices). The specified conductance values are next programmed to the memristor hardware using accurate closed-loop tuning. XMAP is based on formulating the mapping problem as a mathematical optimization problem, which can be elegantly minimized using the concept of representable matrices, i.e., the matrices that can be represented on a crossbar. Compared to the state-of-the-art conversion algorithm, the computational accuracy is improved with up to $3.29 \times $ at the expense of overhead in runtime. The precision improvements translate into noteworthy application-level benefits within signal compression and neural network inference. [ABSTRACT FROM AUTHOR]

Progress in electronic design automation (EDA) has enabled us to manage the exponential growth of complexity in integrated circuits (ICs) allowed by Moore’s Law, and translate it into performance improvements. Furthermore, as Moore’s law slows down and with the collapse of Dennard scaling over the past decade, EDA tools become increasingly important in addressing inefficiencies in ICs. As new proposals and techniques are put forward to address the current and future issues of IC design, a concrete set of contemporary benchmarks needs to be used for their evaluation. Traditionally, EDA researchers have mainly relied on industry provided design benchmarks in evaluating the performance of their tools. However, due to their effort to maintain their competitive advantage, industry releases include older designs with limited information about the details of each design. This means that in multiple cases, new proposals are evaluated with significantly dated designs, often more than a decade old, especially in terms of scale. In this work, we describe OPDB: a scalable, modular, heterogeneous, and extensible design benchmark for the EDA community. OPDB leverages and extends the OpenPiton open-source, tile-based research infrastructure to create a surplus of design benchmarks that target different components. Due to the tiled nature of this architecture, OPDB benchmarks can be made arbitrarily large in order to evaluate the efficiency of EDA tools across different design scales and configurations. OPDB contains several accelerators enabling full SoC designs to be used as benchmarks for EDA tools. [ABSTRACT FROM AUTHOR]

Data deduplication has been widely employed in flash-based storage as an effective technique for enhancing reliability and cost efficiency. However, the read/write interference problem of flash storage, where on-going write requests prevent read requests from accessing available data and significantly increase read latency, remains a critical concern with the rapid evolutions of flash chips from SLC through MLC to TLC and on to QLC, with PLC on the horizon, especially under workloads with a mixture of read and write requests. To significantly improve the read performance in face of read/write interference, which is often more critical than the write performance, we propose an enhanced Hot Read Data Replication scheme for deduplication-based flash storage, called DedupHR, to alleviate the read/write interference problem. DedupHR exploits the content locality in the deduplication-based flash storage and outsources the data blocks with high reference count to a surrogate space such as a dedicated spare flash chip or an over-provisioned space in an SSD. By servicing some conflicted read requests on the surrogate flash space, DedupHR can significantly alleviate, if not entirely eliminate, the contention between the read requests and the on-going write requests. The evaluation results show that DedupHR significantly improves the state-of-the-art schemes in terms of the system performance and cost efficiency. Consequently, the tail-latency of the deduplication-based flash storage is also reduced. [ABSTRACT FROM AUTHOR]

The CLLC resonant converter is a promising candidate for high efficient, bidirectional power transfer applications, such as vehicle-to-grid on-board charger and hybrid vehicle dc–dc converter. Nevertheless, the analysis of CLLC still remains challenging because of its complex multiresonant nature and several storage elements. In this article, a circuit analysis method based on change of variables is presented that maps the state-space equations into two decoupled sets of equations. The analyses are carried out in two state-plane coordinate systems, then the results are mapped onto the original region. The proposed method is then used to thoroughly analyze the CLLC resonant converter operating in the continuous conduction mode (CCM). The voltage and current stresses of components, zero voltage switching condition, output voltage gain, output characteristic diagram, and mode boundary of CCM/ discontinuous conduction mode are then obtained. The accuracy of the proposed approach is verified by the experiments on a 3 kW bidirectional CLLC resonant converter with GaN transistors as the primary and secondary side switches. The results confirm the accuracy of the proposed state-plane analysis of the CLLC resonant converter operating in either direction of power transferring. [ABSTRACT FROM AUTHOR]

Envelope tracking is a well-known RF technique that alleviates the efficiency problem of linear power amplifiers used in wireless communication transmitters. It consists in varying the supply voltage of the amplifier, which is commonly constant, according to the envelope of the communication signal. Therefore, a switching-mode power converter with a bandwidth of several megahertz is required to perform the fast voltage changes needed for tracking the envelope properly. Another important requirement is that the converter needs to be able to achieve high efficiency not only at peak output power, but also at low output power because it operates in that power range most of the time due to the characteristics of modern communication signals. Taking into account these requirements, the design of the converter is very challenging, especially in the case of base stations, where higher power levels are reached by means of higher voltage levels. As a result, transistors with low breakdown voltages (20–30 V), which offer the highest speed, cannot be used in the converter. In this article, a novel multilevel converter able to use transistors with low breakdown voltages is proposed to alleviate that problem. Moreover, it shows a better switching behavior than the previously proposed multilevel converters, thus reducing the switching losses and, consequently, increasing the efficiency. In order to experimentally validate the proposed topology, a 73-W prototype with a switching frequency of 8 MHz was built. The efficiency is 94% and 81.7% at peak output power and at one-tenth of peak output power, respectively. [ABSTRACT FROM AUTHOR]

In this article, a fully coupled multiphysical model of multichip press-pack insulated gate bipolar transistor (PPI) considering surface roughness is proposed. This model realizes the coupling of the electrical-, thermal- and mechanical domains through contact resistance. The simultaneous prediction of temperature and stress under various surface roughness is achieved. First, the fully coupled model and the contact resistance model are established. Second, both thermomechanical stress under the clamping phase and heating phase are analyzed. The influence of the surface roughness on the thermo-mechanical stress distribution is also investigated based on the proposed model. Results show that the surface roughness does not affect the thermomechanical stress distribution under the heating phase, while the amplitudes increase with surface roughness. Third, the correctness of the model is verified by the temperature measurement and deterioration observation results. The observed fretting scratches on the additional metallization area after the power cycling test validates the correctness of the deformation prediction. Finally, the strain-life fatigue model of PPI is established, it turns out that the surface roughness has an impact on the fatigue life of the chip metallization area. [ABSTRACT FROM AUTHOR]

At deep sub-micrometer technology, CMOS circuits suffer from high leakage and have reliability issues due to process variation. Hybrid magnetic tunnel junction (MTJ)/CMOS circuits have been proposed to overcome these challenges. MTJs have zero standby power and are compatible with CMOS technology. In this article, a dynamic logic-based hybrid MTJ/CMOS magnetic full adder (MFA) has been proposed, which eliminates the error voltage appearing on output due to charge injection and clock feedthrough phenomenon, thereby enhancing the performance of MFA and making it more reliable. This effect is induced by the pMOS transistor, which is used as a switch to precharge the output nodes. The proposed MFA uses two dummy transistors, whose drain and source terminals are shorted to make them act as MOS capacitors, to absorb the error voltage introduced by the switch pMOS transistor due to charge injection and clock feedthrough, when turned OFF. Eliminating the error induced due to charge injection and clock feedthrough makes the amplification process faster and reduces the dynamic power consumption. Results are verified by performing transient and Monte Carlo simulations using cadence virtuoso with UMC 40 nm CMOS technology kit and compact model of perpendicular magnetic anisotropy (PMA) MTJ, which validates that the proposed MFA is highly reliable as it provides the error-free output and imparts better power–delay product (PDP) compared to previously proposed MFA. [ABSTRACT FROM AUTHOR]

The artificial neural networks based on biomimetic synaptic devices attempts to process and memorize information by simulating a human brain. Electrolyte-gated transistors (EGTs) are promising candidates for artificial synaptic devices, due to their large specific capacitance, low operating voltage, and sensitive interfacial properties. Although large-scale EGTs array based on inorganic electrolytes and small-scale EGTs arrays based on organic electrolytes are reported, large-scale EGTs arrays based on organic electrolytes have not yet been focused. In this work, a large-scale EGTs array ($10\times10$) based on coplanar-gate structure using lignin as electrolyte is fabricated. The organic dielectric layer fabricated in the last step can be protected from the damage caused by wet etching, thus providing an opportunity for the application of other organic electrolytes in the large-scale EGTs array. Lignin exhibits good electric performance and is environment-friendly due to its renewable property. The synaptic properties of single transistor in the EGTs array, such as excitatory postsynaptic current (EPSC), paired-pulse facilitation (PPF), and high-pass filtering are realized. The real-time learning and forgetting procedures stimulated by different spike numbers of EGTs array are also demonstrated. [ABSTRACT FROM AUTHOR]

In this work, a new type of graphene ICs only comprising multiple graphene field-effect transistor (GFET) components is first reported. Based on the GFET design that enables homogeneous electrical characteristics in batch-made devices, the practicality and functionality significances of multi-GFET integration are experimentally demonstrated via high-fidelity amplifiers for baseband analog signals. Different from the quadratic relationship of the gate-controlled current output (in saturation region) in the traditional silicon-based MOSFETs, the saturation current output of GFETs relating to the gate-controls possesses high linearity. This advantage overcomes the inherent nonlinear distortion issues in the existing silicon MOSFET amplifiers and potentially provides a promising scenario for the accurate preamplification of weak analog signals. Besides, the novel circuit configuration and signaling principle may expand the developmental paradigm of analog amplifiers and set groundwork for the development and practicalization of advanced carbon-based nanoelectronic ICs. [ABSTRACT FROM AUTHOR]

Profiling side-channel attacks in which an adversary creates a “profile” of a sensitive device and uses such a profile to model a target device with similar implementation has received the lion’s share of attention in the recent years. In particular, template attacks are known to be the most powerful profiling side-channel attacks from an information theoretic point of view. When launching such an attack, the adversary first builds a model based on the leakage of the profiling (training) device in his disposal, which is then exploited in the second phase of the attack (i.e., matching) to extract the key from the target device. Discrepancies between the device used for modeling and the target device affect the attack success. The effect of process variation and temperature misalignment between the profiling and target devices in the template attack’s success has been studied extensively in the literature, while the impact of device aging on the template attack’s success is yet to be investigated thoroughly. This article moves one step forward and studies the impact of device aging, mainly bias temperature instability (BTI) and hot carrier injection (HCI), in the devices that have been protected against power analysis attacks via dual rail logics. In particular, we focus on the wave dynamic differential logic (WDDL) circuits, and via extensive transistor-level simulations, we will show how device aging misalignments between the profiling and target devices can hinder template attacks for both unprotected and WDDL protected counterparts. We mounted several attacks on the PRESENT cipher, with and without WDDL protection, at different temperatures and aging times. Our results show that the attack is more difficult if there is an aging-duration mismatch between the training and target devices, and the attack-efficiency decrease is especially significant for mismatches of few weeks. [ABSTRACT FROM AUTHOR]

Fast active quenching of single-photon avalanche diodes (SPADs) is important to reduce the afterpulsing probability (APP). An option to reduce the reaction time of electronics to a SPAD's avalanche is to design a quencher exploiting bipolar transistors. A quencher in a 0.35 μm CMOS technology with a nominal supply voltage of 3.3 V, which operated with excess bias voltages up to 6.6 V, was re-designed accordingly. In the new 0.35 μm pure-silicon BiCMOS quencher, the comparator takes advantage of a bipolar differential amplifier, which additionally gives the head room to increase the width of some CMOS transistors as well. The proposed BiCMOS quencher is able to drive the load of a wire-bonded 184 μm-diameter SPAD, while the CMOS design fails. A comparison, where both chips are measured with a wire-bonded, 34 μm-diameter SPAD, shows that the BiCMOS quencher has a reaction time, which is 330 ps to 1.1 ns faster than that of the CMOS quencher. [ABSTRACT FROM AUTHOR]

This article proposes a macromodel to predict the nonlinear behavior of operational amplifiers having their baseband signal affected by out-of-band disturbances, such as those caused by electromagnetic interference. Like any opamp macromodel, the one proposed in this work was developed with the purpose of not sharing neither the technology parameters nor the circuit topology of the real device. Besides the baseband macromodel, the proposed solution comprises a high frequency equivalent circuit that propagates the out-of-band signals, and a nonlinear model to account for their demodulation. The proposed solution is suitable for any SPICE-like simulator. It does not affect the simulation performance, meaning the simulation time, the simulation accuracy and it does not cause any convergence issue. This article shows in detail the macromodel, the method to calculate its parameters as well as its experimental validation, which was obtained comparing the model predictions with the results of the measurements carried out on a commercial device. [ABSTRACT FROM AUTHOR]

In this letter, the modeling and design of a low-power, compact folded cascode operational amplifier with high immunity to electromagnetic interference (EMI) is presented. The insights derived from the modeling of parameters $V_{gsi}$ , $V_{sbi}$ , and $V_{dsi}$ of the first-stage folded cascode OpAmp with channel length modulation are employed in designing the proposed compact folded cascode OpAmp with 23% reduction in power and 10% reduction in area when compared to the robust folded cascode OpAmp. In addition, a comprehensive comparison of the proposed compact folded cascode OpAmp, classical folded cascode OpAmp, and the robust folded cascode OpAmp is presented when each of these OpAmps are subjected to an EMI of 1.7 Vpp. The postlayout simulation results show that the maximum EMI-induced output offset voltage for the compact folded cascode OpAmp is 6.6 mV over a wide range of frequencies from 1 MHz to 1 GHz by keeping the main specifications intact as that of a robust folded cascode OpAmp. [ABSTRACT FROM AUTHOR]

In this work, a compact model is presented for a 14-nm CMOS-based fin resonant body transistor (fRBT) operating at a frequency of 11.8 GHz and targeting radio frequency (RF) generation/filtering for next-generation radio communication, clocking, and sensing applications. Analysis of the phononic dispersion characteristics of the device, which informs the model development, shows the presence of displacement component coupling due to the periodic nature of the back-end-of-line (BEOL) metal phononic crystal (PnC). An eigenfrequency-based extraction process, applicable to resonators based on electrostatic force transduction, has been used to model the resonance cavity. Augmented forms of the Berkeley short channel IGFET model (BSIM)-common multigate (CMG) model for FinFETs are used to model the drive and sense transistors in the fRBT. This model framework allows easy integration with the foundry-supplied process design kits (PDKs) and circuit simulators while being flexible toward change in transduction mechanisms and device architecture. Ultimately, the behavior is validated against RF measured data for the fabricated fRBT device under different operating conditions, leading to the demonstration of the first complete model for this class of resonant device integrated seamlessly in the CMOS stack. [ABSTRACT FROM AUTHOR]