Search

Transistor random threshold voltage variations due to process fluctuations seriously affects the stability of Static Random Access Memory (SRAM). In this paper, a SRAM bit transistors threshold voltage $({Vth})$ deviation monitoring scheme and system is proposed. This scheme ingeniously achieves on-chip measurement of all transistors threshold voltages without altering compact SRAM bit array layout. Control signal strategies and Transistor ${Vth}$ Determination Circuit (TVDC) for different types of Devices Under Test (DUTs) have been proposed. The system is implemented using a 65 nm CMOS process with a core area of 0.01875mm2. Through Monte Carlo analysis, the Weighted Average (WA) difference of the proposed scheme and the direct measurement method is not more than 10mV, and the Root Mean Square Error (RMSE) difference is not more than 3mV. This system can also effectively detect the cell position of the transistor threshold voltage mismatch simulated by modifying the substrate voltage. For SRAM arrays of different scales, the method proposed in this paper has area efficiency and flexible reconfigurability. [ABSTRACT FROM AUTHOR]

The separation of the data capture and analysis in modern vision systems has led to a massive amount of data transfer between the end devices and cloud computers, resulting in long latency, slow response, and high power consumption. Efficient hardware architectures are under focused development to enable Artificial Intelligence (AI) at the resource-limited sensing devices. One of the most promising solutions is to enable Processing-in-Pixel (PIP) scheme. However, the conventional schemes suffer from the low fill-factor issue. This paper proposes a PIP based Complementary Metal-Oxide-Semiconductor (CMOS) sensor architecture, which allows convolution operation before the column readout circuit to significantly reduce the overall power consumption while improving the resource utilization of the succeeding deep learning accelerator. The simulation results show that the proposed architecture could support the computing efficiency up to 3.37 TOPS/W at the 8-bit weight configuration, which is four times as high as the conventional schemes after normalization. The transistors required for each pixel are only 3.5T, significantly improving the fill-factor. [ABSTRACT FROM AUTHOR]

The missing capability of DC fault current limitation is an inherent disadvantage in the typical half-bridge modular multilevel converter (MMC), which restricts its application in long-distance high voltage direct current (HVDC) systems. The full-bridge submodule (FBSM) and clamped double submodule (CDSM) topologies allow for fault current self-clearing, but also suffer from additional hardware cost and power losses. In this paper, an improved submodule topology utilizing the new reverse-blocking insulated gate bipolar transistor (RB-IGBT) is proposed to improve system economy without compromising its performance. The operating principles and DC fault characteristics of the proposed topology are analyzed in details, including comparison with various topologies in terms of cost, losses, fault current clearing speed and thermal. Compared with the traditional CDSM topology, the proposed RBSM can clear DC faults faster with reduced cost of switching devices. A DC fault protection strategy for MMC-HVDC system is also presented. Simulation results under normal operating, permanent and transient fault conditions are carried out to verify the effectiveness of the proposed topology. [ABSTRACT FROM AUTHOR]

Microelectromechanical devices are known to be sensitive to ambient humidity. This is especially true for devices in moisture sensitive plastic packages such as consumer targeted inertial measurement units. Stress and deformation based effects are shown to be a main contributor to humidity related effects such as performance and offset drifts. This paper shows that stress sensing units embedded in the mechanically coupled electronic control circuitry can be utilized to detect and compensate stress based humidity performance drifts of plastic packaged inertial measurement units. Next to the utilized stress sensor cells themselves a compensation approach is presented, that corrects the humidity based scale factor drift of a MEMS angular rate sensor while a humidity load is applied. This is achieved by finding a symbolic compensation function, which predicts the moisture induced scale factor drift, based only on the stress values within the electronic control circuitry, utilizing genetic symbolic regression. It is demonstrated that, using stress sensors, the humidity induced scale factor drift of two different gyroscope core types can be reduced by a factor of 3, which holds true for parts coming from separate assembly lots. [2022-0013] [ABSTRACT FROM AUTHOR]

Objective: This paper presents a Proof-of-Concept (POC) design and implementation of a biosensing and communication system that can be used for biotelemetry in neural and Gastrointestinal (GI) applications. Methods: Our proposed system is based on backscattering from a semi-passive Radio-Frequency-Identification-Device (RFID) implemented using an Application Specific Integrated Circuit (ASIC) in which electronic switching between transistor gates in high and low states create an impedance difference, thereby effectively changing the ASIC's Radar Cross Section (RCS) and thus modulating its backscattered field. The ASIC is used in conjunction with a biosensor to measure and transmit vital signs from within the body. With this system, we conducted backscatter propagation experiments through different biological and phantom tissues (in ex-vivo and in-vitro) in the GI and neural environments. Results: Our results show that the backscattered waveforms can penetrate tissues of various compositions and thicknesses with power received at distances of up to 55 cm away from the RFID ASIC. Furthermore, results from single- and multi-bit biotelemetry measurements showed a high signal fidelity with low Bit-Error-Rate (BER) while being able to resolve varying tissue temperatures measured by the biosensor in our system. Conclusion: We realized a POC system in which on-chip transistor switching in an ASIC can be used to achieve backscatter communication and biosensing. This system is deployable in neural and GI applications. Significance: Our findings in this work will provide an important practical basis for the design and development of RFID ASIC for biosensing and biotelemetry in medical applications. [ABSTRACT FROM AUTHOR]

This brief presents an NMOS-only voltage reference with small process variations for ultra-low-power applications. All MOSFETs work in the subthreshold region and are biased by the leakage current of the NMOS transistor manufactured in Deep-N-Well (DNW). By fitting the variations of threshold voltage ($\text{V}_{\mathrm{ TH}}$) from slow/fast corners to typical corners linearly, an optimum body selection (OBS) is proposed to reduce the impact of the process variations from $\text{V}_{\mathrm{ TH}}$ or $\Delta \text{V}_{\mathrm{ TH}}$ with the aid of the body effect. The proposed design was fabricated in a 0.18- $\mu \text{m}$ CMOS process, together with a baseline design without using the OBS. Based on the 25-chip measurement results, the output voltage variation of the proposed design is $0.0035 \sigma /\mu $ , which is 61% smaller than that of the baseline design. Besides, for the proposed design with the OBS, the power consumption is 23pW (27°C), while the die area is 0.003mm2. The temperature coefficient is 52ppm/°C in a temperature range from 0°C to 85°C without trimming. The line sensitivity is 0.03%/V, and the power supply rejection ratio is 47dB at 100Hz. [ABSTRACT FROM AUTHOR]

This brief presents a 12-bit successive approximation register (SAR)-based time-interleaved (TI) analog-to-digital converter (ADC) with a fully programmable interleaving factor. A total of six SAR sub-ADCs can be time-interleaved. The interleaving factor is programmable from 2 to 6, resulting in an overall sampling rate from 300 to 900MS/s. On-chip offset, gain, and timing skew background calibrations allow reducing the interleaving spurs to less than −73dBc in every configuration. In particular, the proposed difference-based skew calibration efficiently operates in any configuration, not being limited to power-of-2 interleaving factors. Fabricated in a 28-nm bulk CMOS process, the presented TI-ADC achieves a Nyquist-frequency signal-to-noise plus distortion ratio (SNDR) and a spurious-free dynamic range (SFDR) of 52.01dB and 58.82dBc at 900MS/s, respectively, with an active area occupation of 0.48 mm $^{\mathbf {2}}$ and similar metrics across all the configurations. Featuring a power dissipation of 42.96mW at 900MS/s, the Nyquist-frequency Schreier figure of merit (FoM) is 152.2dB, whereas the Walden one is 146.6fJ/Conv-step. [ABSTRACT FROM AUTHOR]

Processing-in-memory (PIM) seeks to eliminate computation/memory data transfer using devices that support both storage and logic. Stateful logic techniques such as IMPLY, MAGIC and FELIX can perform logic gates within memristive crossbar arrays with massive parallelism. Multiplication via stateful logic is an active field of research due to the wide implications. Recently, RIME has become the state-of-the-art algorithm for stateful single-row multiplication by using memristive partitions, reducing the latency of the previous state-of-the-art by ${5.1\times }$. In this brief, we begin by proposing novel partition-based computation techniques for broadcasting and shifting data. Then, we design an in-memory multiplication algorithm based on the carry-save add-shift (CSAS) technique. Finally, we develop a novel stateful full-adder that significantly improves the state-of-the-art (FELIX) design. These contributions constitute MultPIM, a multiplier that reduces state-of-the-art time complexity from quadratic to linear-log. For 32-bit numbers, MultPIM improves latency by an additional ${4.2\times }$ over RIME, while even slightly reducing area overhead. Furthermore, we optimize MultPIM for full-precision matrix-vector multiplication and improve latency by ${25.5\times }$ over FloatPIM matrix-vector multiplication. [ABSTRACT FROM AUTHOR]

This brief presents offset and gain FPN calibrated linear-logarithmic image sensor. Offset FPN originated from threshold voltage variation of the logarithmic conversion transistor is calibrated with Two-step charge transfer operation. Remaining gain FPN is analyzed and its root cause is investigated. The subthreshold slope difference of the logarithmic conversion transistors in the shared pixel architecture is found to be responsible for the increasing FPN in the logarithmic operation region and potentially limiting dynamic range in high illumination region. A simple modeling-based gain FPN correction method in linear-logarithmic APS using shared pixel architecture has been proposed. The prototype sensor is fabricated by using a 0.13- $\mu \text{m}$ CMOS image sensor process. Thanks to the proposed gain FPN correction together with offset correction using Two-step charge transfer operation, wide dynamic range of more than 120 dB has been achieved while maintaining the total FPN less than 0.29% over the entire dynamic range. [ABSTRACT FROM AUTHOR]

This brief presents a picowatt CMOS voltage reference with ultra-low supply and wide temperature range. Biased by PMOS leakage current, ultra-low voltage and ultra-low power consumption are achieved. The temperature range is enlarged by using the increased bulk diode leakage current modulation (BDLCM) effect at high temperature. The proposed design is implemented in a standard 0.18-μm CMOS process. The measurement results show that, the proposed circuit can provide an average voltage reference of 118.1 mV with a standard deviation of 1.3 mV. The minimum supply voltage is 250 mV and the line sensitivity (LS) is 0.3 %/V. The average temperature coefficient (TC) is 73.5 ppm/°C with a standard deviation of 11.7 ppm/°C within a temperature range from −40 °C to 140 °C. The power supply ripple rejection (PSRR) at 100 Hz is −65 dB. The power consumption at room temperature is 113 pW and the active area is 0.0009 mm2. [ABSTRACT FROM AUTHOR]

The requirements on data-driven Machine Learning models for industrial applications are often stricter, compared to those used for academic purposes, as model reliability is critical in industrial environments. Herein is introduced a framework which enables automated data generation with the goal of efficiently providing a data set sufficient to build a reliable and actionable model. Essential to this framework is the placement of the model training/testing data points, which need to be well distributed across the defined input parameter space. The framework is applied to semiconductor fabrication, wherein TCAD, a set of simulation tools that reproduce the physical processing and the final electrical performance of semiconductor devices, is a well-established capability. Transistor-level processing data is reproduced with TCAD simulations, from which the Machine Learning model is built. The framework described here assures that the resulting Machine Learning model fulfills the accuracy requirements across the parameter space. As an example application, the final Machine Learning model is then used to modify the process for a transistor, to obtain both better electrical performance and reduced variability. [ABSTRACT FROM AUTHOR]

Induction heating appliance operation is constrained by the nonlinear pot material behavior under the generated magnetic field. The equivalent load seen by the inverter varies with the intensity of the field, meaning that this variation is dependent on the mains voltage. In flexible-surface induction cooktops, this fact is combined with a high coil number and different pots to be powered simultaneously, increasing the complexity to control the transmitted power while maintaining proper mains current consumption. In this article, two noncomplementary asymmetrical modulations with in-cycle parameter variation are proposed for improved power factor correction while avoiding the need for switching frequency variation and intermodulation noise in multiload systems. The proposed strategies are analyzed and experimentally tested using a 3.6 kW multi-inverter prototype featuring five induction coils. [ABSTRACT FROM AUTHOR]

This article presents two techniques to address the reliability issues caused by dv/dt under fast switching conditions of gallium nitride high electron mobility transistors. The first technique called active overdrive voltage control is proposed to adjust the gate driving strength according to the rising speed of the switching node (dv/dt) adaptively and, thus, decrease the dv/dt without increasing too much switching loss. The second technique is three-branch high-voltage level shifter (TBLS), which can improve the dv/dt immunity without compromising the signal transmission speed. The common mode current caused by dv/dt can be copied and then compensated by a transient current provided by the auxiliary branch. Combining the above techniques, a 400 V half bridge gate driver IC is fabricated by silicon-on-insulator BCD process. Compared with the gate driver IC utilizing the conventional open-loop output stage, the proposed gate driver IC reduces the turn-on switching loss by 16.2% for the same level of peak dv/dt at 400 V 10 A application. In addition, the proposed TBLS can achieve the dv/dt immunity up to 100 V/ns meanwhile the propagation delay less than 14 ns, enabling megahertz operation frequency. [ABSTRACT FROM AUTHOR]

This brief presents a broadband SiGe power amplifier that achieves 30.1 dBm peak $\text{P}_{SAT}$ , 38.6% peak power-added efficiency (PAE), 90.9% large-signal fractional bandwidth (FBW) and a 3 dB bandwidth from 5.4 to 13.8 GHz. A balanced topology with two-stage, four-way combing is utilized to achieve watt-level output power and high-power efficiency in a wide range of operating frequency. Power stage is optimized and simulated from the perspective of high output power. At the output stage, a 90° coupler and two transformers are co-optimized for broadband output power combining as well as power matching. This balanced PA is implemented in a 0.13- $\boldsymbol {\mu }\text{m}$ SiGe BiCMOS process with a chip area (with pads) of 2.31 mm2. [ABSTRACT FROM AUTHOR]

A simple yet effective approach for programmable gain amplifier (PGA) with a high precision decibel (dB)-linear characteristic and wide bandwidth is presented in this brief. This novel approach is presented by innovatively combining two techniques. Based on the binary-weighted switching technique, the circuit can approach an accurate pseudo-exponential function without using an additional exponential generator for gain control. By adopting the active feedback circuit structure, the bandwidth of PGA can be extended and it also contributes to improve the robustness, both of which cleverly reached a good consistency. The proposed PGA is fabricated in a $0.18~{\mu }\text{m}$ CMOS technology, the core circuit occupies an area of 0.11 mm2. Operated at a supply voltage of 1.8 V, the PGA consumes 8.21 mW. The measurement results show that the voltage gain of the proposed PGA can be controlled from −4.2 dB to 25.9 dB with a gain error less than ±0.09 dB, and the minimum −3dB bandwidth is almost 630 MHz. The input 1dB compression point is measured from −28.7 to 0.5 dBm, while the input referred noise is from 22.4 to 70.9 nV/ ${{\sqrt {}}}$ Hz. [ABSTRACT FROM AUTHOR]

This brief presents a track and hold (T/H) circuit for time-interleaved analog-to-digital converters based on a new linearization technique—time-divided post-distortion cancellation. Fabricated in 65 nm CMOS, it achieves 82.1 dB SFDR with a 700-mV near-Nyquist input at a clock speed of 2 GS/s, while drawing only 9 mW power from a 1.5-V supply. Compared to the previous state-of-the-art circuits, this T/H circuit exhibits an energy-efficiency figure-of-merit improvement of 9.5 dB. [ABSTRACT FROM AUTHOR]

An analog baseband (ABB) spectrum sensing circuit is proposed for fast spectrum sensing. Contrast to the conventional RF scanner where it takes a relatively long period to detect channel and interference condition by sequentially controlling the center frequency of the filter, the proposed ABB circuit can scan it at a time using different bandwidths of low-pass filters with an almost equal out-of-band attenuation slope to sense the powers and frequencies of channel and interference. The ABB circuit is composed of two chains of five cascaded real and complex low-pass filters. The cut-off frequencies of five cascaded low-pass filters are set to be 10, 8, 6, 4 and 2 MHz respectively, regarding the channel bandwidth of 2 MHz. The orders of the five filters are optimized to be $4^{\mathrm{ th}}$ , $4^{\mathrm{ th}}$ , $3^{\mathrm{ rd}}$ , $2^{\mathrm{ nd}}$ , and $2^{\mathrm{ nd}}$ order respectively to make the rejected out-of-band power same for each filter for accurate detection. The filter core is designed on the basis of a flipped voltage follower and a super source follower for a low power dissipation and a high linearity, and the low power technique for implementing high-order filter is newly proposed in the design of filter chain. The measured frequency response at each output of the filter chain was almost the same to the simulation result. The measurement results show a noise figure (NF) of 19.2 dB, 22.1 dB, 24.8 dB, 25.1 dB, and 27 dB for each filters, and an in-band input-referred third-order intercept point (IIP3) of 9.2 dBm, 7.2 dBm, and 15.7 dBm at the output of $1^{\mathrm{ st}}$ , $3^{\mathrm{ rd}}$ , and last stages. The total power consumption of the filter chain is 10.4 mW from a 1.2 V supply voltage. [ABSTRACT FROM AUTHOR]

In this brief we propose a completely novel approach to design robust analog circuits made up only of digital CMOS gates taken from conventional standard-cell libraries. The approach exploits the topology of CMOS NOT, NOR and NAND gates to derive a basic building block, namely basic amplifier ($BA$) cell, which is equivalent to a CMOS inverter (used as a transconductance amplifier) with an additional input which allows to accurately set its static output voltage and to obtain a balanced input-output voltage transfer characteristic. We propose also a standard-cell-based control loop based on a replica bias technique which, despite PVT variations, allows to guarantee a static output voltage equal to half the supply voltage for all the $BA$ cells used in the analog section of the chip. The approach has been validated through parametric and corner simulations referring to a 130 nm CMOS process and the performed analyses have highlighted that the proposed BA cell attains reliable performance under PVT variations, whereas the conventional inverter gate taken from the standard-cell library performs in a very unreliable way in the same PVT conditions. [ABSTRACT FROM AUTHOR]

This brief introduces a compact S-parameter model of the two-port 90° N-Path circuit within the vicinity of the clock frequency. Transfer and reflection coefficients, which manifest the circuit filtering properties and the non-reciprocal phase shifting, are derived for a circuit that utilizes ideal switches and then extended to account for transistor parasitics. New simplified equations for parasitic phase and frequency shifts, which are of interest in the design of circuits such as electronic circulators, are proposed. Good agreement is demonstrated between the analytic coefficients and simulation results of behavioral 4-path as well as 65-nm NMOS 8-path circuits, both excited by a 1 GHz clock. The proposed expressions are utilized to compare an electronic circulator that includes an analytic 8-path model versus one that employs an NMOS switched circuit. Agreement of better than 0.2dB is demonstrated for insertion losses whereas isolation results differ by less than 2 dB over an 80 MHz bandwidth centered at 980 MHz. [ABSTRACT FROM AUTHOR]

This brief presents a 2.0~42.0 GHz ultra-wide bandwidth Cascode distributed low-noise amplifier (CDLNA) MMIC design. With the proposed coupled-line (CL) sections between each drain-artificial transmission line (D-ATML) node and related gate-artificial transmission line (G-ATML) node, the traveling signal is reused to enhance the gain and broaden the operation bandwidth simultaneously. To improve the gain further, the inductive gain peaking has also been employed at each drain of common-source (CS) and common-gate (CG) transistors. Meanwhile, an active termination technique incorporating active and passive elements has been adopted to achieve better noise figure (NF) performance. Employing the proposed techniques, an LNA prototype has been designed and fabricated in a 0.15- $\mu \text{m}$ GaAs E-Mode pHEMT technology with the chip size of 1.53 mm2 including all the pads. From test results, the proposed CDLNA demonstrates a peak gain of 14.1 dB, the best NF of 2.1 dB, a group delay of 102 ± 58.4 ps, and 23.25/14.7 dBm best OIP3/OP1dB, respectively. The total power consumption is 129 mW under 3 V VDD. [ABSTRACT FROM AUTHOR]

This brief presents a high-gain 180-GHz low-noise amplifier with Z-embedding technique. A recursive approach provides an accurate and practical estimation of the maximum available gain with the embedding network while losses of interconnects and embedding components are considered. With the proposed procedure, the essential source embedding capacitance is reduced significantly and therefore practically available. In noise parameters analysis, the equivalent noise resistance is proved to dominate the noise figure deterioration due to the Z-embedding network. The interstage networks are designed to achieve the optimal noise figure. The proposed low-noise amplifier is implemented in a standard 40-nm CMOS technology. This amplifier shows a measured gain of 14.8 dB at 180 GHz, a 3-dB bandwidth of 11 GHz, and a simulated minimum noise figure of 11.0 dB. A low dc power of 23.9 mW is consumed under a 0.9-V supply. [ABSTRACT FROM AUTHOR]

Although design automation is a key enabler of modern large-scale digital systems, automating the transistor-level circuit design process still remains a challenge. Some recent works suggest that deep learning algorithms could be adopted to find optimal transistor dimensions in relatively small circuitry such as analog amplifiers. However, those approaches are not capable of exploring different circuit structures to meet the given design constraints. In this work, we propose an automatic circuit design framework that can generate practical circuit structures from scratch as well as optimize the size of each transistor, considering performance and reliability. We employ the framework to design level shifter circuits, and the experimental results show that the framework produces novel level shifter circuit topologies and the automatically optimized designs achieve $2.8\times $ – $5.3\times $ lower power-delay product (PDP) than prior arts designed by human experts. [ABSTRACT FROM AUTHOR]

With the emergence of the multicore architecture and the increase of chip operating frequency, power optimization has become a key step of circuit logic synthesis. Aiming at the XNOR/OR circuits, with the goal of minimizing power, construct the optimal polarity fixed-polarity Reed–Muller (FPRM) circuits power optimization scheme. However, the power optimization for FPRM circuits is a multipeak combinatorial optimization problem, we first propose a metaheuristic optimization algorithm (MOA), which includes the global exploration optimizer, local deep exploitation optimizer, and initial population and uses the proposed differential evolution optimization, fierce wolf siege algorithm-based tabu search, and improved skew tent map to make the population evolve. Based on the proposed Huffman tree construction algorithm and MOA, we propose an efficient power optimization approach (EPOA) to find the minimum power FPRM circuit. Experimental results on the benchmark circuits confirm the effectiveness of EPOA. [ABSTRACT FROM AUTHOR]

This article proposes an online diagnosis scheme for transistor faults of asymmetric half-bridge converter (AHBC) in switched reluctance motor (SRM) drives. In order to extract more information from the phase current to identify faults, based on the conventional current measurement method, two novel current measurement methods are presented by reconstructing current sensors. According to the novel current measurement methods, a current prediction method is raised. The phase current at the kth sampling time is available so that the estimated current can be calculated. The fault can be detected and located by analyzing the given and actual switching states, which are deduced by comparing the measured and estimated currents. Compared with existing methods, the proposed scheme can be applied to diagnosis of multiple faults in n-phase AHBC, which can operate at various control strategies and chopping modes. With a single current sensor in each phase, the scheme will not increase the cost and complexity of the SRM drive. Furthermore, the scheme does not require complicated computation, making it easy to implement online. The experimental results confirm the effectiveness and flexibility of the proposed scheme. [ABSTRACT FROM AUTHOR]

Class-E power amplifiers are widely used in megahertz frequency power conversion systems due to their high efficiency, which can further be enhanced by virtue of wide-bandgap devices such as GaN high-electron-mobility transistors. Here, a GaN-based cross-quadrant mode Class-E amplifier is proposed, which addresses one of the major challenges for such amplifiers, i.e., to achieve both high power and high efficiency with low-voltage-rating devices. By utilizing the reverse conduction of GaN transistors, a cross-quadrant mode Class-E amplifier with small dc-feed inductance is constructed, whose circuit model is derived by virtue of the Laplace transform technique. We demonstrate an experimental prototype operating at 3.11 MHz with a 100-V GaN transistor, achieving an output power of about 6 W with the efficiency being almost 90% when the input voltage is 10 V and the load resistance is 28 $\mathrm{\Omega }$. Compared with conventional Class-E amplifiers, the power conversion capability of the proposed amplifier is increased up to three times from 0.49 to 1.69 with a slight reduction in efficiency. Such cross-quadrant mode amplifiers can be used to improve the power conversion capability and to reduce the peak switch voltage at the same output power level. [ABSTRACT FROM AUTHOR]

This brief investigates the characteristics and impact of the metastabity of true single-phase clock DFFs used for catch detection in Vernier TDCs, and proposes a metastability error correction technique that automatically eliminates the metastability-induced errors of Vernier TDCs. The effectiveness of the proposed technique is assessed using an 8-stage Vernier TDC with metastability error correction catch-detect DFFs. The TDC is designed in a TSMC 130 nm 1.2 V CMOS technology and analyzed using Spectre from Cadence Design Systems with BSIM3.3 device models. Simulation results demonstrate the proposed technique completely eliminates metastability-induced errors of Vernier TDCs at the cost of an additional power, area, and delay. [ABSTRACT FROM AUTHOR]

This brief presents a 40.68-MHz active rectifier with a near-zero-quiescent-current inverter-based conduction-time generator for wirelessly powered implantable devices. By using the proposed scheme, the rectifier achieves near-optimum switching operation with negligible turn-on and -off delays and thus high power conversion efficiency even at very high frequency such as 40.68 MHz. The active rectifier was fabricated in a standard 0.18 $\mu \text{m}$ CMOS process. With a 500- ${\Omega }$ load resistor, the measured power conversion efficiency is higher than 87% through the whole input range of 1.2 V to 1.8 V, and a peak efficiency of 93.3% is achieved with 1.2 V input amplitude. [ABSTRACT FROM AUTHOR]

The miniaturization of CMOS have lead to high leakage and process variation at sub-micron technology. Hybrid circuits including CMOS and magnetic tunnel junction (MTJ), a spintronic device have been put forward to conquer aforesaid limitations. MTJs have appeared to be most assuring candidates owing to it’s compatibility with CMOS and almost zero leakage power. In this brief an offset compensating magnetic full adder (OCMFA) (a hybrid circuit of CMOS and MTJ) has been proposed, which compensates the offset voltage occurring due to process variation and mismatch. The proposed OCMFA compensates the offset voltage in the precharge mode by pre-charging the outputs associated with high resistance branch at a higher voltage and that with lower resistance branch at a lower voltage. The asymmetrical pre-charging of output nodes is assisted by the write current, to provide input to MTJs and load connected diodes. Thus, it is robust against process variation and upgrades the performance of MFA. Power, delay, variability, and corner analysis are performed utilizing UMC 40nm CMOS technology kit at the cadence virtuoso platform and the compact model of perpendicular magnetic anisotropy (PMA) MTJ. This brief contributes in the reliability analysis of proposed MFA with the earlier reported MFA. The proposed OCMFA provides 65% lower PDP and shows 84.6% higher reliability as compared to conventional precharge sense amplifier based magnetic full adder (PCSA-MFA). [ABSTRACT FROM AUTHOR]

This brief presents a 2.16 $\mu \text{W}$ low-power third-order single-bit continuous-time delta-sigma modulator (CTDSM) for electrocardiogram (ECG) signal acquisition application. The proposed CTDSM uses an active-RC (A-RC) integrator as a first integrator and an improved linearized $G_{m}$ -C integrator for the second and third integrators, respectively. The mixed-integrator structure helps to mitigate the trade-offs between power consumption and resolution. Moreover, a source-degenerated auxiliary differential pair circuit is used for the $G_{m}$ -C integrators to improve their linearity. By using A-RC and $G_{m}$ -C integrators together along with an improved-linearized $G_{m}$ block, the total power consumption was measured as 2.16 $\mu \text{W}$ with a peak signal-to-noise ratio of 80.1 dB, signal-to-noise, and distortion ratio of 78.4 dB, and a dynamic range of 81.4 dB with a bandwidth of 250 Hz. Furthermore, a real-time ECG signal was successfully captured in an ECG acquisition system that consisted a heart-rate sensor and a signal acquisition circuit, including the proposed CTDSM. [ABSTRACT FROM AUTHOR]

This brief presents a high current-efficiency rail-to-rail class-AB op-amp with dual-loop control. Based on the conventional folded cascode op-amp with gain-boost, a dual-loop control strategy consisting of a gain-boost loop and an adaptive output stage current control loop is proposed to achieve bidirectional large load driving capability and high DC gain. Furthermore, the adaptive output stage current control loop achieves class-AB operation with symmetric separate signal paths to the output transistors and high reconfigurability. In addition, the implementation of the constant transconductance ($\text{g}_{\mathrm{ m}}$) rail-to-rail input and slew rate (SR) enhancement circuit is adopted to widen the input voltage range and improve the large-signal transient response. The proposed op-amp is fabricated in a 0.18- $\mu \text{m}$ 5 V CMOS process with an active area of about 0.25*0.27 mm2. Measured results show the proposed op-amp achieves over 122 dB DC gain, 1 MHz gain-bandwidth, and 2.1 V/ $\mu \text{s}$ SR under bidirectional load conditions (100pF and 10k $\boldsymbol{\Omega }$). At 1.5 V and 5.5 V supplies, positive current-efficiency (CE+) are 15 and 1780, negative current-efficiency (CE−) are 37 and 1658, power consumptions are 59.2 $\mu \text{W}$ and 225.5 $\mu \text{W}$ , respectively. [ABSTRACT FROM AUTHOR]

A 28-GHz $2\times 8$ bit quadrature RF-DAC is presented, which has an analog LO leakage cancellation circuit. It is based on a double-balanced Gilbert cell structure where current bleeding paths are introduced to prevent the cells from being completely turned off. LO leakages of the RF-DAC are canceled by controlling the current bleeding paths. It was fabricated in a 28-nm bulk CMOS process and achieved a −5.6-dBm CW output power with 12-mW power consumption from a 1.1 V supply and 3-Gb/s maximum data rate with 64-QAM signals. −45-dBc LO leakage was achieved using the proposed leakage cancellation technique. [ABSTRACT FROM AUTHOR]

This brief proposes a broadband differential GaN power amplifier (PA) with coupled-line-based matching networks for Ku-band satellite communication. The developed matching technique can achieve flat wideband impedance matching with a compact area. Also, this brief employs a combination of series and parallel power combining topology to improve the impedance conversion ratio of the output matching network, thereby reducing the insertion loss. As proof of the above concept, our two-stage PA is realized in a 0.25- $\mathbf {\mu }\text{m}$ GaN pHEMT process. The PA scores 18.2-to-21.2 dB gain, 38.6-to-39.9 dBm saturated output power ($\text{P}_{\mathrm{ sat}}$), and 35%-to-42% peak power added efficiency (PAE) from 10.5 to 15.5 GHz. The PA shows a flat RF performance across 10.7-to-14.9 GHz with $\mathbf { < }1$ dB gain ripple and $\mathbf { < }0.7$ dB $\text{P}_{\mathrm{ sat}}$ ripple. Meanwhile, the total chip size is $2.7\mathbf {\times }2.4$ mm2, corresponding to a power density up to 1.47 W/mm2. [ABSTRACT FROM AUTHOR]

In this brief, we combine a buffered asymmetric dual-path structure with cascode Miller compensation to extend the unity-gain bandwidth of a three-stage amplifier while decreasing its power consumption. This design is implemented in a 65 nm CMOS technology with 0.0017 mm2 chip area and 6.62 ${\mu }\text{W}$ power consumption. Post-simulation results achieve ${>}100$ dB DC gain, 1.20 MHz UGB, and 0.391 V/ ${\mu }\text{s}$ SR with a 1.5 nF load capacitor. [ABSTRACT FROM AUTHOR]

Self-heating (SH) is a phenomenon that can induce excessive heat inside the transistor channel. SH represents an emerging and serious concern, especially in advanced technology nodes, where excessive heat acting on elevated channel geometries will notably shift the critical transistor parameters (e.g., threshold-voltage $V_{\text {th}}$ and carrier mobility $\mu $). The underlying 3-D device structures (e.g., FinFET, nanowire, or nanosheet structures), along with newly employed materials such as silicon-germanium (SiGe), which show worse thermal conductivity than traditional materials, can considerably exacerbate SH. On top of that, quantum confinement, a phenomenon that becomes dominant at sub-10nm, further increases the intensity of SH. In this article, we are the first to explore SH effects from the perspective of hardware security, rather than the performance, reliability standpoints covered in state-of-the-art (SOTA) work. As proof of concept, we devise an SH-based hardware trojan (HT) that exploits the SH-induced $V_{\text {th}}$ change in 7-nm FinFET circuits. Leveraging $V_{\text {th}}$ -dependent reconfigurable logic, we design a reconfigurable HT payload that maliciously changes its functional behavior once the SH-induced $V_{\text {th}}$ change takes effect. Following SOTA work, we present a comprehensive modeling and analysis of SH effects at the device level and highlight its impact on transistor $V_{\text {th}}$. Next, we study how fabrication-time changes in the transistor doping and geometry can promote the SH-assisted degradation. We then describe various payload configurations for the proposed HT, quantify its overheads, and discuss its resilience against standard HT detection techniques. Finally, we demonstrate two case studies using the proposed HT, one to leak the secret key from a pipelined design of an advanced encryption standard (AES) circuit, and another to showcase denial-of-service for a Gaussian-blur filter circuit. Our work utilizes industry-standard models with parameters extracted from measurements and calibrated with experiments. Our results are obtained from meticulous study and optimization across the device-, circuit-, and system-levels. [ABSTRACT FROM AUTHOR]

Bayesian optimization (BO) is popular for a analog circuit sizing problem recently. However, BO can only work well in small-scale circuit. Scaling BO to common circuit optimization (typically dimension > 10) is difficult due to the curse of dimensionality. In this article, we proposed a new BO algorithm (cBO), which can scale BO to more larger scale circuit and improve the optimization result. First, according to the fact that a specification of the analog integrated circuit is mainly determined by a few transistors, dropout strategy is adopted in our algorithm. At each iteration, only a subset of selected variables to be optimized. A variables selection strategy based on mutual information analysis and a new fill-in strategy are proposed. Second, the $g_{m}/I_{D}$ methodology-based optimization strategy is proposed. Optimization variables are not width and the length of transistors, but $g_{m}/I_{D}$ , $I_{D}$ and length. $g_{m}$ , $I_{D}$ and $g_{m}/I_{D}$ have a direct relationship to circuit performance. This is equivalent to search in circuit feature space, which could achieve better performance and handle constraints more easily. Four commonly used circuits, including low dropout regulator, two stage amplifiers, Bandgap voltage reference (VR), and VR are used for validation. Compared with other high-dimensional BO, common BO, and commercial tools (Cadence ADE_GXL), the proposed algorithm is found to produce the best optimization result and best stability. And, the ablation study shows the effectiveness and efficiency of two ingredients of the proposed algorithm. [ABSTRACT FROM AUTHOR]

Most of current processing-in-memory (PIM) architectures are application specific, that is, they can only accelerate particular functions, e.g., matrix-vector dot product for neural network acceleration. However, practical applications usually involve various functions. In order to accelerate different functions, various accelerators, and dedicated circuits have been proposed. In this work, by exploring the similarities among some commonly used dedicated circuits, we adopt ferroelectric field-effect transistors (FeFETs) to build a reconfigurable multifunctional memory architecture named Re-FeMAT. Re-FeMAT is composed of multiple processing elements (PEs). Each PE is not only a nonvolatile memory array, but also can perform logic operations (i.e., the PIM mode), convolutions (i.e., the binary convolutional neural network and the convolutional neural network (CNN) acceleration mode) and content search (i.e., the ternary content-addressable memory (TCAM) mode) without changing the circuit structure. Re-FeMAT can support applications that require multiple functions. As an example, by configuring different PEs to different working modes and using a simulated annealing algorithm or a tabu search algorithm to optimize the task-PE assignment, Re-FeMAT can completely accelerate few-shot learning applications. Our simulation results based on a calibrated FeFET model show that the proposed Re-FeMAT architecture achieves better performance and power efficiency than the previous FeMAT architecture. Compared with FeFET-based single-functional circuits, though the power dissipation of Re-FeMAT is higher in some modes, the power-delay product is still smaller. Compared with a state-of-the-art FeFET-based multifunctional accelerator named attention-in-memory, Re-FeMAT achieves lower power, latency, and energy when accelerating a complete few-shot learning task. [ABSTRACT FROM AUTHOR]

In order to reduce defect parts per million, cell-aware (CA) methodology was proposed to cover various types of intracell defects. In this article, we present a novel methodology for generating 2-time-frame (2tf) CA tests based on timing slack analysis. The proposed 2tf CA fault model, aware of timing slack and named TS, defines a fault: 1) on a cell instance basis and 2) based on per-instance timing criticality (according to timing slack). By comparing the derived extra delay against the timing slack of the cell instance, a delay fault can be defined, and according to its severity, the fault can be further classified into small-delay fault or gross-delay fault. In contrast to prior 2tf CA methodology that is on a cell (rather than cell instance) basis and unaware of timing criticality/slack, our methodology can identify “more realistic” faults which really need to be considered, and potentially the cost/effort for testing those 2tf CA faults can be reduced. We also propose a test quality metric, timing slack defect coverage (TSDC), to measure the effectiveness of automatic test pattern generation (ATPG) tests in terms of the ability to detect small-delay TS defects along long paths. Experimental results on a set of 22-nm industrial designs demonstrate that, due to more realistic fault identification, the number of identified small-delay faults can be reduced by 56.8%. With the slack-based ATPG for testing small-delay faults along long paths, TS can reduce the number of test patterns by 33.1% while achieving 0.49% higher TSDC, compared with the results of prior 2tf CA methodology. [ABSTRACT FROM AUTHOR]

This article presents a 10-kW novel gallium-nitride (GaN)-based three-phase grid to 48-V battery energy storage system (BESS). The BESS utilizes a single-stage ac–dc dual-active-bridge (DAB) converter with dual-phase-shift (DPS) and variable-frequency (VF) control. 600- and 80-V GaN power transistors, as well as planar magnetics, are used to achieve 96.6% efficiency and 50-W/in $^3$ power density. The operation principle and power transfer characteristics are derived based on time-domain analysis of the DAB inductor current. VF and DPS are utilized to achieve power factor correction and zero-voltage switching simultaneously while minimizing the DAB rms current. An online calculation algorithm is presented with short execution time, which enables the closed-loop control of the BESS. Experimental results are presented to validate the novel control. [ABSTRACT FROM AUTHOR]

Inspired by the mechanism of visual attentional selection, a color feature selection unit consisting of photoreceptors and an attentional selection circuit (ASC) is presented. The detection and wavelength recognition of trichromatic light are accomplished by the photoreceptors with RGB filters. The ASC, fabricated in a standard CMOS technology, activates the competition among photoreceptors to select the principal color-component feature defined as the attentional focus. The number of focuses and resolution can be changed with a top-down stimulus. Electrical test results show that the ASC can select and interpret the most important color-component feature. In optical tests, the ASC chip-based unit can extract the principal color-component of single-color and dual-color light in real-time to complete color recognition. The percentage ratio between the intensity of stray light relative to the light with maximum intensity is up to 93.58%. And the maximum achievable recognition frame rate is 1 kHz, which is more than one order of magnitude higher than the frequency of the biological vision systems. Besides, the unit's outputs can be transformed into binary codes as labels for color recognition, and the color recognition process does not require the participation of ADC, CPU, and memory, consequently avoiding the von Neumann bottleneck. [ABSTRACT FROM AUTHOR]

This article presents local shielding techniques applied to a half-bridge inverter leg with the aim to reduce the common-mode (CM) current noise at converter’s dc input. The research study is conducted for 650-V enhancement mode Gallium Nitride power transistor switches. Main contributors of parasitic capacitances referred to the inverter-leg middle point node are identified. Then, shielding solutions are proposed to reduce the CM current emission by these capacitances. Respecting the precautions concerning the isolation of CM currents of the half-bridge inverter leg, the electromagnetic compatibility measurement setup is developed. Experimental step-by-step addition of local shielding copper layers to different contributors of middle point capacitance shows progressive attenuation of CM noise spectra. [ABSTRACT FROM AUTHOR]

This brief proposes a broadband noise-cancelling (NC) common-gate (CG)-common-source (CS) low-noise amplifier (LNA) with a passive network to improve the gain and noise performance simultaneously. In the CG-CS LNA with active feedforward, a current-bleeding (CBLD) circuit is required to provide the required DC current of the auxiliary amplifier, which introduces additional noise. In the proposed work, by adding a passive network at the output, the noise of the CBLD circuit can be made negligible. Moreover, the passive network also provides the shunt peaking to facilitate the gain and noise performance over the desired band. Fabricated in TSMC 40 nm CMOS technology, the measured results show the proposed LNA exhibits a gain of 16.5 – 19.5 dB, a noise figure (NF) of 3.2 – 5.2 dB from 2 to 12 GHz and an IIP3 of −3.5 dBm at 6 GHz. It consumes 9 mW from a 1.2 V supply and occupies a very compact die area of 0.092 mm2. [ABSTRACT FROM AUTHOR]

This brief proposes a novel sub-1V discrete-time CMOS bandgap reference circuit where a constant voltage is produced by summation of a CTAT and a PTAT voltage that are sampled onto a capacitor. By sampling the voltages onto a capacitor, we eliminate the need for an opamp in the bandgap core, which tends to be the dominant source of noise and offset concerns in low voltage bandgap designs in scaled technologies. A prototype was designed and fabricated in 28nm TSMC HPC+ technology with a nominal output voltage of 108mV. It demonstrates a temperature coefficient of 8.5ppm/°C between −40°C and 125°C, and occupies an area of 0.0075mm2 while consuming $11.6\mu \text{W}$ of power. [ABSTRACT FROM AUTHOR]

In this brief, a new combiner analysis method for the design of Doherty Power Amplifiers (DPA) is proposed. A compact L-C combiner is used to validate the proposed method through both simulation and realization of a two-stage DPA in a 130nm RF-SOI process. Using a 2.3GHz CW signal, the PA achieves a measured peak PAE of 51% at 32dBm output power under 3.4V supply voltage. From 2.1GHz to 2.5GHz, the PA shows an average output power and PAE higher than 26.9dBm and 39% respectively at −35dBc E-UTRA ACLR when using a 10MHz-50RB QPSK LTE uplink signal with memoryless DPD. At 2.3GHz, the PA achieves a linear Pout and PAE of 28.85dBm and 42.8% respectively. [ABSTRACT FROM AUTHOR]

In the mm-wave frequency band, the rectifier’s sensitivity is the bottleneck of a wireless-powered IoT transponder’s distance. At a meter’s distance, the received power is weak, and transistors in a front end of a wireless power receiver operate in the weak inversion region. This article presents a mathematical analysis of the mm-wave multi-stage rectifier in the low-power region. A design methodology of a 57–64-GHz fully integrated eight-stage rectifier with a bulk-drain connection in 40-nm CMOS technology is presented. Parasitic effects on a multi-stage rectifier are analyzed. Based on the analysis, an intrinsic threshold voltage modulation is applied to improve the sensitivity. A tree-type power splitter is also proposed for the RF power signal’s phase balance. With this method, the RF signal arrives at each stage with an equal phase, and its suppression at the output is improved by 16 dB. This mm-wave rectifier achieves −7.1-dBm input sensitivity at 57 GHz with 1-V dc output voltage. The overall sensitivity from 57 to 64 GHz is better than −4.5 dBm. Compared to other mm-wave silicon-based rectifier state of the arts, the proposed mm-wave rectifier achieves better sensitivity while maintaining a compact size. [ABSTRACT FROM AUTHOR]

A novel power amplifier (PA) with wide bandwidth and load mismatch resilience is presented based on the quasi-balanced Doherty PA (QB-DPA) architecture. By reconfiguring the parallel/series QB-DPA operation modes with the nominal/exchanged biasing alternation and control of phase dispersion, the proposed QB-DPA topology can overcome the bandwidth limitations and ensure a standard Doherty profile and high efficiency and linearity against dynamic load mismatch over the operational bandwidth. Based on the theoretical analysis, a design guidance of output matching topology on phase offset implementation is presented. As a proof of concept, a physical prototype is demonstrated targeting for 1.7–2.7-GHz bandwidth. The developed QB-DPA achieves an efficiency of 56%–78% at $\text {OP}_{\mathrm {1\,dB}}$ and 47%–71% at 6-dB output back-off (OBO) over the in-band operation with 50- $\Omega $ load. Through reconfiguration (parallel/series mode for mismatch recovery and nominal/exchanged biasing for bandwidth extension), the developed QB-DPA demonstrates significantly improved $\text {OP}_{\mathrm {1\,dB}}$ variation both at center frequency 2.1 GHz and edged-frequency 1.7 and 2.6 GHz at 2:1 voltage standing wave ratio (VSWR) over 360° phase span. In modulated measurement using 20-MHz long-term evolution (LTE) signals, $> 44.5\%$ average efficiency and $ < -30.9$ -dBc adjacent channel power ratio (ACPR) are obtained across the wide bandwidth at matched-load condition. More importantly, for VSWR 2:1 circle, the high linearity [ $ < 5.3\%$ error vector magnitude (EVM)] and average efficiency ($> 38.1\%$) can be experimentally maintained through reconfigurations. [ABSTRACT FROM AUTHOR]

Current sourceinverters (CSIs) require power switches with first quadrant current conduction and gate-controlled output characteristics as well as reverse blocking capability. Experimental demonstration of a SiC monolithic reverse blocking transistor (MRBT) suitable for CSI applications is described in this letter. The proposed device is based on the integration of a SiC JBS diode with a SiC power mosfet on the same chip. The cathode of the SiC JBS diode is connected to the drain of the SiC power mosfet by their common N+ substrate. The proposed device structure creates a novel SiC-based unipolar single-chip three-terminal transistor with reverse blocking capability. The measured characteristics of a 1.2 kV 4H-SiC MRBT, fabricated in a commercial six-inch wafer foundry, are reported in this letter. The devices show a diode-like on-state characteristic with a low knee voltage of 1.3 V and an on-state voltage drop of 2.8 V at 5 A. The measured reverse transfer capacitance and output capacitance for the MRBT at a drain bias of 2 and 1000 V are a factor of ∼3x and ∼1.6x smaller than the measured values for the internal mosfet device. Switching measurements show a 12% reduction in the gate-drain charge for the MRBT compared with the internal mosfet which is favorable for reducing switching losses. [ABSTRACT FROM AUTHOR]

A high step-down ratio three-level half-bridge (TLHB) dc–dc converter with a current-doubler rectifier is presented for power conversion from a 48-to-60-V input to a 0.5-to-1-V output. The proposed TLHB topology and operation employed on the primary side improve the power-conversion efficiency by reducing the switching loss while minimizing the turn ratio of the transformer by converting the input voltage down to one quarter on the primary side. Moreover, it reduces the voltage stress on switches by half, thereby enabling the converter to be implemented with Si transistors with low breakdown voltage. The designed TLHB gate-driver IC minimizes the delay mismatches in gate drivers and mitigates the effect of the leakage inductance of the transformer, reducing the voltage imbalance on the flying capacitor without any balancing scheme in the controller. The proposed dc–dc converter implemented with 40-V Si transistors for the primary-side switches achieves 92.8% peak efficiency while supporting the maximum load current of 60 A and the maximum input voltage of 60 V. The converter with the proposed TLHB gate driver IC shows less than 0.8% voltage imbalance on the flying capacitor. [ABSTRACT FROM AUTHOR]

This brief proposes an ultra-low-power current reference in TSMC 180nm technology. Temperature compensation is achieved by taking the ratio of compensated voltage and an on-chip resistance. This design uses the concept of the back-gate effect of critical MOSFET to generate complementary to absolute temperature (CTAT) voltage. The circuit works from a supply voltage of 0.55V and is designed for a reference current of 5.6nA. Furthermore, a pseudo-differential amplifier (PD-AMP) helps realize low line regulation of 0.022%/V in the supply range of 0.55 to 1.9V. An average temperature coefficient (TC) of 256.07ppm/°C is achieved for mismatch and process variations in Monte-Carlo simulations for 1000 samples over a temperature range of −30°C to 70°C. The circuit consumes only 9.5nW of power (at room temperature and minimum supply voltage), making it suitable for ultra-low-power biomedical applications. [ABSTRACT FROM AUTHOR]

This brief proposes a 3-stage dual-branch charge pump (CP) with an advanced dynamic gate-biasing technique (DGB) enabling ultra-low-voltage (0.1 V) energy harvesting. Specifically, we reduce the forward conduction loss and the reverse current leakage loss with the combination of an advanced DGB and an NMOS-PMOS dual-switch transistor pair. Also, we investigate the relationship between the pumping capacitance and the power conversion efficiency (PCE) of the CP, thus guiding the PCE improvement with minimal capacitance. The prototype fabricated in 65-nm CMOS achieves a 43.4% PCE at a 0.1-V input voltage. [ABSTRACT FROM AUTHOR]

With the shortening of chip processes, the number of contained electrons and the supply voltage are decreased. When the energy level of contained electrons is close to the Landauer limit, the traditional analysis method based on empirical equations can no longer accurately analyze the nonequilibrium information processing of transistor logic gates. Based on stochastic thermodynamics theory, we propose an energy consumption model for a single-electron transistor AND gate which can be calculated by the input state transitions. Based on the proposed AND gate energy consumption model, an optimal input sequence operation method is proposed to reduce the energy consumption of three-input AND gate. Simulation results show that the energy consumption of three-input AND gate is reduced by up to 63.39% using the optimal operation method. [ABSTRACT FROM AUTHOR]