Search

Better duplicate elimination performance causes higher fragmentation which leads to degraded restore performance. As a result, restore performance needs to be optimized either through strengthening locality by selective rewriting and/or making the best use of the limited available memory through cache optimization. In this paper, we explore SACRO, SSD Assitsted Chunk Caching for Restore Optimization. It avoids the need to repetitively access chunk containers in disk by using SSD (Solid State Drives) as a secondary chunk cache. An FRT (Future Reference Table) is constructed from the recipe of a backup stream and a Future Reference Count entry in the FRT is utilized to assign priorities to chunks as they are accessed during restoration. These priority values coupled with access distances are used to decide to cache a chunk either in memory or the SSD. The restore performance of SACRO is shown to significantly outperform other restoring approaches which utilize chunk caching. For one dataset, at 4 MB cache size and 4 MB Look Ahead Window size its restore factor is 3.5 MB/container_access while ALACC and LRU record 3.4 MB/container_access and 0.9 MB/container_access respectively. Moreover, SACRO can be integrated to already existing deduplication systems with very limited amount of modification done on the deduplication system. [ABSTRACT FROM AUTHOR]

Video content consumption is currently dominating the mix of traffic observed in Internet service provider (ISP) networks. The distribution of that content is usually performed by means of content delivery network (CDN) caches storing and delivering multimedia. The advent of virtualization is calling attention to the CDN providers as a use case for virtualizing the cache function. In parallel, there is a trend for sharing network infrastructures as a way of reducing deployment costs by ISPs. Then, an interesting scenario emerges when considering the possibility of sharing virtualized cache functions among ISPs which are sharing a common physical infrastructure, mostly considering that those ISPs offer similar video content catalogs to end users. Furthermore, when deciding to share the caches among ISPs, it is interesting to understand the impacts due to limiting the storage capacity at the edge sites. This paper investigates through simulations the potential efficiencies that can be achieved when sharing a virtual cache function if compared with the classical approach of independent virtual caches operated per ISP, as well as the implications of limiting the storage capacity of the caches at the edge. [ABSTRACT FROM AUTHOR]

As a key component of high‐performance switches and routers, the packet forwarding engine (PFE) is mainly responsible for selecting the appropriate output port for tens of thousands of packets within an extremely short time frame. However, the performance of PFE is determined by the selected group membership algorithm. This paper puts forth a hybrid strategy–caching scalar‐pair and vectors routing and forwarding (CSVRF), consisting of virtual output port bitmap caching (VOPBC) and fractional‐N SVRF to address major multicast forwarding issues such as scalability by using content addressable memory. In CSVRF, a virtual output port bitmap cache is introduced, which includes the most popular combinations of output port bitmap and divides the big scalar‐pair into N sub‐groups to achieve parallel compute and the reusability of less bit‐length prime. The results demonstrate that the memory space and the forwarding latency are effectively reduced compared with previous work. In space efficiency, it only required 10% memory space compared with the original SVRF/fractional‐N SVRF, decreased 10% memory usage compared with pure VOPBC and nearly improved 1 to 4 orders of magnitude of packet processing time compared with the original SVRF and the fractional‐N SVRF respectively. [ABSTRACT FROM AUTHOR]

Summary: Cache coherence in modern computer architectures enables easier programming by sharing data across multiple processors. Unfortunately, it can also limit scalability due to cache coherency traffic initiated by competing memory accesses. Rack‐scale systems introduce shared memory across a whole rack, but without inter‐node cache coherence. This poses memory management and concurrency control challenges for applications that must explicitly manage cache‐lines. To fully utilize rack‐scale systems for low‐latency and scalable computation, applications need to maintain cached memory accesses in spite of non‐coherency. This paper introduces Bounded Incoherence, a memory consistency model that enables cached access to shared data‐structures in non‐cache‐coherency memory. It ensures that updates to memory on one node are visible within at most a bounded amount of time on all other nodes. We evaluate this memory model on modified PowerGraph graph processing framework, and boost its performance by 30% with eight sockets by enabling cached‐access to data‐structures. [ABSTRACT FROM AUTHOR]

With the development of mobile edge computing technology, edge caching provides a feasible solution for low‐latency and high‐reliability data forwarding in the Internet of Vehicles (IoV). Due to the limited number and storage capacity of the edge servers, and the limited communication range of a single vehicle, the delay and connection requirements are hard to be satisfied. A vehicle clustering based edge caching scheme is proposed in this paper, aiming at minimizing the content acquisition delay of the requesting vehicles (RVs) within the communication range of the edge servers. After getting the optimal vehicle association results, the minimization of content acquisition delay is transformed into a knapsack problem, which is then solved by a dynamic programming algorithm to obtain the optimal cache decisions. Simulation results show that the proposed scheme reduces task acquisition delay by at least about 100 s and increases the cache hit rate by about 50%, compared with the random cache scheme. [ABSTRACT FROM AUTHOR]

Parallel global optimization of expensive simulation models like nonlinear partial differential equations (PDEs) can speed up model calibration or project design decisions, but the impact of memory management on the efficiency of using parallel global optimization methods has not been previously studied. This paper quantifies cache memory limitations arising during parallel optimization of expensive PDE models. An efficient parallel optimization algorithm is applied to model calibration for two different, expensive real‐world PDEs (i.e., hydrodynamic and water quality analysis for a 250‐hectare lake). One of these two lake models takes 4.5 h per simulation in serial, but that PDE simulation time per simulation increases to 12 h with parallel optimization if default processor scheduling strategy is used on a modern nonuniform memory access multicore platform. We proposed a novel mixed affinity scheduling strategy for parallel simulation optimization that increases computational efficiency by as much as 20% over the default affinity strategy. [ABSTRACT FROM AUTHOR]

Data deduplication is a widely used technique to remove duplicate data to reduce the storage overhead. However, deduplication typically cannot eliminate the redundancy among nonidentical but similar data chunks. To reduce the storage overhead further, delta compression is often applied to compress the post‐deduplication data. While the two techniques are effective in saving storage space, they introduce complex references among data chunks, which inevitably undermines the system reliability and introduces fragmentation that may degrade the restore performance. In this paper, we observe that the delta compressed chunks (DCCs) are much smaller than regular chunks (non‐DCCs). Also, most fragmentation caused by the base chunk of DCCs remain fragmented in consecutive backups. Based on these observations, we introduce a framework called RepEC+, which combines replication and erasure coding and uses History‐aware Delta Selection to ensure high reliability and restore performance. Specifically, RepEC+ uses a delta‐utilization‐aware filter and a cooperative cache scheme (CCS) to maintain cache locality and avoid unnecessary container reads, respectively. Moreover, the system selectively performs delta compression by historical information to avoid cyclic fragmentation in consecutive backups. Experimental results based on four real‐world datasets demonstrate that RepEC+ significantly improves the restore performance by 58.3%–76.7% with a low storage overhead. [ABSTRACT FROM AUTHOR]

Memory prefetcher algorithms are widely used in processors to mitigate the performance gap between the processors and the memory subsystem. The complexities behind the architectures and prefetcher algorithms, however, not only hinder the development of accurate architecture simulators, but also hinder understanding the prefetcher's contribution to performance, on both a real hardware and in a simulated environment. In this paper, we contribute to shed light on the memory prefetcher's role in the performance of parallel High‐Performance Computing applications, considering the prefetcher algorithms offered by both the real hardware and the simulators. We performed a careful experimental investigation, executing the NAS parallel benchmark (NPB) on a real Skylake machine, and as well in a simulated environment with the ZSim and Sniper simulators, taking into account the prefetcher algorithms offered by both Skylake and the simulators. Our experimental results show that: (i) prefetching from the L3 to L2 cache presents better performance gains, (ii) the memory contention in the parallel execution constrains the prefetcher's effect, (iii) Skylake's parallel memory contention is poorly simulated by ZSim and Sniper, and (iv) Skylake's noninclusive L3 cache hinders the accurate simulation of NPB with the Sniper's prefetchers. [ABSTRACT FROM AUTHOR]

Summary: Cache management policy plays a key role in offering low latency access to flash‐based SSDs. Most existing solutions including LRU and its successors only focus on improving the cache hit ratio, but rarely consider to reduce the waiting time of the eviction operation in the page‐level mapping FTLs. As the workloads spreading across internal chips of modern flash‐based SSDs are often highly imbalanced when workloads are write‐intensive, the time cost of evicting a dirty page from cache varies in a wide range. In this paper, we propose a novel eviction‐cost‐aware cache management policy, called ECR, to minimize the eviction cost in write‐dominant applications. ECR gives a higher probability to evict a page, which causes the shortest waiting time in the corresponding chip queue. To achieve this, we introduce a monitor module to keep track of states of all chip queues, and a multi‐LRU list structure to accelerate the selection of a victim chip and a target page in cache to perform an eviction. Our experimental results show that ECR can significantly reduce the average response time by as much as 59.55% and 44.84% compared to LRU and GCaR‐CFLRU, respectively, where GCaR‐CFLRU is the combination of state‐of‐the‐art algorithm GCaR and CFLRU. [ABSTRACT FROM AUTHOR]

Fog computing is a promising technique to reduce the latency and power consumption issues of the Internet of Things (IoT) ecosystem by enabling storage and computational resource close to the end‐user devices with additional benefits such as improved execution time and processing. However, with an increase in IoT devices, the resource allocation and job scheduling became a complicated and cumbersome task due to limited and heterogeneous resources along with the locality restriction in such computing environment. Therefore, this paper proposes a cache‐based approach for efficient resource allocation in fog computing environment, while maintaining the quality of service. The proposed algorithm is realized using iFogSim simulator and a comprehensive comparison is presented with the traditional First Come First Served and Shortest Job First policies. The performance evaluation revealed that with the proposed scheme the execution time, latency, processing delays and power consumption decreased by 38%, 11.1%, 6%, and 17.8%, respectively, as compared to those of the traditional schemes. [ABSTRACT FROM AUTHOR]

Cache‐enabled device‐to‐device (D2D) network has been deemed as an effective technique to offload the data traffic. However, the gain of the caching schemes is closely related to the homogeneity among users' preference distribution. To tackle this issue, recommendation is a promising proactive approach. It increases the request probability of recommended contents, reshaping users' contents demand patterns, and improving caching performance. Moreover, considering the heterogeneous network settings, i.e. content retrieval costs vary, the routing design becomes a non‐negligible factor on caching performance optimization. On these grounds, the average system cost of D2D‐enabled wireless caching networks with multiple BSs is first described. Then the routing strategies are designed together with caching and recommendation policies by minimizing the average cost of these networks. The optimization problem is proven as NP‐hard. To facilitate the analysis, the original problem is decoupled into two sub‐problems and solve them respectively. Afterwards, all the variables are optimized in an alternating manner until the convergence is achieved. The proposed algorithm's convergence performance and benefits over benchmark strategies in terms of total cost and cache hit ratio are supported by Monte‐Carlo simulation results. [ABSTRACT FROM AUTHOR]

The development of the Internet of things brings exponential growth of wireless traffic, which puts great pressure on the backhaul link. The proactive caching of some contents in the edge device of mobile network can effectively reduce the repeated transmission of the same contents and relieve the burden of the backhaul link. Moreover, the introduction of recommendation mechanisms can reshape user's request and improve cache hit ratio. However, the optimization of recommendation and caching decisions is highly dependent on the users' preference information for files. Here, a joint optimization algorithm of recommendation and caching based on users' preference prediction with multiple base stations cooperative caching is proposed. To improve the caching efficiency, the Deep Crossing model is adopted to predict users' preferences. Under the constraints of cache capacity, recommendation quantity and bandwidth, an optimization problem to minimize the total transmission delay of the system is formulated. Then, the NP‐hardness of the proposed optimization problem is proved and it is decoupled it into three sub‐problems, namely recommendation, user access and caching optimization sub‐problems. Simulation results show that the proposed algorithm can effectively reduce the total transmission delay of the system. we propose a joint optimization algorithm of recommendation and caching based on users' preference prediction with multiple base stations cooperative caching. To improve the caching efficiency, we adopt the Deep Crossing model to predict users' preferences. Under the constraints of cache capacity, recommendation quantity and bandwidth, we formulate an optimization problem to minimize the total transmission delay of the system. [ABSTRACT FROM AUTHOR]

The A64FX CPU is arguably the most powerful Arm‐based processor design to date. Although it is a traditional cache‐based multicore processor, its peak performance and memory bandwidth rival accelerator devices. A good understanding of its performance features is of paramount importance for developers who wish to leverage its full potential. We present an architectural analysis of the A64FX used in the Fujitsu FX1000 supercomputer at a level of detail that allows for the construction of Execution‐Cache‐Memory performance models for steady‐state loops. In the process we identify architectural peculiarities that point to viable generic optimization strategies. After validating the model using simple streaming loops we apply the insight gained to sparse matrix‐vector multiplication (SpMV) and the domain wall (DW) kernel from quantum chromodynamics. For SpMV we show why the compressed row storage (CRS) matrix storage format is not a good practical choice on this architecture and how the SELL‐C‐σ format can achieve bandwidth saturation. For the DW kernel we provide a cache‐reuse analysis and show how an appropriate choice of data layout for complex arrays can realize memory‐bandwidth saturation in this case as well. A comparison with state‐of‐the‐art high‐end Intel Cascade Lake AP and Nvidia V100 systems puts the capabilities of the A64FX into perspective. We also explore the potential for power optimizations using the tuning knobs provided by the Fugaku system, achieving energy savings of about 31% for SpMV and 18% for DW. [ABSTRACT FROM AUTHOR]

The aim of this article is to show that solvers for tridiagonal Toeplitz systems of linear equations can be efficiently implemented for a variety of modern GPU‐accelerated and multicore architectures using OpenACC. We consider two parallel algorithms for solving such systems with special assumptions about coefficient matrices. As the first algorithm, we propose a new, faster implementation of the divide and conquer method. The next algorithm is a new, vectorizable algorithm based on a recently introduced sequential method. We consider the use of both column‐wise and row‐wise storage formats for two‐dimensional arrays and show how to efficiently convert between these two formats using cache memory and improve the overall performance of our implementations. We also show how to tune the performance by predicting the best values of the methods' parameters. Numerical experiments performed on Intel CPUs and Nvidia GPUs show that our new implementations achieve relatively good performance and accuracy. [ABSTRACT FROM AUTHOR]

Models for virtual machines running on cloud computing systems. Modeling system behaviors of clouds is a grand challenge because the resource utilization in VMs is heterogeneous due to variability in workload conditions. We address this challenging issue by uniquely (1) objectifying the usage prediction of virtualized resources and (2) predicting the performance trends of programs running on clouds. At the heart of the modeling system, we pay particular attention to CPU cores, disk size, main memory space, and input data volume, which serve as important factors for the developed prediction module. We devise two resource‐utilization prediction algorithms driven by two distinctive sets of I/O and CPU intensive benchmarks, where one algorithm deals with execution time and the other one revolves around input data size. We investigate the correlation between CPU/disk utilization and VM live migrations. Our system aims at not only providing performance optimization for virtualized resources but also ensuring service level agreement (SLA) and Quality of Service (QoS). The model fits the curve quite well, thereby advocating for the efficiency of the algorithm. The case studies conducted in this project draw the comparisons between the performance of striped and monolithic disks as well as bringing forth the problem of cache coherence that causes hindrance to the experiment. We also deal with the cache‐coherence problem to improve the accuracy of our prediction algorithms [ABSTRACT FROM AUTHOR]

In general, it is accepted that gap formation significantly affects the placement of scatter‐hoarded seeds by small rodents, but the effects of different forest gap sizes on the seed‐eating and scatter‐hoarding behaviors of small rodents remain unclear. Thus, we examined the effects of a closed‐canopy forest, forest edge, and gaps with different sizes on the spatial dispersal of Quercus variabilis acorns and cache placement by small rodents using coded plastic tags in the Taihang Mountains, China. The seeds were removed rapidly, and there were significant differences in the seed‐eating and caching strategies between the stand types. We found that Q. variabilis acorns were usually eaten after being removed from the closed‐canopy forest and forest edges. By contrast, the Q. variabilis acorns in the forest gap stands were more likely to be scatter‐hoarded. The dispersal distances of Q. variabilis acorns were significantly longer in the forest gap plots compared with the closed canopy and forest edge plots. However, the proportion of scatter‐hoarded seeds did not increase significantly as the gap size increased. In small‐scale oak reforestation projects or research, creating small gaps to promote rodent‐mediated seed dispersal may effectively accelerate forest recovery and successional processes. [ABSTRACT FROM AUTHOR]

With the growth of mobile data traffic in wireless networks, caches are used to bring data closer to mobile users and to minimise the traffic load on macro base station (MBS). Storing data in caches on user terminals (UTs) and small base stations (SBSs) faces challenges with respect to the decision of cache contents. Here, a multi‐objective cache content strategy that aims to maximise the cache hit rate of SBSs in mobile edge networks (MENs) is proposed. The multi‐objective cache placement optimisation is formulated as a classification problem. Unlike previous work, mobility input attributes such as user locations, contact duration, communication ranges, contact probability between UTs and SBSs, etc. as well as content popularity and the correlation between these input attributes separating the decision space into two regions of cache and not cache are used. Stochastic gradient descent algorithm is used for the training of three supervised machine learning techniques: artificial neural network ANN, support vector machine (SVM), and logistic regression LR to define the hyperplane that separates the cache content decision space. Simulation results show that compared with the weighted‐sum approach, the SBSs cache hit rates increase on the average by 18.58%, 18.52%, and 18.2%, and the total energy consumption values decrease on the average by 33.49%, 53.19%, and 49.9% for ANN, SVM, and LR, respectively. [ABSTRACT FROM AUTHOR]