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Locally-active memristors blessed with an edge-of-chaos domain, which can be destabilized for generating action potentials, are natural candidates for emulating biological neurons. Pinpointing the edge-of-chaos domain, where neuromorphic behaviors may occur, is important for studying neuromorphic dynamics of memristors. This paper proposes a short-cut method for locating the edge-of-chaos domains in two kinds of generic memristors, and in several typical memristive 1-port circuits using only the Jacobian matrix in terms of their equations. Taking the Chua Corsage Memristor (CCM) and several CCM-based memristive 1-port circuits as examples, we verify the proposed new methods, and calculates their edge-of-chaos domains. Also, we carry out a complete classification of all the parameter regions of the CCM and several CCM-based memristive 1-port circuits, namely the locally-passive, locally-active but unstable, and edge-of-chaos domains, under both voltage and frequency control. Near the calculated edge-of-chaos domain, we uncover some new neuromorphic behaviors. To confirm the physical interpretations and predictions of the edge-of-chaos theorem, this paper presents an inexpensive electronic circuit realization of the complete set of equations defining the CCM using only off-the-shelf circuit components. When this poor-man's memristor is connected to various linear passive R, L, C circuits, and a battery, the resulting circuit can be tuned to generate action potentials, and a garden variety of neuromorphic phenomena, including chaos. But the highlight of this paper is reserved for the CCM itself where the world's first oscilloscope picture of a contiguous self-intersecting triple-branch DC V–I curve of the CCM is displayed in real time. [ABSTRACT FROM AUTHOR]

To meet the challenges of low-carbon power generation, distributed energy resources (DERs) such as solar and wind power generators are now widely integrated into the power grid. Because of the autonomous nature of DERs, ensuring properly regulated output voltages of the individual sources to the grid distribution system poses a technical challenge to grid operators. Stochastic, model-free voltage regulation methods such as deep reinforcement learning (DRL) have proven effective in the regulation of DER output voltages; however, deriving an optimal voltage control policy using DRL over a large state space has a large computational time complexity. In this paper, we illustrate a computationally efficient method for deriving an optimal voltage control policy using a parallelized DRL ensemble. Additionally, we illustrate the resiliency of the control ensemble when random noise is introduced by a cyber-adversary. [ABSTRACT FROM AUTHOR]

This paper presents an innovative cross-coupled differential drive rectifier for dual-band Radio frequency identification (RFID) tags. A self-compensating rectifier with enhanced power-conversion efficiency (PCE) at low and high RF power is proposed. The proposed rectifier utilizes a self-compensating circuit, the extra two cross-couple transistors, to increase the gate voltage of transistors to control the conduction of the rectifying transistors. In order to adapt high frequency (HF) and ultrahigh frequency (UHF) rectification, the matching circuit is designed with parasitic cancellation technology. Moreover, the cascading power management circuits are added to generate a stable output voltage. The multi-standard rectifier is designed and simulated in 0. 1 8 μ m CMOS process. The simulated result shows that the proposed three-stage rectifier achieves a PCE 74% (at 5 0 0 k Ω load) when receiving a 915 MHz signal with average power of − 2 5 dBm. Moreover, the maximum efficiency achieves 56% at HF 13.56 MHz, and the final output voltage can be stabilized at a specific voltage of 1.052 V. [ABSTRACT FROM AUTHOR]

Phase Locked Loop (PLL) is an on-chip clock generator for timing-centric electronic systems. Voltage Controlled Oscillator (VCO) is the key element for high-performance PLLs. A detailed qualitative explanation has been given to describe VCO operation. It is shown from simulation results that the variation of small signal transconductance ( g m ) is the main dominant source of frequency and gain ( K VCO ) variation in a VCO. In this work, simulation results for the conventional ring oscillator are presented which demonstrates ≈ 3 times variation in K VCO across Process Voltage Temperature (PVT) corners. Such huge sensitivity to PVT is undesirable for high bandwidth PLL design. To mitigate this sensitivity, a constant-gm bias circuit is proposed in this paper, with a detailed mathematical analysis. A prototype of 4-stage ring oscillator with center frequency of 5 GHz is developed in 65 nm TSMC CMOS technology, and post-layout simulation results are carried out. Results show that maximum K VCO variation of 28% and frequency variation of 17% at a given control voltage. Temperature sensitivity has been decreased from 19.3% to 7% using the proposed biasing technique. Proposed solution consumes 2.4 mW power from 1 V power supply. [ABSTRACT FROM AUTHOR]

This paper presents the design of a Chirp Spread Spectrum (CSS), ultra-wideband (UWB), pulse generator (PG) and device mismatch impact on its performance. The proposed CSS-PG is built using a differential ring oscillator (RO) controlled by a ramp generator, allowing varying linearly the pulse frequency with time over the CSS pulse duration. Device mismatches and random variations during integrated circuit manufacturing are the most critical imperfections in high precision differential UWB voltage controlled RO circuit. These mismatches lead to behavioral variations of the PG. The proposed CSS-UWB-PG is designed and analyzed using CMOS 0.18 μ m technology. The CSS-PG presents an output swing of 266 mV Vpp for 20 nsec and consumes 1.72 mW for a PRF of 10 MHz. The simulated PSD covers the UWB low band from 3 GHz to 5 GHz and complies with the FCC regulations. For V th mismatch, the simulation results show a maximum relative accuracy on oscillation frequency and phase noise of 3.43% and 6.9%, respectively. Monte Carlo and process simulation are performed to study the impact of the random parameter variation on this CSS-PG. Theses simulations show the robustness of the proposed design as the PG PSD is still inside the FCC-UWB mask and its bandwidth is greater than 500 MHz. [ABSTRACT FROM AUTHOR]

The realization of capacitance multiplier using the versatile active building block, namely voltage differencing differential difference amplifier (VDDDA) is presented in this paper. The realized capacitance multiplier is very simple consisting of one VDDDA, one MOS resistor ( R M) and one grounded capacitor which is attractive for integration. The multiplication factor (KC) of the realized circuit can be electronically controlled via the bias current ( I B) and control voltage ( V C) without the need of any matching condition of active and passive element. Moreover, the multiplication factor can be adjusted to be more or less than one. The performances of the presented capacitance multiplier are verified through Pspice simulation using CMOS VDDDA in 0.18 μ m TSMC technology with ± 0. 9 V power supplies. The multiplication factor is designed to be K C = 2 by choosing V C = 0. 8 5 V, I B = 5 0 μ A and C = 3 0 pF. The simulated multiplication factor is around 1.98. The simulated operational frequency range is around three decades (6.16 kHz–8.91 MHz). The performances of the proposed circuit are also verified by the experiment using VDDDA implemented from the commercial ICs, AD830 and LM13700 with ± 5 V power supplies. The experiment is conducted under the same multiplication factor ( K C = 2) as the simulation by choosing R M = 0. 2 7 k Ω (1% passive resistor), I B = 9 6. 2 μ A and C = 1 nF. The experimental multiplication factor is around 2.06. The experimental operational frequency range is around three decades (1 kHz–1.25 MHz). By adjusting the bias current from 17.67 μ A to 400 μ A, the experimental multiplication factor is controllable from 11.47 to 0.48. The percent deviation of the theoretical and experimental multiplication factor is lower than 5% when the value of bias current is greater than 39 μ A. These deviations stem from the effect of the parasitic capacitance and resistance in VDDDA. Moreover, the application example of the presented capacitance multiplier as the sinusoidal oscillator is presented. The performances of the presented oscillator verified via the experiment are well consistent with theoretical anticipation. [ABSTRACT FROM AUTHOR]

This paper presents a low-ripple and high-efficiency buck–boost DC–DC converter with delta-sigma modulator controller that converts 1.8 V to 1.2 V and 3.3 V. A current and voltage closed-loop controller has been designed to achieve better performance simultaneously such as lower settling-time, steady-state error and over shoot and under shoot. The converter is started in the current controller mode initially, when the output voltage approaches the desired value, the power stage is controlled with the voltage controller mode. PI compensator and a third-order delta-sigma modulator are utilized in the voltage mode. Also, the closed-loop stability of the designed converter has been analyzed with Lyapunov method using converter nonlinear model. This work has been simulated in MATLAB-SIMULINK environment. The performance results show that the maximum efficiency of the closed-loop DC–DC converter is 90% at 5 MHz switching frequency, and the output voltage ripple is 0.5% and 0.6% for the buck and boost modes, respectively. Also, the simulation results demonstrate the closed-loop stability of the converter in the presence of 10% load variation. [ABSTRACT FROM AUTHOR]

This paper proposes a control scheme that enhances both the power quality and voltage synchronization of the Self-Excited Induction Generator (SEIG) driven by a wind turbine supplying power to a remote region. A reactive power constraint of SEIG under load disturbances is balanced by a modified Second-Order Generalized Integrator (SOGI) with Fuzzy Logical Controller (FLC) controlled Quasi-Impedance (QZ) source network-based Static Compensator (STATCOM). The combination of STATCOM and the photovoltaic system, battery and flywheel enhances the active power potential of conventional STATCOMs by means of a hybridized STATCOM system. This system is intended for the optimum use of energy generated from renewable energy sources by physical energy storage systems such as flywheels and batteries. This tends to compensate for the deviation of both active and reactive power and hence increase in active power, reliability and system stability. For analyzing device behavior, the dynamic hybrid STATCOM model with FLC dependent ESOGI has been developed. In standalone operation, simulated and experimental findings indicate the increased capability and system efficiency under variable load conditions. [ABSTRACT FROM AUTHOR]

The flight control system is the integrated command center and core component of the UAV system. Aiming at the problems of poor accuracy and low efficiency in the field measurement of flight control system parameters, combined with the configuration of the flight attitude sensor-vertical gyroscope, hardware-in-the-loop simulation technology, and integrated automatic test methods are adopted. The hardware-in-the-loop simulation test platform for the UAV flight control system composed of a low-cost, high-precision miniaturized UAV attitude calibration platform and a control piston deflection angle test device is designed. The main controller replaces the ground master control station of the UAV and directly sends remote control commands to the aircraft. By changing the attitude of the aircraft, and measuring the voltage of the control signal, the feedback signal, and the rudder angle, the comprehensive performance test of the parameters of the flight control system is realized. The performance test of the platform shows that the platform can meet the test requirements of angular position, system voltage, and control piston deflection angle. [ABSTRACT FROM AUTHOR]

This work describes a new design approach for a four-stage ring Voltage-Controlled Oscillator (VCO) for Orthogonal Frequency Division Multiplexing (OFDM) systems, which is ideal for low-phase noise and low-power applications. The phase noise of the proposed ring VCO has been improved by limiting the delay cell's output current to a relatively narrow portion of the output waveform, and the complementary nature of the delay cell prevents the power from increasing substantially. The proposed VCO is designed and simulated in GPDK 90 nm CMOS technology using Cadence Virtuoso under 1.0 V power supply. A tuning frequency range of 112–362 MHz is obtained with control voltage ranges 0.0–1.0 V. The proposed ring VCO consumes 1.07 mW of power. At a 1 MHz offset frequency, phase noise reduction is achieved to − 1 0 9. 3 6 dBc/Hz. The proposed design is also validated by the Process–Voltage–Temperature (PVT) analysis. The proposed VCO has a Figure of Merit (FOM) of − 1 6 0. 2 4 dBc/Hz and acquires a total area of 0.00085 mm2. [ABSTRACT FROM AUTHOR]