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In this study, we propose the use of artificial synaptic transistors with coplanar-gate structures fabricated on paper substrates comprising biocompatible and low-cost potato-starch electrolyte and indium–gallium–zinc oxide (IGZO) channels. The electrical double layer (EDL) gating effect of potato-starch electrolytes enabled the emulation of biological synaptic plasticity. Frequency dependence measurements of capacitance using a metal-insulator-metal capacitor configuration showed a 1.27 μF/cm2 at a frequency of 10 Hz. Therefore, strong capacitive coupling was confirmed within the potato-starch electrolyte/IGZO channel interface owing to EDL formation because of internal proton migration. An electrical characteristics evaluation of the potato-starch EDL transistors through transfer and output curve resulted in counterclockwise hysteresis caused by proton migration in the electrolyte; the hysteresis window linearly increased with maximum gate voltage. A synaptic functionality evaluation with single-spike excitatory post-synaptic current (EPSC), paired-pulse facilitation (PPF), and multi-spike EPSC resulted in mimicking short-term synaptic plasticity and signal transmission in the biological neural network. Further, channel conductance modulation by repetitive presynaptic stimuli, comprising potentiation and depression pulses, enabled stable modulation of synaptic weights, thereby validating the long-term plasticity. Finally, recognition simulations on the Modified National Institute of Standards and Technology (MNIST) handwritten digit database yielded a 92% recognition rate, thereby demonstrating the applicability of the proposed synaptic device to the neuromorphic system. [ABSTRACT FROM AUTHOR]

The gallium-nitride (GaN) high electron-mobility transistor (HEMT) technology has emerged as an attractive candidate for high-frequency, high-power, and high-temperature applications due to the unique physical characteristics of the GaN material. Over the years, much effort has been spent on measurement-based modeling since accurate models are essential for allowing the use of this advanced transistor technology at its best. The present analysis is focused on the modeling of the scattering (S-) parameter measurements for a 0.25 μm GaN HEMT on silicon carbide (SiC) substrate at extreme operating conditions: a large gate width (i.e., the transistor is based on an interdigitated layout consisting of ten fingers, each with a length of 150 μm, resulting in a total gate periphery of 1.5 mm), a high ambient temperature (i.e., from 35 °C up to 200 °C with a step of 55 °C), a high dissipated power (i.e., 5.1 W at 35 °C), and a high frequency in the millimeter-wave range (i.e., from 200 MHz up to 65 GHz with a step of 200 MHz). Three different modeling approaches are investigated: the equivalent-circuit model, artificial neural networks (ANNs), and gated recurrent units (GRUs). As is shown, each modeling approach has its pros and cons that need to be considered, depending on the target performance and their specifications. This implies that an appropriate selection of the transistor modeling approach should be based on discerning and prioritizing the key features that are indeed the most important for a given application. [ABSTRACT FROM AUTHOR]

The choice of gate metal technology for junctionless transistors needs to have diverse characteristics as metals have distinct work functions and hence, they show incompatibility while tailoring threshold of the device. In such a scenario, bimetallic stacked gate can be a promising candidate to present wide range of tunable work functions required for nanoregime junctionless transistors. This paper explores the electronic phenomena occurring at metal-metal interface and the impact of Platinum (Pt)/Titanium (Ti) bimetallic stacked gate-based work function tunability on the RF and thermal performances of p-type window-based Silicon on Insulator Junctionless Transistor (SOI JLT) using numerical simulator SILVACO ATLAS. The parameters considered for performance evaluation are ON-state current (ION), OFF-state current (IOFF ), ION/IOFF ratio, transconductance (gm), cutoff frequency (fT ), Transconductance Frequency Product (TFP), Intrinsic Gate Delay (IGD), intrinsic gain (AV ), and Global Device Temperature (GDT). The gm, fT, TFP, AV and GDT improve for modified over conventional in the ON state at higher work function, while IGD improves at lower work function. The improvements of 11.7 % and 2.21 % are obtained in maximum gm and fT, respectively, for modified transistor over conventional. The findings suggest that bimetallic stacked gate modified SOIJLT is a better option than conventional for low-power RF application. [ABSTRACT FROM AUTHOR]

The performance improvement of CMOS computer fails to meet the enormous data processing requirement of artificial intelligence progressively. The memristive neural network is one of the most promising circuit hardwares to make a breakthrough. This paper proposes a novel memristive synaptic circuit that is composed of four MOS transistors and one memristor (4T1M). The 4T1M synaptic circuit provides flexible control strategies to change memristance or respond to the input signal. Applying the 4T1M synaptic circuit as the cell of memristive crossbar array, based on the structure and algorithm of the back-propagation (BP) neural network, this paper proposes circuit design of the memristive crossbar-based BP neural network. By reusing the 4T1M memristive crossbar array, the computations in the forward-propagation process and back-propagation process of BP neural network are accomplished on the memristive crossbar-based circuit to accelerate the computing speed. The 4T1M memristive crossbar array can change all the cells' memristance at a time, accordingly, the memristive crossbar-based BP neural network can realize synchronous memristance adjustment. The proposed memristive crossbar-based BP neural network is then evaluated through experiments involving XOR logic operation, iris classification, and MNIST handwritten digit recognition. The experimental results present fewer iterations or higher classification accuracies. Further, the comprehensive comparisons with the existing memristive BP neural networks highlight the advantages of the proposed memristive crossbar-based BP neural network, which achieves the fastest memristance adjustment speed using relatively few components. [ABSTRACT FROM AUTHOR]

The history of ternary adders goes back to more than 6 decades ago. Since then, a multitude of ternary full adders (TFAs) have been presented in the literature. This article conducts a review of TFAs so that one can be familiar with the utilised design methodologies and their prevalence. Moreover, despite numerous TFAs, almost none of them are in their simplest form. A large number of transistors could have been eliminated by considering a partial TFA instead of a complete one. According to our investigation, only 28.6% of the previous designs are partial TFAs. Also, they could have been simplified even further by assuming a partial TFA with an output carry voltage of 0 V or VDD. This way, in a single‐VDD design, voltage division inside the Carry generator part would have been eliminated and less power dissipated. As far as we have searched, there are only three partial TFAs with this favourable condition in the literature. Additionally, most of the simulation setups in the previous articles are not realistic enough. Therefore, the simulation results reported in these papers are neither comparable nor entirely valid. Therefore, the authors got motivated to conduct a survey, elaborate on this issue, and enhance some of the previous designs. Among 84 papers, 10 different TFAs (from 11 papers) are selected, simplified, and simulated in this article. Simulation results by HSPICE and 32 nm carbon nanotube FET technology reveal that the simplified partial TFAs outperform their original versions in terms of delay, power, and transistor count. [ABSTRACT FROM AUTHOR]

For purposes of technological processes, the power supply is needed. Within thermically processes, entering features are defined, such as production speed for a specific range of products. All mentioned actions demand calculation of power needed for power supply. The type of voltage is determined. The application of alternating and direct voltage is possible. For specific power and type of power supply, a converter is designed. Welding demands alternating voltage at a particular frequency. Such power supplies are realized through transistor inverters which will work at a specific frequency. This paper analyses existing solutions. The main objective of this paper is the representation of the original calculation with more accurate values of inverter components. [ABSTRACT FROM AUTHOR]

Transistor random threshold voltage variations due to process fluctuations seriously affects the stability of Static Random Access Memory (SRAM). In this paper, a SRAM bit transistors threshold voltage $({Vth})$ deviation monitoring scheme and system is proposed. This scheme ingeniously achieves on-chip measurement of all transistors threshold voltages without altering compact SRAM bit array layout. Control signal strategies and Transistor ${Vth}$ Determination Circuit (TVDC) for different types of Devices Under Test (DUTs) have been proposed. The system is implemented using a 65 nm CMOS process with a core area of 0.01875mm2. Through Monte Carlo analysis, the Weighted Average (WA) difference of the proposed scheme and the direct measurement method is not more than 10mV, and the Root Mean Square Error (RMSE) difference is not more than 3mV. This system can also effectively detect the cell position of the transistor threshold voltage mismatch simulated by modifying the substrate voltage. For SRAM arrays of different scales, the method proposed in this paper has area efficiency and flexible reconfigurability. [ABSTRACT FROM AUTHOR]

Metal–oxide–semiconductor field-effect transistors (MOSFETs) have proven to be effective devices for rectifying electromagnetic radiation at extremely high frequencies, approximately 1 THz. This paper presents a new interpretation of the THz rectification process in the structure of an MOS transistor. The rectification depends on the nonlinear effect of the carrier dynamics. The paper shows that the so-called self-mixing effect occurs within the interface region between the source and the channel. The basic tool used numerical TCAD simulations, which offer a direct interpretation of different aspects of this interaction. The complex, 2D effect is examined in terms of its basic aspects by comparing the MOS structure with a simplified case study structure. We demonstrate that a contribution to the output-rectified voltage detectable at the drain arises from the charging of the drain well capacitance due to the diffusion of excess electrons from the self-mixing interaction occurring at the source barrier. In addition, the paper provides a quantitative description of the rectification process through the definition of the output equivalent circuit, offering a new perspective for the design of detection systems. [ABSTRACT FROM AUTHOR]

Although Moore's Law reaches its limits, it has never applied to analog and RF circuits. For example, due to the short channel effect (SCE), drain-induced barrier lowering (DIBL), and sub-threshold slope (SS)..., longer transistors are required to implement analog cells. From 22 nm CMOS technology and beyond, for reasons of variability, the channel of the transistors has no longer been doped. Two technologies then emerged: FinFET transistors for digital applications and UTBB FDSOI transistors, suitable for analog and mixed applications. In a previous paper, a new topology was proposed utilizing some advantages of the FDSOI technology. Thanks to this technology, a novel cross-coupled back-gate (BG) technique was implemented to improve analog and mixed signal cells in order to reduce the surface of the integrated circuit. This technique was applied to a current mirror to reduce the small channel effect and to provide high-output impedance. It was demonstrated that it is possible to overcompensate the SCE and DIBL effects and to create a negative output resistor. This paper presents a new LC tank oscillator based on this current mirror functioning as a negative resistor. [ABSTRACT FROM AUTHOR]

Nonvolatile computing have been shown to be effective in the face of the sudden power outage for wireless sensor networks, Internet-of-Things applications, data converters, and emerging energy-harvesting circuits. It also plays a significant role in power-gating to minimize the leakage power for improving the energy efficiency. However, using on-chip backup module for D flip--flop has a bottleneck, and result in an increase in total power consumption, occupied area, and reduced calculation speed. Furthermore, the backup module needs external control signals, which increases the complexity of the circuit. This paper proposes a novel nonvolatile flip-flop with simultaneous data backup capability, which uses NCFET ferroelectric transistor to fundamentally advance the non-volatile computing paradigm. Proposed NVFF exhibits 0.8% faster and 5.0% smaller energy than previous works, while uniquely providing Radiation- Hardened feature. [ABSTRACT FROM AUTHOR]

In this paper, we study the drift behavior of organic electrochemical transistor (OECT) biosensors in a phosphate-buffered saline (PBS) buffer solution and human serum. Theoretical and experimental methods are illustrated in this paper to understand the origin of the drift phenomenon and the mechanism of ion diffusion in the sensing layer. The drift phenomenon is explained using a first-order kinetic model of ion adsorption into the gate material and shows very good agreement with experimental data on drift in OECTs. We show that the temporal current drift can be largely mitigated using a dual-gate OECT architecture and that dual-gate-based biosensors can increase the accuracy and sensitivity of immuno-biosensors compared to a standard single-gate design. Specific binding can be detected at a relatively low limit of detection, even in human serum. [ABSTRACT FROM AUTHOR]

This paper discusses the potential to decrease the response time of a DC–DC converter through the substitution of Si transistors with GaN transistors and the implementation of digital control techniques. This paper introduces an improved methodology for designing digital voltage controllers by analyzing discretization delays and subsequently implementing a modified analog controller design method. The theoretical analysis was verified using an experimental prototype of a 100 W 48 V to 12 V GaN-based DC–DC converter. A digital controller that allows a 50 kHz bandwidth to be achieved based on an STM32G4 microcontroller was developed, and the design of the controller is discussed in detail. The converter was operated with a 500 kHz switching frequency using a 6 µH inductor and a 20 µF ceramic capacitor output filter. Although the digital control introduced a 1.2 µs delay, a converter response time equal to 40 µs was achieved. Simulation models were created and their results were verified via comparisons with experimental results obtained with an AP310 frequency response analyzer. [ABSTRACT FROM AUTHOR]

For insulated gate bipolar transistor (IGBT) modules using wire bonding as the interconnection method, the main failure mechanism is cracking of the bonded interface. Studying the mechanical properties of the bonded interface is crucial for assessing the reliability of IGBT modules. In this paper, first, shear tests are conducted on the bonded interface to test the bonded interface's strength. Then, finite element–cohesive zone modeling (FE-CZM) is established to describe the mechanical behavior of the bonded interface. A novel machine learning (ML) architecture integrating a convolutional neural network (CNN) and a long short-term memory (LSTM) network is used to identify the shape and parameters of the traction separation law (TSL) of the FE-CZM model accurately and efficiently. The CNN-LSTM architecture not only has excellent feature extraction and sequence-data-processing abilities but can also effectively address the long-term dependency problem. A total of 1800 sets of datasets are obtained based on numerical computations, and the CNN-LSTM architecture is trained with load–displacement (F–δ) curves as input parameters and TSL shapes and parameters as output parameters. The results show that the error rate of the model for TSL shape prediction is only 0.186%. The performance metric's mean absolute percentage error (MAPE) is less than 3.5044% for all the predictions of the TSL parameters. Compared with separate CNN and LSTM architectures, the proposed CNN-LSTM-architecture approach exhibits obvious advantages in recognizing TSL shapes and parameters. A combination of the FE-CZM and ML methods in this paper provides a promising and effective solution for identifying the mechanical parameters of the bonded interfaces of IGBT modules. [ABSTRACT FROM AUTHOR]

This paper presents a 9-bit differential, minimum-powered, successive approximation register (SAR) ADC intended for implantable devices or sensors. Such applications demand nanowatt-range power consumption, which is achieved by designing the SAR ADC with a proposed bootstrap switch, bespoke split-capacitive DAC, customized comparator and a modified dynamic bit-slice unit for SAR logic. The linearity of the ADC is improved by introducing a bootstrap switch with a low clock feedthrough and threshold voltage variations along with the disseminated attenuation capacitor in the split-capacitive DAC. The dynamic comparator is customized to be simple in terms of the number of transistors to gain the advantage of low power and is also designed to have a low dynamic offset voltage. The stacking concept is embedded in the bit-slice unit of SAR logic to achieve reduced leakage power. This paper is concerned with how to contribute to low power consumption in all the aspects possible related to the implementation of the SAR ADC. With a 0.4 V supply and at 2 kS/s, the proposed ADC achieves an SNDR of 52.52 dB and a power consumption of 5.29 nW, resulting in a figure of merit (FOM) of 7.66 fJ/conversion-step. [ABSTRACT FROM AUTHOR]

Carbon nanotube field‐effect transistors (CNT FETs) have been demonstrated to exhibit high performance only through low‐temperature fabrication process and require a low thermal budget to construct monolithic three‐dimensional (M3D) integrated circuits (ICs), which have been considered a promising technology to meet the demands of high‐bandwidth computing and fully functional integration. However, the lack of high‐quality CNT materials at the upper layer and a low‐parasitic interlayer dielectric (ILD) makes the reported M3D CNT FETs and ICs unable to provide the predicted high performance. In this work, we demonstrate a multilayer stackable process for M3D integration of high‐performance aligned carbon nanotube (A‐CNT) transistors and ICs. A low‐κ (~3) interlayer SiO2 layer is prepared from spin‐on‐glass (SOG) through processes with a highest temperature of 220°C, presenting low parasitic capacitance between two transistor layers and excellent planarization to offer an ideal surface for the A‐CNT and device fabrication process. A high‐quality A‐CNT film with a carrier mobility of 650 cm2 V–1 s–1 is prepared on the ILD layer through a clean transfer process, enabling the upper CNT FETs fabricated with a low‐temperature process to exhibit high on‐state current (1 mA μm–1) and peak transconductance (0.98 mS μm–1). The bottom A‐CNT FETs maintain pristine high performance after undergoing the ILD growth and upper FET fabrication. As a result, 5‐stage ring oscillators utilizing the M3D architecture show a gate propagation delay of 17 ps and an active region of approximately 100 μm2, representing the fastest and the most compact M3D ICs to date. [ABSTRACT FROM AUTHOR]

Floating-gate transistor lies at the heart of many aspects of semiconductor applications such as neural networks, analog mixed-signal, neuromorphic computing, and especially in nonvolatile memories. The purpose of this paper was to design a high-performance nanocrystal floating-gate transistor in terms of a large memory window, low power, and extraordinary erasing speeds. Besides, the transistor achieves a thin thickness of the tunnel gate oxide layer. In order to obtain the high-performance design, this work proposed a set of structure parameters for the device such as the tunnel oxide layer thickness, Interpoly Dielectric (IPD), dot dimension, and dot spacing. Besides, this work was successful in the virtual fabrication process and methodology to fabricate and characterize the 65 nm nanocrystal floating-gate transistor. Regarding the results, while the fabrication process solves the limitation of the tunnel oxide layer thickness with the small value of 6 nm, the performance of the transistor has been significantly improved, such as 2.8 V of the memory window with the supply voltage of ±6 V at the control gate. In addition, the operation speeds are compatible, especially the rapid erasing speeds of 2.03 μs, 28.6 ns, and 1.6 ns when the low control gate voltages are ±9 V, ±12 V, and ±15 V, respectively. [ABSTRACT FROM AUTHOR]

This paper presented a flux controlled memristor using the most versatile analog block, a single Operational Amplifier (Op-Amp), an N-channel metal–oxide–semiconductor field-effect transistor (MOSFET), and four passive elements. The following benefits are offered by the suggested memristor design: (1) a lesser number of active and passive elements; (2) floating nature of the circuit; (3) wide-operating frequency range (200 Hz–20 kHz); and (4) simple and versatile design. The performance evaluation through simulation of the proposed memristor model including post-layout simulation of silicon components (Op-Amp and NMOS transistor (M )) is verified with Cadence Virtuoso tool using standard CMOS 90 nm technology. In addition, the application of the proposed memristor in the field of analog and digital are also shown in the paper. Furthermore, the proposed circuit verification is also carried out experimentally using off-the-shelf components (IC LM741 and 2N6659) along with passive components. [ABSTRACT FROM AUTHOR]

A new power receiving unit (PRU) is proposed in this paper for resonant wireless power transfer (WPT), which is characterized by the capability of attracting high power from the power transmitting unit (PTU). The resonant WPT is designed for delivering the electrical power to the PRU attached on an electrical vehicle (EV) chassis 50 cm away from a PTU installed on the ground. The proposed PRU uses only the passive elements such as inductors, diodes, and capacitors, which need no initial power from the EV. It is then applicable for charging a battery to several hundred volts for even a first-time charging battery. For a resonant WPT at a switching frequency of 4 MHz, the proposed PRU behaves as a negative impedance converter (NIC) itself in the subharmonics of 4 MHz. The NIC effect plus the subharmonic oscillation causes an instability current charging the battery connected to the PRU. In this paper, we simulated the PRU and performed the experiment. The experiment demonstrated a battery charging of 150 W from 50 cm away using three D-mode GaN HEMT transistors via the instability current ramp. The power transfer efficiency (PTE) improved as the power delivered to the load (PDL) increased. The peak PTE was 65% in the present findings. The simulation analysis showed that the circuit allowed itself be used to much higher power transfer when it is implemented with more GaN HEMT transistors connected in parallel. The theoretical derivation of the PRU circuit is also used to support both the experimental and simulation results. [ABSTRACT FROM AUTHOR]

For high-frequency switching applications, silicon carbide (SiC) devices are more suitable than silicon-based devices, which is conducive to improving the efficiency and power density of power electronic equipment. However, as the switching frequency increases, the influence of parasitic parameters on the switching characteristics of devices becomes increasingly apparent. When SiC metal-oxide-semiconductor field-effect transistors (MOSFETs) are applied in bridge circuits, the crosstalk problem easily occurs with the complementary conduction of upper and lower transistors, which seriously limits the promotion of SiC MOSFETs. However, the existing crosstalk suppression drive circuit tends to increase the switching loss, switching delay, and control complexity; therefore, a gate drive with crosstalk suppression capability is proposed. In this paper, the gate drive has two features: a negative voltage to shut down the SiC MOSFET; and an adjustment of the gate-source equivalent impedance. To accomplish this goal, the mechanism of crosstalk voltage generation is analyzed. Furthermore, the operation principle of the gate drive is analyzed, and the parameters of the gate drive are designed. Eventually, the proposed gate drive is verified by an LTspice simulation and experimental platform. The results prove that the gate drive can suppress the crosstalk voltage without affecting the switching speed. [ABSTRACT FROM AUTHOR]

With the continuous expansion of pixel arrays in digital microfluidics (DMF) chips, precise droplet control has emerged as a critical issue requiring detailed consideration. This paper proposes a novel capacitance-based droplet sensing system for thin-film transistor DMF. The proposed circuit features a distinctive inner and outer dual-pixel electrode structure, integrating droplet driving and sensing functionalities. Discharge occurs exclusively at the inner electrode during droplet sensing, effectively addressing droplet perturbation in existing sensing circuits. The circuit employs a novel fan-shaped structure of thin-film transistors. Simulation results show that it can provide a 48 V pixel voltage and demonstrate a sensing voltage difference of over 10 V between deionized water and silicone oil, illustrating its proficiency in droplet driving and accurate sensing. The stability of threshold voltage drift and temperature was also verified for the circuit. The design is tailored for integration into active matrix electrowetting-on-dielectric (AM-EWOD) chips, offering a novel approach to achieve precise closed-loop control of droplets. [ABSTRACT FROM AUTHOR]

In this paper, a CGH40010F GaN-based wideband RF rectifier with high rectification efficiency is presented. A novel continuous class-EFJ-mode rectifier is constructed by combining a continuous class-J-mode rectifier and class-EF-mode rectifier under specific impedance conditions. This novel continuous class-EFJ-mode rectifier has high rectification efficiency and wide bandwidth at the same time. For validation, a wideband high-efficiency class-EFJ-mode rectifier functioning within the 2.0–3.0 GHz range is designed, fabricated, and measured. The measurements indicate that, with an input power of 40 dBm and a resistance of 72 Ω on the dc load, the implemented rectifier sustains a rectification efficiency exceeding 60% across its entire operational frequency band. Meanwhile, the dimensions of the circuits are only 3 cm × 3.1 cm. [ABSTRACT FROM AUTHOR]

Many advanced technologies have been employed in high-performance active matrix displays, including liquid crystal displays, organic light-emitting diode displays, and micro-light-emitting diode displays. On the other side, there exists a strong demand for cost reduction, and it is one of the low-cost schemes for integrating the driver circuit in a panel based on thin-film transistor technologies. This paper reviews the overall concept, operation principles, and various circuit approaches in shift registers for scanning pulse generation. In addition, it deals with the implementation of additional functionalities in gate drivers to support pixel compensation, multi-line driving, in-cell capacitive touch screen, pixel sensing, and adaptive scanning region control. [ABSTRACT FROM AUTHOR]

This paper presents an inverter-based active feedback transimpedance amplifier (IAF-TIA), in which an active feedback is applied to a voltage-mode inverter-based TIA, and therefore, the controlled positive regeneration process enables the proposed IAF-TIA to achieve the limiting operations for input currents greater than 100 μApp. However, the active inverter feedback mechanism might be prone to instability, hence mandating a very careful optimization of the loop gain. For this purpose, a diode-connected NMOS transistor is employed as a switch in the feedback path with its gate connected to the input, which helps not only to mitigate the corresponding issue but also to accommodate large input currents up to 1.5 mApp. The proposed IAF-TIA implemented in a standard 180 nm CMOS process demonstrates a 70.5 dBΩ transimpedance gain, 1.21 GHz bandwidth, 4.3   pA / Hz noise current spectral density, 63.5 dB input dynamic range, and 23.6 mW power dissipation from a single 1.8 V supply. The chip core occupies an area of 180 × 50 μm2, including an on-chip P+/N-well/Deep N-well avalanche photodiode as an optical detector. [ABSTRACT FROM AUTHOR]

Highlights: Transient response plays a crucial role as a performance indicator for organic electrochemical transistors (OECTs), particularly in their application in high-speed logic circuits and neuromorphic computing systems. This review presents a systematic overview on the fundamental principles underlying OECT transient responses, emphasizing the essential roles of transient electron and ion dynamics, as well as structural evolution, in both volatile and non-volatile behaviors. We also discuss the materials, morphology, device structure strategies on optimizing transient responses. The rapid development of organic electrochemical transistors (OECTs) has ushered in a new era in organic electronics, distinguishing itself through its application in a variety of domains, from high-speed logic circuits to sensitive biosensors, and neuromorphic devices like artificial synapses and organic electrochemical random-access memories. Despite recent strides in enhancing OECT performance, driven by the demand for superior transient response capabilities, a comprehensive understanding of the complex interplay between charge and ion transport, alongside electron–ion interactions, as well as the optimization strategies, remains elusive. This review aims to bridge this gap by providing a systematic overview on the fundamental working principles of OECT transient responses, emphasizing advancements in device physics and optimization approaches. We review the critical aspect of transient ion dynamics in both volatile and non-volatile applications, as well as the impact of materials, morphology, device structure strategies on optimizing transient responses. This paper not only offers a detailed overview of the current state of the art, but also identifies promising avenues for future research, aiming to drive future performance advancements in diversified applications. [ABSTRACT FROM AUTHOR]

This paper derives theoretical results for adaptive bias in Doherty amplifiers and presents the design and measurements of an integrated adaptive bias circuit tailored for high peak-to-average high bandwidth signals. Fundamental equations for output power, impedance, and efficiency of the complete Doherty amplifier are derived. Even with ideal transistor models, the Doherty amplifier is fundamentally nonlinear due to saturation of the main amplifier and class-C nonlinearity of the auxiliary. Increasing the transconductance of the auxiliary amplifier mitigates the distortion. Adaptive bias offers the possibility to control the output current characteristic of the auxiliary amplifier. This means that adaptive bias linearises and mitigates the need for an oversized auxiliary amplifier. Both methods, transconductance scaling and adaptive bias, are analysed and compared as well as having a band limited adaptive bias signal. The design of a multiple GHz bandwidth adaptive bias circuit is presented. To verify the circuit design and the theoretical predictions, an mmW Doherty amplifier in 22 nm CMOS-FD-SOI, utilizing the presented adaptive bias circuit, is measured and compared with and without adaptive bias. Comparison is conducted both using continuous-wave and modulated high bandwidth signals. Measured results confirm the predicted improvements by the adaptive bias as derived by the theoretical analysis. [ABSTRACT FROM AUTHOR]

The objective of this paper is to evaluate the effect of a nanostructured C-Pd film deposited in the gate area of a field-effect transistor (FET) with a carbon–palladium composite gate (C-Pd/FET) on the hydrogen-sensing properties of the transistor. The method of preparing a field-effect transistor (FET) with a C-Pd film deposited as a gate and the properties of such a transistor and the film itself are presented. The C-Pd film deposited by PVD method on the gate area serves as an active layer. The PVD process was carried out in a dynamic vacuum of 10−5 mbar from two separated sources—one containing fullerenes (C60) and the other containing palladium acetate. Scanning electron microscopy (SEM), energy-dispersive X-ray spectroscopy (EDS, EDX) and electrical property studies were used to the characterize C-Pd films and FET/C-Pd structures. SEM observations revealed the topography of C-Pd films and FET/C-Pd transistors. EDS/EDX microanalysis was applied to visualize the arrangement of elements on the studied surfaces. The changes in electrical properties (resistance and relative resistance) due to the presence of hydrogen were studied in a designed and computerized experimental set-up. The enhanced properties of the FET/C-Pd transistor are demonstrated in terms of hydrogen detection. [ABSTRACT FROM AUTHOR]

Metal-oxide (MOx) thin-film transistors (TFTs) require complex circuit structures to cope with their depletion mode characteristics, making them applicable only to large-area active matrix (AM) displays despite their low manufacturing cost and decent performance. In this paper, we report a simple MOx 10T-2C scan driver circuit that overcomes the depletion mode characteristics using a series-connected two transistor (STT) configuration and clock signals with two kinds of low-voltage levels. The proposed circuit has a wide operating range of TFT characteristics, i.e., −2.8 V ≤ VTH ≤ +3.0 V. Through the measurement results of the manufactured sample, it was confirmed that the performance and area of our circuit are suitable for high-resolution mobile displays. [ABSTRACT FROM AUTHOR]

In this paper, we demonstrate a comprehensive study of NF3-based selective etching processes for inner spacer formation and for channel release, enabling stacked horizontal gate-all-around Si nanosheet transistor architectures. A cyclic etching process consisting of an oxidation treatment step and an etching step is proposed and used for SiGe selective etching. The cyclic etching process exhibits a slower etching rate and higher etching selectivity compared to the direct etching process. The cycle etching process consisting of Recipe 1, which has a SiGe etching rate of 0.98 nm/cycle, is used for the cavity etch. The process achieved good interlayer uniformity of cavity depth (cavity depth ≤ 5 ± 0.3 nm), while also obtaining a near-ideal rectangular SiGe etch front shape (inner spacer shape = 0.84) and little Si loss (0.44 nm@ each side). The cycle etching process consisting of Recipe 4 with extremely high etching selectivity is used for channel release. The process realizes the channel release of nanosheets with a multi-width from 30 nm to 80 nm with little Si loss. In addition, a selective isotropic etching process using NF3/O2/Ar gas mixture is used to etch back the SiN film. The impact of the O2/NF3 ratio on the etching selectivity of SiN to Si and the surface roughness of SiN after etching is investigated. With the introduction of O2 into NF3/Ar discharge, the selectivity increases sharply, but when the ratio of O2/NF3 is up to 1.0, the selectivity tends to a constant value and the surface roughness of SiN increases rapidly. The optimal parameter is O2/NF3 = 0.5, resulting in a selectivity of 5.4 and a roughness of 0.19 nm. [ABSTRACT FROM AUTHOR]

Silicon qubits based on specific SOI FinFETs and nanowire (NW) transistors have demonstrated promising quantum properties and the potential application of advanced Si CMOS devices for future quantum computing. In this paper, for the first time, the quantum transport characteristics for the next-generation transistor structure of a stack nanosheet (NS) FET and the innovative structure of a fishbone FET are explored. Clear structures are observed by TEM, and their low-temperature characteristics are also measured down to 6 K. Consistent with theoretical predictions, greatly enhanced switching behavior characterized by the reduction of off-state leakage current by one order of magnitude at 6 K and a linear decrease in the threshold voltage with decreasing temperature is observed. A quantum ballistic transport, particularly notable at shorter gate lengths and lower temperatures, is also observed, as well as an additional bias of about 1.3 mV at zero bias due to the asymmetric barrier. Additionally, fishbone FETs, produced by the incomplete nanosheet release in NSFETs, exhibit similar electrical characteristics but with degraded quantum transport due to additional SiGe channels. These can be improved by adjusting the ratio of the channel cross-sectional areas to match the dielectric constants. [ABSTRACT FROM AUTHOR]

A novel high-speed and process-compatible carrier-stored trench-gate bipolar transistor (CSTBT) combined with split-gate technology is proposed in this paper. The device features a split polysilicon electrode in the trench, where the left portion is equipotential with the cathode. This design mitigates the impact of the anode on the trench gate, resulting in a reduction in the gate-collector capacitance (CGC) to improve the dynamic characteristics. On the left side of the device cell, the P-layer, the carrier-stored (CS) layer and the P-body are formed from the bottom up by ion implantation and annealing. The P-layer beneath the trench bottom can decrease the electric field at the bottom of the trench, thereby improving breakdown voltage (BV) performance. Simultaneously, the highly doped CS layer strengthens the hole-accumulation effect at the cathode. Moreover, the PNP doping layers on the left form a self-biased pMOS. In a short-circuit state, the self-biased pMOS turns on at a certain collector voltage, causing the potential of the CS-layer to be clamped by the hole channel. Consequently, the short-circuit current no longer increases with the collector voltage. The simulation results reveal significant improvements in comparison with the conventional CSTBT under the same on-state voltage (1.48 V for 100 A/cm2). Specifically, the turn-off time (toff) and turn-off loss (Eoff) are reduced by 38.4% and 41.8%, respectively. The short-circuit current is decreased by 50%, while the short-circuit time of the device is increased by 2.46 times. [ABSTRACT FROM AUTHOR]

Reconfigurable FETs (RFETs) are widely recognized as a promising way to overcome conventional CMOS architectures. This paper presents novel addition circuit intentionally designed to exploit the ability of RFETs to operate efficiently on demand as n- or p-type FETs. First, a novel Full Adder (FA) is proposed and characterized. A comparison with other designs shows that the proposed FA achieves a worst-case delay and a dynamic power consumption of up to 43.5% and 79% lower. As a drawback, in terms of the estimated area, it is up to 32% larger than the competitors. Then, the new FA is used to implement Ripple-Carry Adders (RCAs). A 32-bit adder designed as proposed herein reaches an energy–delay product (EDP) ~25.7× and ~141× lower than its CMOS and the RFET-based counterparts. [ABSTRACT FROM AUTHOR]

In this paper, a low-power Injection-Locked Clock and Data Recovery (ILCDR) using a 28 nm Ultra-Thin Body and Box-Fully Depleted Silicon On Insulator (UTBB-FDSOI) technology is presented. The back-gate auto-biasing of UTBB-FDSOI transistors enables the creation of a Quadrature Ring Oscillator (QRO) reducing both size and power consumption compared to an LC tank oscillator. By injecting a digital signal into this circuit, we realize an Injection-Locked Oscillator (ILO) with low jitter. Thanks to the good performance of this oscillator, we propose a low-power ILCDR with fast locking time and low jitter for burst-mode applications. The main novelty consists of the implementation of a complementary QRO based on back-gate control using FDSOI technology to realize a simple and efficient ILCDR circuit. With a Pseudo-Random Binary Sequence (PRBS7) at 868 Mbps, the recovered clock jitter is 26.7 ps (2.3% UIp-p) and the recovered data jitter is 11.9 ps (1% UIp-p). With a 0.6 V power supply, the power consumption is 318μW. All the results presented here are based on post-layout simulations, as no prototypes have been produced. Similarly, we can estimate the surface area of the chip (without the pad ring) at around 6600 μm2. [ABSTRACT FROM AUTHOR]

This paper presents a detailed refinement and validation of two well-known lifetime prediction models for IGBTs, namely CIPS08 and SKiM63, using experimental power cycling test data. This study focuses on adapting these models to reflect the operational conditions and degradation patterns to more accurately fit different IGBT types and applications. Key modifications include recalibrating the scale factor and temperature coefficients in the SKiM63 model and refining the CIPS08 model coefficients (β1 = −2.910, β2 = 1083.714, β3 = −4.521) based on the impact of temperature fluctuations, bond wire diameter, and electrical stresses observed during power cycling tests. These adjustments provide a significant shift from traditional values, with the recalibrated models offering a better fit, as evidenced by a reasonable coefficient of determination (R2) and root mean square error (RMSE). Utilizing Monte Carlo simulations with a 5% uncertainty, the study calculates the B10 lifetimes of PV inverters, demonstrating a substantial reduction from 43 years in the unmodified model to 13 years in the modified model. This emphasizes the critical need for ongoing modification and validation of predictive models based on the actual operational data to enhance the reliability and efficiency of IGBTs in power electronic systems. [ABSTRACT FROM AUTHOR]

This paper presents new resonant inverter topologies for dual-frequency induction heating (IH). These 2T1C and 3T topologies combine the advantageous features of two- and one-inverter solutions. An analytical description of the load impedance of a dual-frequency series-parallel circuit has been made. Using manufacturer datasheets and LTspice models of selected transistors, a MATLAB model was parameterized. Based on it, power losses are determined as a function of the following parameters: nominal power, frequency and DC bus voltage. The obtained results allowed for determining the data necessary in the design process. The research has been experimentally verified. Tests were carried out for pulsing and simultaneous operation. Power control characteristics as a function of frequency are determined. The possibility of operating the inverter with high efficiency (>97%) in the proposed 2T1C and 3T systems at nominal power is demonstrated. [ABSTRACT FROM AUTHOR]

The passive multipliers based on semiconductor diodes, most frequently a Schottky type, should be driven by a certain value of input power, where the conversion losses are optimal. This means that the variation in the input power level causes the change in the output power level. A solution to this issue is the integration of an output power amplifier, which in the state of saturation provides quasi-stabilization of the output power. Practically, this approach gives an unsatisfactory performance: weak stabilization or narrow input power range. This paper comprises a concept of an active frequency multiplier with the use of one FET transistor and a special adaptive bias circuit in order to obtain a very wide input power range when the output power is stable. The principle of the operation, design guidelines, and measurement results have been presented for an example circuit of the frequency doubler. The results show the possibility to obtain up to 10 dB input power range for a 1 dB change in output power level without the use of additional amplifiers. [ABSTRACT FROM AUTHOR]

This paper discusses some of the design choices underlying the development of watt-level integrated Doherty power amplifiers in the K and Ka band, focusing on compound semiconductor technologies. The key aspect of on-chip power combination is discussed, presenting and comparing some of the possible alternatives. Then, the impact on the achievable bandwidth and performance of different parameters is quantified, adopting an approximate analysis, which focuses on the Doherty output combiner and allows estimating the non-linear performance of the amplifier thanks to some simplifying assumptions, without requiring a full, non-linear model of the active devices. Two sample GaAs and GaN technologies are compared first, considering parameters that are representative of the currently available commercial processes, and then several power combination strategies are analyzed, adopting the GaN technology, which is currently the only one that allows achieving the power levels required by the applications directly on chip. Finally, some hints as to the impact of the output parasitic effects of the transistors on the presented analysis are given. [ABSTRACT FROM AUTHOR]

This paper focuses on the problem of the modeling of FET power transistors made of gallium nitride offered by GaN Systems, Transphorm, and Nexperia. The considered devices have been available on the market since 2014. GaN-FETs are built as a cascade connection of a normally on gallium nitride HEMT and a normally off MOSFET made of silicon. On the manufacturer's sites, one can find models of these devices for like-SPICE tools in the text form. The main goal of this paper is to evaluate the model's accuracy by comparing calculation results obtained by the use of the considered models with the authors' measurement results and datasheet. It has been demonstrated that the GaN Systems model built on controlled sources described by a set of arbitrarily selected mathematical functions more accurately reproduces the basic characteristics of a transistor. On the other hand, the models from Transphorm and Nexperia, which are constructed based on built-in semiconductor device models, more precisely calculate the values of selected functional transistor parameters. [ABSTRACT FROM AUTHOR]

Fiber-type electronics is a crucial field for realizing wearable electronic devices with a wide range of sensing applications. In this paper, we begin by discussing the fabrication of fibers from conjugated polymers. We then explore the utilization of these fibers in the development of field-effect and electrochemical transistors. Finally, we investigate the diverse applications of these fiber-type transistors, encompassing chemical and physical sensors. Our paper aims to offer a comprehensive understanding of the use of conjugated polymers in fiber-type transistor-based sensors. [ABSTRACT FROM AUTHOR]

This paper presents ultra high-density spin-orbit torque magnetic random-access memory (SOT-MRAM) for last-level data cache application. Although SOT-MRAM has many appealing attributes of low write energy, nonvolatility, and high reliability, it poses challenges to ultra-high-density memory implementation. Due to using two access transistors per cell, the vertical dimension of SOT-MRAM is >40% longer than that of the spin-transfer torque magnetic random-access memory (STT-MRAM), a single transistor-based design. Moreover, the horizontal dimension cannot be reduced below two metal pitches due to the two vertical metal stacks per cell. This paper proposes an ultra-high-density SOT-MRAM design by reducing the vertical and horizontal dimensions. The proposed SOT-MRAM is designed by a single transistor with a Schottky diode to achieve lesser vertical dimension than the two-transistor-based design of conventional SOT-MRAM. Moreover, the horizontal dimension is also reduced by sharing a vertical metal between two consecutive bit-cells in the same row. The comparison of the proposed designs with the conventional SOT-MRAM reveals a 63% area reduction. Compared with STT-MRAM, the proposed high-density memory design achieves 48% higher integration density, 68% lower write power, 29% lower read power, and 1.9× higher read-disturb margin. [ABSTRACT FROM AUTHOR]

The Dadda algorithm is a parallel structured multiplier, which is quite faster as compared to array multipliers, i.e., Booth, Braun, Baugh-Wooley, etc. However, it consumes more power and needs a larger number of gates for hardware implementation. In this paper, a modified-Dadda algorithm-based multiplier is designed using a proposed half-adder-based carry-select adder with a binary to excess-1 converter and an improved ripple-carry adder (RCA). The proposed design is simulated in different technologies, i.e., Taiwan Semiconductor Manufacturing Company (TSMC) 50 nm, 90 nm, and 120 nm, and on different GHz frequencies, i.e., 0.5, 1, 2, and 3.33 GHz. Specifically, the 4-bit circuit of the proposed design in TSMC's 50 nm technology consumes 25 uW of power at 3.33 GHz with 76 ps of delay. The simulation results reveal that the design is faster, more power-energy-efficient, and requires a smaller number of transistors for implementation as compared to some closely related works. The proposed design can be a promising candidate for low-power and low-cost digital controllers. In the end, the design has been compared with recent relevant works in the literature. [ABSTRACT FROM AUTHOR]

The reliability of oxide‐semiconductor (OS) thin‐film transistors (TFTs) is significantly influenced by the gate insulator (GI). During electrical bias stress, the defect sites near the semiconductor/GI interface and/or within the GI may trap electrons, which makes the threshold voltage (Vth) shift toward positive values. On the other hand, carbon (C) or hydrogen (H) atoms may diffuse from the GI into the active layer, and act as shallow donors, which induce negative Vth shifts (ΔVth). In this paper, an in situ atomic layer deposition (ALD)‐based GI heterostructure is introduced, which consists of a stack of two complementary materials, namely Al2O3 and SiO2. Here, a competition occurs between electron trapping in Al2O3 (positive ΔVth) and carrier generation from H atoms in SiO2 (negative ΔVth) which allows the achievement of nearly zero ΔVth under positive bias temperature stress (PBTS). This strategy is successfully applied to a high‐mobility (>50 cm2 Vs−1) ALD‐based indium‐gallium‐zinc oxide (IGZO) device, resulting in a net ∆Vth of −0.02 V under PBTS and drain current variation (∆ID) of +0.49% under constant current stress (CCS). The application of an in situ ALD process thus offers valuable insights to resolve the mobility versus reliability trade‐off in high‐performance oxide TFTs. [ABSTRACT FROM AUTHOR]

Intensive research has been carried out on two-dimensional materials, in particular molybdenum disulfide, towards high-performance field effect transistors for integrated circuits1. Fabricating transistors with ohmic contacts is a challenging task due to the formation of a high Schottky barrier that severely limits the performance of the transistors for real-world applications. Graphene-based heterostructures can be used in addition to, or as a substitute for unsuitable metals. In this paper, we present lateral heterostructure transistors made of scalable chemical vapor-deposited molybdenum disulfide and chemical vapor-deposited graphene achieving a low contact resistances of about 9 kΩ·µm and high on/off current ratios of 108. Furthermore, we also present a theoretical model calibrated on our experiments showing further potential for scaling transistors and contact areas into the few nanometers range and the possibility of a substantial performance enhancement by means of layer optimizations that would make transistors promising for use in future logic integrated circuits. [ABSTRACT FROM AUTHOR]

This paper presents a high-speed V-band on-off keying (OOK) modulator in 65 nm CMOS based on distributed transmission lines architecture. The high-speed operation of the proposed OOK modulator is attained by distributing a single large switching transistor into smaller units. The effects of parasitic capacitances of each small switch are mitigated by series inductors, forming an artificial transmission line. The switch size and the number of stages are optimized for a reasonable balance between insertion loss and isolation. Small signal measurement of the OOK modulator reveals 3.8 dB insertion loss and 20.5 dB isolation at 60 GHz, with <5 dB insertion loss and >16 dB on-off ratio from 50 GHz to 70 GHz. Testing with a modulation setup shows the modulator is fully functional up to 5 Gbps at a 60 GHz carrier. Limitations of the test setup prevent modulation testing at >5 Gbps. The fabricated modulator does not consume any DC power and has an active footprint of 0.025 mm2. [ABSTRACT FROM AUTHOR]

The single-event effects (SEEs) of frequency divider circuits and the radiation tolerance of the hardened circuit are studied in this paper. Based on the experimental results of SEEs in InP HBTs, a transient current model for sensitive transistors is established, taking into account the influence of factors such as laser energy, base-collector junction voltage, and radiation position. Moreover, the SEEs of the (2:1) static frequency divider circuit with the InP DHBT process are simulated under different laser energies by adding the transient current model at sensitive nodes. The effect of the time relationship between the pulsed laser and clock signal are discussed. Changes in differential output voltage and the degradation mechanism of unhardened circuits are analyzed, which are mainly attributed to the cross-coupling effect between the transistors in the differential pair. Furthermore, the inverted output is directly connected to the input, leading to a feedback loop and causing significant logic upsets. Finally, an effective hardened method is proposed to provide redundancy and mitigate the impacts of SEEs on the divider. The simulation results demonstrate a notable improvement in the radiation tolerance of the divider. [ABSTRACT FROM AUTHOR]

The diminution of power dissipation has recently become a paramount concern in contemporary VLSI design. Owing to the shrinking chip size and the gradual development of several micro-electronic reliabilities, low-power (LP) system design has become the utmost priority. Hence, this paper proposes an effective power reduction method that combines clock gating (CG) and a multi-bit flip flop (MBFF) approach. Initially, the CG and MBFF schemes were implemented separately in two standard Johnson counters, one involving a true single-phase clock (TSPC) LP D flip flop (DFF) with five transistors and the other involving a standard DFF with 32 transistors. Furthermore, a combined CG-MBFF scheme is proposed and implemented in 4-bit and 16-bit Johnson counters to illustrate the superiority of the proposed CG-MBFF scheme in terms of power diminution over the CG and MBFF methods when implemented separately. Additionally, an LP application employing a 4-bit Johnson counter was implemented with and without the proposed scheme. [ABSTRACT FROM AUTHOR]

Current mirrors with ideal performance are widely in demand for realizing low power applications. In this paper, an FVF current mirror is proposed to have high bandwidth, low input, and boosted output resistance. The low voltage operation is confirmed using flipped voltage follower at the input. Also at the input, a local negative feedback loop is created which reduces the input node resistance and the achieved value ranges below an ohm. The output stage consists of a regulated cascode and a super cascode topology which is driven by an inverting amplifier realized using a self-cascode structure to improve the output resistance. However, instead of using the traditional gate-driven self-cascode, the proposed design uses its quasi-floating gate MOS transistor-based structure which further improves the output resistance and bandwidth. The proposed current mirror operates with minimum error in the range of 0–1000 µA. The bandwidth of the proposed circuit ranges in gigahertz which is 3.1 GHz. The resistance at the input is found as 0.407 Ω whereas the output has boosted resistance to a Giga ohm value which is 86 GΩ. The stability and robustness analysis is done via temperature, process corners and Monte Carlo runs. The complete design is done using the MOSFET model of UMC in 0.18-micron technology at ± 0.5 V with the help of HSpice. [ABSTRACT FROM AUTHOR]

In this paper, high-performance indium gallium oxide (IGO) thin-film transistor (TFT) with a double-gate (DG) structure was developed using an atomic layer deposition route. The device consisting of 10-nm-thick IGO channel and 2/48-nm-thick SiO2/HfO2 dielectric was designed to be suitable for a display backplane in augmented and virtual reality applications. The fabricated DG TFTs exhibit outstanding device performances with field-effect mobility (μFE) of 65.1 ± 2.3 cm2V−1 s−1, subthreshold swing of 65 ± 1 mVdec−1, and threshold voltage (VTH) of 0.42 ± 0.05 V. Both the (μFE) and SS are considerably improved by more than two-fold in the DG IGO TFTs compared to single-gate (SG) IGO TFTs. Important finding was that the DG mode of IGO TFTs exhibits the nearly temperature independent μFE variations in contrast to the SG mode which suffers from the severe remote Coulomb scattering. The rationale for this disparity is discussed in detail based on the potential distribution along the vertical direction using technology computer-aided design simulation. Furthermore, the DG IGO TFTs exhibit a greatly improved reliability with negligible VTH shift of − 0.22 V under a harsh negative bias thermal and illumination stress condition with an electric field of − 2 MVcm−1 and blue light illumination at 80 °C for 3600 s. It could be attributed to the increased electrostatic potential that results in fast re-trapping of the electrons generated by the light-induced ionization of deep level oxygen vacancy defects. [ABSTRACT FROM AUTHOR]

The multiplier is the fundamental component of many computing modules. As the most important component of a multiplier, the full adder (FA) also has a significant impact on the overall performance. Full adders based on pass transistor logic (PTL) have been a very popular research field in recent years, but the uneven delay makes it difficult to analyze the critical path of multipliers based on PTL full adders. In this paper, we propose a model to evaluate the critical path of the carry save array (CSA) multiplier that could reduce the size of the simulation input set from 4 G to 93 K to finally obtain the maximum delay of the multiplier. We propose a novel low-power, high-speed CSA multiplier based on both PTL full adders and CMOS full adders, using our critical-path evaluation model. The proposed work is implemented in the 28 nm process. We use the model to reduce the worst-case delay by 14.5%. The proposed multiplier improved the power delay product by 9.4% over the conventional full CMOS multiplier. [ABSTRACT FROM AUTHOR]

Micro-LED is considered an emerging display technology with significant potential for high resolution, brightness, and energy efficiency in display applications. However, its decreasing pixel size and complex manufacturing process create challenges for its integration with driving units. Recently, researchers have proposed various methods to achieve highly integrated micro-structures with driving unit. Researchers take advantage of the high performance of the transistors to achieve low power consumption, high current gain, and fast response frequency. This paper gives a review of recent studies on the new integration methods of micro-LEDs with different types of transistors, including the integration with BJT, HEMT, TFT, and MOSFET. [ABSTRACT FROM AUTHOR]

With the development of high-voltage and high-frequency switching circuits, GaN high-electron-mobility transistor (HEMT) devices with high bandwidth, high electron mobility, and high breakdown voltage have become an important research topic in this field. It has been found that GaN HEMT devices have a drift in threshold voltage under the conditions of temperature and gate stress changes. Under high-temperature conditions, the difference in gate contact also causes the threshold voltage to shift. The variation in the threshold voltage affects the stability of the device as well as the overall circuit performance. Therefore, in this paper, a review of previous work is presented. Temperature variation, gate stress variation, and gate contact variation are investigated to analyze the physical mechanisms that generate the threshold voltage (VTH) drift phenomenon in GaN HEMT devices. Finally, improvement methods suitable for GaN HEMT devices under high-temperature and high-voltage conditions are summarized. [ABSTRACT FROM AUTHOR]