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Hot electrons with high kinetic energy could be generated in the channel of GaN high-electron-mobility transistors (HEMTs) during hard switching operation. Those “lucky” hot electrons scattered to the vulnerable interface between the passivation and barrier layers could bombard the interface region and create new defects that would lead to degradation of the dynamic on-resistance (${R}_{ON}$) after long-term operations. In this work, we propose a solution to the hot-electron induced device degradation through channel engineering, i.e., deploying a double-channel structure in place of the conventional single-channel structure in ${p}$ -GaN gate HEMTs. It is revealed that hot electrons are mostly generated in the lower channel and thus the additional scattering interface can effectively deter the hot electrons from reaching the vulnerable surface. Dynamic ${R}_{ON}$ degradation induced by long-term stresses at “semi-on” states is shown to be substantially suppressed in the ${p}$ -GaN gate HEMT with the double-channel structure. [ABSTRACT FROM AUTHOR]

With a switching drain bias, the gate reliability of Schottky-type ${p}$ -GaN gate high-electron-mobility transistors (HEMTs) under AC positive gate bias stress has been systematically investigated. The mean-time-to-failure (MTTF) under such application-relevant stress is found to be prolonged compared to that extracted from static and AC gate bias stress tests with the absence of a switching drain bias and exhibits positive coefficients with frequency and OFF-state drain bias (${V} _{\text {DSQ}}$). Such results can be explained by the drain-induced hole insufficiency in the gate stack at large ${V} _{\text {DSQ}}$ , a physical mechanism that results in elevated energy band at ON-state when ${V} _{\text {DSQ}}$ is just switched to low voltage. This non-equilibrium transient status could suppress injection of electrons from the 2DEG channel to the ${p}$ -GaN gate, which in turn substantially weakens the hot-electron’s generation in the depleted ${p}$ -GaN layer and the subsequent bombardment to the gate-metal/ ${p}$ -GaN interface, and thus prolongs the gate lifetime. [ABSTRACT FROM AUTHOR]

A cost-effective engineered bulk silicon (EBUS) substrate technology is presented, featuring p-n junction implemented on bulk Si substrates using mainstream ion implantation and thermal annealing processes. Standard p-GaN/AlGaN/GaN heterostructures are successfully grown on the EBUS substrate and used to fabricate 200-V enhancement-mode p-GaN gate HEMTs. By creating deep trenches in the EBUS substrate to isolate the local P+ silicon regions underneath the high-side (HS) and low-side (LS) power switches, adverse effects (e.g., back-gating and dynamic ON-resistance degradation) in the use of conventional bulk Si substrate are all eliminated. The mechanism of crosstalk suppression in the GaN-on-EBUS platform is revealed in comparison with conventional GaN-on-Si platform and verified by a series of designed tests. [ABSTRACT FROM AUTHOR]

The high-speed superiority of GaN power devices with silicon-based peripheral circuits is not yet fully leveraged, mainly due to the parasitic inductance of interconnections. In this article, we demonstrate a GaN-based gate driver with an overcurrent (OC) protection circuit and an undervoltage lockout (UVLO) circuit on a p-GaN gate power HEMT platform. The gate driver features a rail-to-rail output voltage, suppressed gate ringing, and tunable driving speed, all of which are highly desired in high-efficiency and high-speed GaN power systems. To offer timely but reliable protections, the OC protection and UVLO circuit are designed with reference to the switching speed and the threshold voltage of GaN power devices. The OC protection is implemented with a separated sensing branch and blanking time controller, and the response time to an OC event is reduced to 10 ns after the blanking time. The UVLO circuit has a fixed hysteresis of 0.5 V, and its threshold voltage is especially tailored for the GaN integrated circuits. [ABSTRACT FROM AUTHOR]

In this article, the impacts of the off-state gate bias (VGS,OFF) on dynamic on-resistance (RON) are systematically investigated in commercial Schottky-type p-GaN Gate high-electron-mobility transistors. Double-pulse tester and pulsed I–V system are adopted to evaluate the dynamic RON with various off-state gate and drain bias (VDS,OFF) under hard- and soft-switching conditions. More negative VGS,OFF can aggravate the dynamic RON degradation under both soft- and hard-switching, especially when switching with a high VDS,OFF. The impacts of VGS,OFF on switching transients and off-state stress are investigated separately to reveal the underlying mechanisms, which are found to be associated with the generation and movements of holes. The off-state gate bias of the voltage-driving scheme needs to be carefully considered according to the identified mechanisms in terms of dynamic on-resistance degradation. [ABSTRACT FROM AUTHOR]

A tunnel-oxide-free GaN-based non-volatile memory (NVM) device is proposed to untangle the trilemma among speed, retention, and endurance in the implementation of conventional NVM. The program and erase (P/E) are based on bipolar charge injection controlled by individual junction barriers, whereas the data retention relies on bipolar charge trapping in an interfacial charge storage layer. The wide bandgap energy of GaN allows the formation of deep-level traps at a dielectric/GaN interface and high junction barriers in GaN, both of which benefit long-term retention. As such, the GaN-based NVM device could get rid of the tunnel oxide, thereby enabling faster P/E processes and facilitating to decouple the enhancement of endurance from that of speed and retention. The proposed device demonstrates a P/E time of 100 ns, endurance over 106 cycles, and long retention time. [ABSTRACT FROM AUTHOR]

Short circuit (SC) capability of 650-V Schottky-type p-GaN gate high-electron-mobility transistors (HEMTs) under single and repetitive tests is characterized in this article. The investigated devices exhibit strong capability under a single SC test, but weak capability under repetitive SC tests with a bus voltage of 400 V and a gate drive voltage of 6 V. The failure mechanism under repetitive SC tests is revealed through electrothermal simulation and microscale failure spot analysis. Thermal fatigue cracks are formed due to the high temperature spike and local temperature fluctuations in the narrow GaN channel and buffer layers, leading to weak repetitive SC capability. The unique heat confinement effect in the GaN layer plays an important role in the formation of high temperature spike and fatigue cracks. The withstand time in a single SC test is several hundred microseconds due to fast drain current drop that results from high temperature and, to a lesser degree, the dynamic threshold voltage shift during the SC transient. The device failure in a single-event SC test is related to heat diffusion to a wider region. Some guidelines are proposed for handling and improving the repetitive SC capability. [ABSTRACT FROM AUTHOR]

A closely coupled double-channel (DC) structure realized on an 8-inch GaN-on-Si wafer is utilized to fabricate GaN high-electron-mobility-transistors (HEMTs) with enhanced RF linearity. The strong channel-to-channel coupling from this DC structure enables efficient transport of electrons between the two parallel channels to accommodate balanced carrier concentration and current density between the two channels. Consequently, the nonlinearity of source resistance under high current operations and the external bias dependence of cut-off frequencies could be substantially mitigated, leading to device linearity enhancement. Meanwhile, the DC structure enables simple top gate control that favors a high-yield planar process. Two-tone measurements at 4 GHz show that the DC GaN HEMT delivers an output 3rd-order intermodulation point (OIP3) that is improved by 5.2 dB over a single-channel GaN HEMT. [ABSTRACT FROM AUTHOR]