As 2-D CMOS reaches its fundamental scaling limits due to device, manufacturing, and interconnect bottleneck related constraints at the nanoscale, migration to 3-D provides a possible alternative to continue technology scaling in future. Toward that goal, several 3-D integration approaches with multi-die, multichip, and sequential layers stacking are pursued. However, these approaches only show incremental density benefits and exhibit new challenges, such as lack of thermal management, increasing cost, and reliability issues. In contrast to these, we proposed a radically different fabric concept, called stacked horizontal nanowire-based 3-D CMOS (SN3D), on a single die that can offer a paradigm shift in technology scaling as well as design. Using prefabricated and doped stacked horizontal nanowires as fundamental building blocks, the fabric is assembled using architected connectivity and insulation features. Innovations in circuit style for mapping to SN3D’s physical framework, and bottom-up material filling-based manufacturing techniques are also central to our approach. In this paper, we detail, fabric’s core constructs, logic circuits implementation in SN3D fabric, benchmarking methodology and results, and finally the manufacturing aspects. Our circuit analysis reveals tremendous benefits; for a 4-bit full adder design, SN3D shows $11\times $ , 19%, 18%, and 6.7 $\times $ , 8.69%, 9% benefits over state-of-art 2-D CMOS and transistor-level monolithic 3-D in terms of density, power, and performance, respectively. In addition, our step-by-step TCAD emulation of manufacturing flow establishes feasibility. If realized, the SN3D fabric can be transformative for the semiconductor industry. [ABSTRACT FROM AUTHOR]