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This paper presents a balancing algorithm for the so-called Director Switch, a controlled, reverse conducting, self-powered, high-voltage switch, using series-connected insulated gate bipolar transistors (IGBTs). This is a key component on two new voltage-source, high-voltage direct current (HVDC) converter topologies. These, which promise efficiency, cost, and size reductions, are an alternate arm converter and a series bridge converter. One of the main design challenges of the director switch is how to supply the IGBT gate drivers, and other auxiliary electronics while overcoming the high-voltage insulation barrier to ground level. In this paper, this is achieved by using the energy stored in a capacitive clamp snubber circuit, which also helps with the overvoltage mitigation during rare hard-switching events. However, the clamp capacitor and by proxy the IGBT voltages become highly unbalanced during operation, compromising the integrity of the switch. This paper presents a balancing strategy that consists in applying a controlled delay in the switching of the IGBT levels, in a way that forces a voltage balance on all the switch levels. The paper explains the unbalance. Then, the balancing strategy is explained and validated on simulation and on a high-voltage experimental rig, on switches comprising two and three series-connected IGBTs, respectively. [ABSTRACT FROM AUTHOR]

This paper presents a dc–dc input-parallel output-parallel (IPOP) converter configuration for renewable energy integration with medium-voltage dc grids. A full-bridge zero-current-switching (FB-ZCS) converter with voltage-doubler output is proposed as the fundamental module. To achieve smooth current commutation and ZCS, the leakage inductance of transformer and a resonant capacitor across its secondary are utilized. This resonant capacitor is always charged to its full-rated capacity irrespective of converter loading and requires a dedicated charging interval resulting in duty-cycle loss. For a given leakage inductance, a large resonant capacitor is required for higher current ratings. With a single-centralized converter, these operational and design constraints result in significant duty-cycle loss, restricting the operation range. This paper proposes an IPOP configuration for high-power applications. Phase shedding at reduced loading ensures that individual modules are operated optimally. Input inductance requirement in modules is reduced due to interleaving of the input current. Additionally, voltage stress across converter components and input current ripple are reduced by 50% in the proposed converter modules. Steady-state operation, modeling, current-sharing control, start-up, and shutdown of modules in the IPOP configuration are demonstrated using simulations. Experimental results on a scaled-down prototype are presented to validate its operation. [ABSTRACT FROM AUTHOR]

This paper presents a neutral-point deviation and ripple compensating control method applied to a three-level neutral-point-clamped (NPC) converter. The neutral-point deviation and its harmonic components are analyzed with a focus on the average current flowing through the neutral-point of the dc link. This paper also proposes a control scheme compensating for the neutral-point deviation and dominant harmonic components under generalized unbalanced grid operating conditions. The positive and negative sequence components of the switching functions and ac input currents are employed to accurately explain the behavior of three-level NPC converter. Simulation and experimental results are presented to verify the validity of the proposed method. [ABSTRACT FROM AUTHOR]

A high-frequency high voltage gain discontinuous conduction mode coupled-inductor boost LED driver based on planar component is presented in this paper. GaN switch is adopted with lower conducting resistance and higher switching speed. Zero voltage switching (ZVS) is achieved at the same time to reduce high switching loss caused by high switching frequency. Compared with the previous work, the voltage gain is higher and efficiency is higher because of ZVS. This paper focuses on high efficiency; therefore, resonant gate driver is adopted and efficiency is increased by 0.6%. In terms of the coupled-inductor, planar component is used and parameter optimization is also proposed to realize lower loss, including wingding loss and fringing loss caused by the air gap. A 500 kHz 36 W prototype has been designed to demonstrate theoretical analysis. In addition, comparison of drive loss between the resonant gate driver used in this paper and conventional driver implemented by Si8271 is made, revealing advantages of the resonant driver. Obtained efficiency was up to 92.1% at full load. [ABSTRACT FROM AUTHOR]

Power converters are one of the failure sources in modern power systems, and hence driver of maintenance and downtime costs, which should be reduced by reliable design, control, and operation of converters. This paper proposes a power sharing control strategy for evenly distributing the thermal stresses among dc converters in dc microgrids, and consequently enhancing the overall system reliability. The aim of this paper is to extend the aging process of failure prone converters by adjusting their loadings. The proposed approach employs the prior experienced thermal damages on the converter's fragile components in order to adjust its contribution on demand supply. According to the proposed strategy, the higher the thermal stress on a converter is, the lower the power it will supply. As a result, the overall system reliability will be improved. A numerical case study on a dc microgrid is presented to illustrate the effectiveness of the proposed power sharing strategy. Moreover, experimental tests are provided to demonstrate the applicability of the reliability-oriented power sharing method. [ABSTRACT FROM AUTHOR]

Advanced power systems for electromagnetic propulsion depend on capacitor banks as the first stage of pulsed power. Significant electrical energy is required to support a number of anticipated launch applications. In support of successful integration of these technologies, TPL has developed an improved dielectric material for high energy density capacitors. Recent developments have led to a novel dielectric film that can be fabricated and incorporated into innovative, high-voltage designs using conventional manufacturing processes. Full-scale (100 kJ) capacitors incorporating TPL's established film technology is projected to provide an energy density between 3.5 and 4.0 J/cm3. [ABSTRACT FROM AUTHOR]

DC fault protection is the bottleneck that restricts the development of modular multilevel converter based high voltage direct current (MMC-HVDC) system. Superconducting fault current limiters (SFCL) is an ideal protection device that can significantly limit short circuit current and enhance the fault tolerance ability of MMC-HVDC system. At present, several topologies of SFCLs have been proposed, but there is no systematical study of their current-limiting characteristics in MMC-HVDC. This paper studies the development process of DC short-circuit faults in MMC-HVDC system, and analyzes its demand for fault current limiting. Then, resistive type, saturated iron core type and hybrid type SFCL are modeled and their limiting effect of critical fault current under DC pole-to-pole fault is tested. By comparison, the current-limiting characteristics of three types of SFCL are concluded. Results show that resistive SFCL has best performance in steady state, while saturated iron core SFCL has best performance in transient state. The current-limiting characteristic of hybrid type SFCL is between the other two types. [ABSTRACT FROM AUTHOR]

The dc-dc converters with high step-up DC-voltage gain play a vital role in integrating low voltage DC sources. Though several converter topologies are reported in the recent past, attempts have been made to reduce the components, especially the switching devices, passive elements, converter losses, etc., of the converter. A novel DC-DC converter topology, viz., single switched impedance network (SSIN)-based converter with n-stage is proposed in this paper. The operation of the SSIN based converter in continuous and discontinuous conduction modes are discussed. The effect of parasitic elements on DC-voltage gain and efficiency of the SSIN is carried out. The small-signal model of the SSIN converter is derived. The performance of the SSIN converter is compared with the similar converter topologies. The 500 W prototypes of the SSIN with n = 1 and n = 2 are fabricated, and the experimental results are presented in this paper. To improve the converter performance, SiC-based semiconductor devices are used. The SSIN converter with two-stage has low switch loss at 500 W load, improved efficiency during high power and high output voltage operation, the switch stress of Vo/2, etc. [ABSTRACT FROM AUTHOR]

Common inductor (CIM) and common capacitor (CCM) passive current-sharing methods have the advantages of simple implementation and low cost. However, there is still a lack of detailed comparative research on the two methods, which makes researchers confused when choosing the two methods. To provide clear scheme guidance, this paper provides a detailed comparison of the performance of the two methods. Firstly, this paper reveals the difference between the current waveforms of the two methods, that is, the current waveform of the CIM method is distorted, while the CCM method is non-distorted. Then, the mechanism of the above phenomenon is analysed in depth. Secondly, for comparing the current sharing performance of the two methods, the first harmonic approximation (FHA) equivalent circuit model considering parasitic parameters is established to obtain the system’s current sharing error model, and the parameter sensitivity analysis is provided. Finally, the relationship between the current waveform, current sharing error, and load ripple of the two methods is discussed. Then, based on the two methods, a more attractive common resonate tanks (CRT) current-sharing method is proposed. The correctness of the view in this paper has been verified by extensive simulations and experiment results. [ABSTRACT FROM AUTHOR]

Various overvoltage mitigation schemes were used in literature in suppression of switching overvoltages in wind farms. However, the evaluation of how the effectiveness of these mitigation techniques would vary with the change of the wind farm topology is still un-explored territory. The main aim of this paper is to study the effectiveness of four mitigation schemes while using SF6 circuit breaker namely; R–L smart choke, R–C snubber circuit, surge capacitor and pre-insertion resistor (PIR) were studied in four different wind farm topologies; radial, single-sided ring, double-sided ring and star topologies. The topologies were based on a real wind farm located in Zaafrana, Egypt. The results showed that R–L choke to be the most effective scheme for all topologies followed by PIR, R–C snubber and surge capacitor schemes respectively. Their percentage of reduction of overvoltage ranged from 62 to 84% for R–L choke, 33–67% for PIR, 8–25% for R–C snubber circuits and 4–15% for surge capacitors. Also, it was shown that the change of the wind farm topology didn't affect the order of effectiveness of the mitigation schemes such that R–L remained the most effective and surge capacitor the least effective for all topologies. [ABSTRACT FROM AUTHOR]

In this paper, a solution is proposed to the problem of the unequal phase imbalance of output voltage caused by a three-phase, four-wire, split capacitor inverter when the load is unbalanced. First, the triple-loop control strategy was used to solve the unequal amplitude problem. This method used the feedforward + feedback composite control strategy on the inductor current inner-loop and voltage mid-loop to decrease the disturbance of the power and load. And the Root Mean Square (RMS) of voltage on the outer-loop completed the control of amplitude for the three-phase voltage. Second, to solve the imbalanced phase problem, the imbalance operation mechanism of the three-phase four-wire inverter was analyzed. It is known from the analysis that the phase imbalance is related to the DC-side splitting capacitance. The function relations between the DC-side capacitance and phase angle between each phase was simulated by MATLAB. But, it was too complicated to calculate the magnitude of the capacitance value through the functional relationship. In order to simplify the design of the DC-side splitting capacitor, the relations among the imbalanced current, the voltage fluctuations of the DC-side capacitor and the harmonics of load voltage were analyzed. In addition, by following the requirement of the national standard about the harmonics of load voltage, a DC-side capacitor design was mentioned to decrease the influence of imbalanced phase. Finally, simulation and experimental results show that the three-phase load voltage is stable, the THD value is less than 3%, and three-phase voltage unbalance is less than 2%, thus verifying the effectiveness of the proposed DC-side split capacitor design and control strategy. [ABSTRACT FROM AUTHOR]

This paper presents a comprehensive techno-economic analysis of different energy storage systems (ESSs) in providing low-voltage ride-through (LVRT) support for power electronics-based electrolyzer systems. A framework for analyzing the performance of a grid-integrated electrolyzer-ESS system is developed, taking into account realistic scenarios and accurate models. The system components consist of a 500 kW alkaline electrolyzer module integrated with a medium-voltage grid and three different commercially available ESSs based on Li-ion battery, Li-ion capacitor, and supercapacitor technology, respectively. The performance of these ESSs is extensively studied for three LVRT profiles, with a primary focus on the upcoming Danish grid code. In order to perform simulation studies, the system is implemented on the MATLAB®/Simulink®-PLECS® platform. The results demonstrate that all three energy storage technologies are capable of supporting the electrolyzer systems during low-voltage abnormalities in the distribution grid. The study also reveals that the supercapacitor-based technology seems to be more appropriate, from a techno-economic perspective, for fault ride-through (FRT) compliance. [ABSTRACT FROM AUTHOR]

In this paper, a new ultra-low-power double-inverter-based and multi-mode, high-order universal OTA-C filter is presented. The proposed circuit is designed based on the use of subthreshold biased double inverters as OTA blocks which leads to the reduction of power consumption as well as the chip size area. Furthermore, the grounded capacitors are employed in the proposed circuit to properly reduce the noise and parasitic effects of the proposed circuit. Moreover, another advantage of the proposed filter circuit is the low sensitivity of the proposed circuit performance to the values of the active and passive elements in the circuit. However, the proposed design is simulated in CADENCE using 0.18 µm CMOS technology parameters. As simulation results show, the proposed low-power filter has very good performance that can be considered as a proper universal OTA-C filter for ultra-low-power applications. [ABSTRACT FROM AUTHOR]

As advanced systems continue to advance and fuse functions expand, the demand for higher power supply requirements for fuses has increased. Consequently, researchers have turned their attention to the recovery of energy from the environment. Piezoelectric energy harvesting has gained significant popularity due to its advantageous characteristics, such as high energy density, ease of implementation, and compact size. However, the presence of various component types within the energy harvesting circuit inevitably results in the generation of reactive power, leading to a reduction in the circuit's power factor. To address this issue, this paper introduces the adoption of the third-order valley-fill circuit as the power factor correction circuit. The implementation process involves the utilization of Multisim software to simulate the double-limit zero-crossing detection circuit, pulse signal generation circuit, and power factor correction circuit. Furthermore, the aforementioned circuits were subjected to plate-level welding, followed by individual tests to evaluate the effectiveness of the double-limit zero-crossing detection, pulse signal test, and load voltage measurement. These findings unequivocally exemplify the successful accomplishment of the intended objective of augmenting the output power by the third-order valley-fill circuit. [ABSTRACT FROM AUTHOR]

The conventional proportional-gain-feedback link can only obtain the smallest effective damping region (EDR) due to the control delay among all the active damping methods regarding the capacitor current feedback. The digitally controlled system tends to be unstable when the system resonant frequency reaches the critical frequency caused by the grid impedance variation. To weaken the adverse effect on the system caused by the control delay, phase-lead feedback links are applied along the feedback path to provide phase compensation. By taking the simplicity and reliability of the feedback links into account, this paper proposes an alternative to an ideal differentiator, which consists of the Tustin discrete form of 's' and a digital low-pass filter. This proposed method has an identical phase frequency characteristic as an ideal differentiator but a better magnitude frequency characteristic, and its EDR can reach [0, fs/3]. The system stability analysis is conducted under different resonant frequencies, and under the condition of a weak grid, the co-design approach of the active damper and digital controller is presented. Finally, the experimental results are shown to verify the proposed method. [ABSTRACT FROM AUTHOR]

The development of aqueous zinc‐ion capacitors (ZICs) is an effective approach to improve the safety and environmental friendliness of energy storage devices. In this paper, TiC/CNTs core‐shell array structures (TCT) were synthesized on titanium substrate through in‐situ simple chemical vapor deposition and carbon reduction and used as self‐supporting cathodes for aqueous ZICs. As expected, as‐prepared TCT electrode exhibited excellent electrochemical performance in aqueous electrolytes, demonstrating a high specific capacitance of 275.13 F g−1 at a current density of 1.0 A g−1 and maintaining 90.5 % of its initial capacity after 10000 charge‐discharge cycles. The assembled Zn//TCT ZIC displays excellent rate capability, delivering an excellent specific capacitance of 298.2 F g−1 at 0.5 A g−1 and 193.5 F g−1 at a high current density of 10 A g−1. Zn//TCT device can provide an ultra‐high energy density of 24.8 Wh kg−1 at a power of 6984.1 W kg−1. DFT calculations further demonstrate that a large number of electrons are transferred at the TiC/CNT interface and stable TIC−C bonds can be formed. This work provides a new strategy for rationally designing transition metal carbide electrodes and constructing ZICs with high energy and power densities. [ABSTRACT FROM AUTHOR]

This paper presents a floating meminductor emulator circuit using a voltage differencing inverted buffered amplifier (VDIBA), current follower (CF), and two grounded capacitors. The parasitic resistance at the input terminal of the current follower has been utilized. The idea of implementing a meminductor emulator is simple and works on the principle of putting memory inside the active inductor circuit. A capacitor (memory element) has been charged by the current flowing through the active inductor circuit. Therefore, the proposed meminductor emulator can be viewed as an active inductor circuit having memory inside it. The proposed floating meminductor emulator works over a significant range of frequencies and satisfies all the characteristics of a meminductor. The meminductor emulator has been realized and simulated in the LTspice simulation tool using TSMC's 180-nm CMOS technology parameters. A chaotic oscillator circuit has been realized using the proposed meminductor emulator to verify its performance. The results obtained for the chaotic oscillators are found to be satisfactory and thus verify the performance of the proposed meminductor emulator. [ABSTRACT FROM AUTHOR]

This paper introduces an optimized DC–DC converter that employs a modified switched inductor-capacitor technique to achieve ultra-high voltage gain for renewable energy systems. The development is based on adding one cell of modified switched inductor (MSL1) with series diodes interleaved with the main switch in the proposed DC–DC converter. The (MSL1) with capacitor operates in resonant mode to reduce current stress across the main switch when the charge in capacitor becomes zero. This approach also reduces voltage stress across the main switch, all inductors, and diodes. Furthermore, modified switched inductors (MSL2) with an auxiliary switch and a coupled capacitor are incorporated to provide double boosting voltage and to achieve high voltage gain. Additionally, a main and auxiliary switch are integrated with modified switched capacitors (MSC) to provide ultra-high voltage gain and to reduce voltage stress across auxiliary switch. Moreover, the proposed converter exhibits a continuous input current with zero pulsating, even at very low duty cycles. The advantages of the proposed converter are high efficiency, low voltage stress, and low values of inductors and capacitors when utilizing a high switching frequency. A mathematical model for the proposed converter is developed for both continuous conduction mode and discontinuous conduction mode. In addition, the PCB design for the proposed converter is presented, and experimental tests are conducted to verify the simulation and laboratory results. The proposed converter aims to boost the voltage from 20 to 40 V to a variable output voltage between 200 and 400 V, delivering 400 watts of power with an efficiency of 96.2%. [ABSTRACT FROM AUTHOR]

Capacitance and Insulated gate bipolar transistor (IGBT) junction temperature are two critical healthy parameters for modular multilevel converters (MMC) sub‐modules (SMs) condition monitoring. This paper proposes an integrated monitoring method for capacitance degradation and IGBT junction temperature variation. By measuring multiple characteristics of the same port voltage, the capacitance and the junction temperature can be obtained simultaneously, which greatly simplifies the measurement unit required for condition evaluation and realizes the submodule‐level condition monitoring at a lower cost. The capacitance is characterized by voltage changes during capacitor discharging and the junction temperature is monitored by capacitor voltage overshoot (peak value) during IGBT turn‐off. Theoretical analysis and experimental results verify the effectiveness of the proposed method and articulated the influence of load current, SM capacitor pre‐discharge voltage, and junction temperature. Moreover, an online data‐acquisition circuit for time‐specific capacitor voltage characterization is devised. [ABSTRACT FROM AUTHOR]

Modular Multilevel Converters (MMCs) are promising candidates for high‐voltage high‐power applications. The main challenge of the MMCs is the zero‐frequency operation. To achieve a successful DC–DC conversion process with balanced capacitors' voltages with limited voltage ripple, this paper suggests the employment of the conventional two‐leg half‐bridge submodule‐based MMC structure in conjunction with a single bidirectional high‐voltage (HV) valve across the low‐voltage side. In the suggested structure, the HV valve is controlled on and off to ensure energy equalization for the MMC arms. In addition, soft‐switching for the HV valve is proposed to reduce the switching losses. Detailed illustration and design of the proposed concept are presented. Simulation and experimentation results are elucidated to show the effectiveness of the proposed DC–DC hybrid MMC. The results showed efficient performance of the suggested converter. [ABSTRACT FROM AUTHOR]

In this paper, an interleaved fly-back-forward boost converter with a new auxiliary circuit was presented. An auxiliary circuit with a low number of elements provided zero voltage switching conditions to turn the switches on and off; besides, the energy of the transformer leakage inductance was properly absorbed by the auxiliary circuit and prevented voltage spikes on the switch. Furthermore, the third winding in the auxiliary circuit not only transfered the energy of the auxiliary circuit to the output but also caused a complete discharge of the snubber capacitors of the main switches in the resonance process. This auxiliary circuit could be expanded, and the number of auxiliary switches did not increase with the addition of converter branches. The performance of the proposed converter was fully analyzed, and a 120 W laboratory prototype was implemented to demonstrate its correct operation. The results showed a 6.5% increase in the efficiency compared with the converter without an auxiliary circuit. [ABSTRACT FROM AUTHOR]

Compactness has obtained sufficient importance in wideband phase shifter design considerations, as it is directly related to fabrication cost. In this paper, a novel structure was presented to create compact broadband 180-degree phase shifter, which has the advantages of enhanced bandwidth and significantly reduced chip area. The proposed configuration consists of edge-coupled multi-microstrip lines (ECMML) and an artificial transmission line (ATL) with dual-shorted inductors, both of which have the periodic shunt load of capacitors. The ECMML can provide a high coupling coefficient, leading to an increase in the bandwidth, while the introduced capacitors can greatly reduce the line length (35.8% of the conventional method). To verify the relevant mechanisms, a wideband switched network with compact dimensions of 0.67 × 0.46 mm2 was designed via 0.15-micrometer GaAs pHEMT technology. Combined with the measured switch transistor, it was shown that the proposed phase shifter exhibits an insertion loss of less than 2 dB, a return loss of greater than 12 dB, a maximum phase error of less than 0.6° and a channel amplitude difference of less than 0.1 dB in the range of 10 to 20 GHz. [ABSTRACT FROM AUTHOR]

Microwave transducers are widely used for sensing applications in areas such as gas sensing and microfluidics. Inkjet printing technology has been proposed as a promising method for fabricating such devices due to its capability to produce complex patterns and geometries with high precision. In this work, the temperature-dependent electrical properties of an inkjet-printed single-port interdigitated capacitor (IDC) were investigated at cryogenic temperatures down to 20 K. The IDC was designed and fabricated using inkjet printing technology, while its reflection coefficient was measured using a vector network analyzer in a cryogenic measurement setup and then transformed into the corresponding admittance. The resonant frequency and quality factor (Q-factor) of the IDC were extracted as functions of the temperature and their sensitivity was evaluated. The results showed that the resonant frequency shifted to higher frequencies as the temperature was reduced, while the Q-factor increased as the temperature decreased. The trends and observations in the temperature-dependent electrical properties of the IDC are discussed and analyzed in this paper, and are expected to be useful in future advancement of the design and optimization of inkjet-printed microwave transducers for sensing applications and cryogenic electronics. [ABSTRACT FROM AUTHOR]

This paper presents a unique methodology to calculate the filtering capacitances of the OpAmp already reported in the literature. The methodology aims to show that there is an optimal solution that can be used to increase the electromagnetic interference (EMI) immunity of any OpAmp for a wide range of frequencies. By using this proposed methodology, an OpAmp structure that reduces the EMI effect is designed in standard 0.18\ \mu \textm mixed-mode CMOS technology. Detailed mathematical analyses and simulation results are presented and discussed. Simulation results show that the maximum EMI-induced offset voltage in the frequency range from 1 MHz to 1 GHz for the OpAmp is 4.4 mV. In contrast, the standard Miller OpAmp exhibits a maximum EMI-induced offset voltage of 92.4 mV under the same operating conditions. [ABSTRACT FROM PUBLISHER]

A novel high-voltage direct current (HVdc) power supply which has no transformer or voltage multiplier circuit is presented and analyzed in this paper. This is made possible upon the diodes storage delay phenomenon. This proposed power supply is compact, lightweight, and low cost. Its basic structure includes a diode with a proper reverse recovery specification that plays the role of a step-up transformer in the conventional HVdc supplies and a high-voltage capacitor which stabilizes the output voltage. This structure has remarkable advantages over the conventional transformer-based HVdc supplies, such as compactness, a low ripple output, and a low-cost power supply. Performance of the proposed method and its accuracy are investigated in this paper. The results are verified by implementation of a 1.2-kV prototype supply. [ABSTRACT FROM AUTHOR]

This paper presents the effect of stray capacitances in bipolar (negative and/or positive) pulses generated by the two different topologies of the solid-state Marx modulators. According to the analysis, the stray capacitances influence the energy transfer from the Marx modulator capacitors to the load affecting the bipolar (negative and/or positive) pulse rise time. This paper deals with the structure design to reduce the influence of the stray capacitance and to improve the pulse rise time of these bipolar solid-state Marx modulators. A four-stage laboratory prototype of the two topologies has been assembled using 1200-V insulated gate bipolar transistors and diodes, operating with 1000-V dc input voltage and 1-kHz frequency, producing 4-kV bipolar pulses, with 5- \mu \texts pulse duration and 120-ns rise time, into a resistive load. [ABSTRACT FROM PUBLISHER]

This paper presents a new soft switching high voltage gain interleaved dc-dc converter with a three-windings coupled inductor for a fuel cell vehicle. Two interleaved and intercoupled boost cells are connected by the input parallel and output series (IPOS) configuration, realizing low input current ripple and high voltage gain simultaneously. All power switches can operate under soft switching conditions by only adding a simple auxiliary circuit composed of one auxiliary inductor and one power switch. Besides, the auxiliary inductor is coupled with the main inductors, which results in a rapid zero convergence of the auxiliary current and a small conduction loss of the auxiliary circuit. The operating principle, steady state characteristic, comparison with other converters, and parameter design are analyzed in this paper. Finally, the main characteristics of the proposed converter are verified by a 1-kW laboratory prototype. [ABSTRACT FROM AUTHOR]

Capacitor mismatch plays an important part in the spurious-free dynamic range (SFDR) performance of high-resolution successive approximation register (SAR) analog-to-digital converters (ADCs). This paper presents a symmetric group control dynamic element matching (SGCDEM) method aiming at enhancing SFDR of SAR ADCs applied in biomedical applications. The proposed scheme symmetrically divides the capacitor array into four sub-DACs, using quantization results corresponding to each sub-DAC as rotary control codes to symmetrically control the rotation of the capacitors. In order to improve the energy efficiency and save chip area, the proposed method replaces the pseudo-random number generator (PRNG) with quantization results of ADC as the rotary control code. Moreover, split rotator technology is applied in the proposed scheme to reduce the number of multiplexers (MUX) used in the rotator, which introduces a low logic depth. The proposed architecture has been implemented on a 12-bit SAR ADC model in MATLAB in order to verify its performances. After taking a standard deviation of 1% for the unit capacitance into consideration, this method achieves above 77.3 dB SFDR, enabling to correct the SFDR by more than 23.6 dB compared with the structure without DEM. [ABSTRACT FROM AUTHOR]

This paper summarizes the work performed by the Task Force —within Performance Characteristic Subcommittee of IEEE PES Transformers Committee— to investigate potential revisions to IEEE Std C57.142-2010. Although the scope of this document does not implicitly exclude HV and EHV systems, the existing document primarily includes examples and information on distribution voltage systems. A Task Force was formed to investigate the need to include information about power system transient events on HV systems more explicitly in this existing document. The Task Force was charged with the following tasks:-Establish system voltages encompassed by C57-142-2010 Guide. -Gather field data, reports, and literature on HV and EHV failures related to substation transients and transformer interaction. -Solicit input from the other technical committees on this subject. -Review IEC and CIGRE work in this area. -Recommend course of action on revision of the present Guide. -Recommend high level changes to the Guide. -Prepare final paper for the Subcommittee. In the course of this work several failure scenarios were identified. These are categorized and the failures are described in this paper. The final recommendations to the Subcommittee are summarized and recommendations are presented for the course of action on the revision/addition of HV and EHV material to the current C57.142 Guide. [ABSTRACT FROM AUTHOR]

This paper presents a single-phase transformerless bidirectional power factor corrector (PFC). A capacitor is inserted into a conventional full-bridge PFC by connecting the ac line terminal and a terminal of DC voltage. The functions of this inserted capacitor have two roles: to bypass the common-mode leakage current from the stray capacitor; to form an LCL filter to reduce the inductor current ripple. A hybrid modulation method is employed in this PFC. The unipolar switching scheme is applied to modulate the PFC, which can achieve high efficiency. Meanwhile, an additional modulation is inserted into the blank time of low-frequency switches to decrease the changing speed of the voltage on the inserted capacitor, and to decrease the spike on the inductor current and leakage current. The performance of the PFC is experimentally verified using a 5 kW prototype. [ABSTRACT FROM AUTHOR]

Conventional resistive gate driving circuits suffer from significant recovery gate driving losses, especially at MHz ranges. The increasing gate driving losses brought by high switching frequency place a limitation to the high power density converter design. This paper proposes a novel floating resonant gate driver which maintains high efficiency at several megahertz operating frequency. The gate loss reduction is achieved by adopting a resonant process with driving power recycling. Part of the gate driving power can be recycled to a gate driving capacitor in the gate driving loop during charging and discharging. The proposed gate driver merges the merits of fast switching speed and low gate driving losses. A prototype of LLC power converter with the proposed floating resonant gate driver operating at 3.5 MHz is implemented. According to the experimental verification, the proposed gate driver realized a driving loss reduction by 70% and theoretical analysis is in good agreement with experimental results. [ABSTRACT FROM AUTHOR]

Step-up converters are widely used in many applications, such as renewable energy generation with photovoltaic panels and fuel cell stacks. In many cases, the required voltage gain is larger for those applications than a traditional boost converter can achieve. Several large-voltage gain converters have been recently studied. This paper introduces a converter topology in which the voltage gain is larger than a traditional boost converter. The main advantages of the proposed topology are: (i) it provides a large voltage gain without the use of an extreme duty cycle; (ii) its capacitors require a smaller voltage to be sustained compared with other, similar state-of-the-art converters; (iii) the voltage among the ground input and output is not pulsating; and (iv) it can be synthesized with commercial, off-the-shelf half-bridge packed transistors. The proposed converter can be employed in different applications, such as distributed generation and microgrids. This paper presents the steady-state analysis of the proposed converter in the continuous conduction mode, a short comparison with similar topologies, and their voltage on capacitors. Computer-based simulation results are provided to verify the principle of the proposed converter in different operating conditions. [ABSTRACT FROM AUTHOR]

In distributed generation systems, the inverter is the main power interface and its stability directly determines the reliable operation of the grid-connected system. As a typical topology for a three-phase four-wire inverter, the LCL-type three-phase four-wire split capacitor inverter (LCL-TFSCI) is taken as the research subject of this paper. Compared with the three-phase three-wire inverter, there is an additional zero-sequence path in the LCL-TFSCI. Therefore, it is not only necessary to consider the stability of the positive and negative sequence system, but there is also the need to consider the stability of the zero-sequence system when performing stability analysis for the LCL-TFSCI. In this paper, a small-signal impedance model considering the zero-sequence loop of LCL-TFSCI is firstly established. Subsequently, the instability risk is revealed when LCL-TFSCI is connected to the grid with parallel compensation capacitors. Through instability analysis, an impedance-reshaping method based on the complex filter and combined differential elements is proposed, which can reshape the impedance characteristic of LCL-TFSCI within the wide frequency range and expand the stability domain of the grid-connected system. Finally, the proposed method is verified by simulation and experiment. [ABSTRACT FROM AUTHOR]

In this paper, we present on-chip frequency compensation with a capacitor multiplier for a current-mode control DC-DC converter. The capacitor multiplier technique can effectively remove the crossover frequency from the origin. An equivalent capacitance is obtained by amplifying the small current in the capacitor. The value of the equivalent capacitor can be adjusted. The functional block diagram and small-signal transfer function of a buck DC-DC converter are derived for a simplified system loop for on-chip frequency compensation with a capacitor multiplier. In this paper, the derived system transfer function for frequency compensation is verified by simulation and from test results. The proposed circuit is suitable for low-cost and small-size applications. Simulation results and experimental results are presented to demonstrate the theoretical analysis. [ABSTRACT FROM AUTHOR]

Shunt capacitors are usually installed in distribution grids for power factor correction. On the other hand, the number of harmonic‐producing sources such as wind turbines (WTs), photovoltaic (PV) panels, storage units, and electronic loads is rapidly growing in distribution grids. Since improper placement and sizing of shunt capacitors in harmonic‐polluted grids may aggravate power quality conditions and lead to harmonic resonance, special attention should be paid to this optimization problem when harmonics are present. In this paper, a framework based on shuffled frog leaping algorithm (SFLA) is proposed for optimal placement of fixed capacitor banks. Moreover, a resonance index (RI) is proposed for assessment and mitigation of potential harmonic resonance based on resonance mode analysis (RMA). The resonance mitigation method helps in avoiding power quality constraint violations and directs the algorithm toward the feasible solution space. It thus results in a higher efficiency, and the chance of reaching (near) globally optimum solutions increases. The proposed algorithm is particularly useful when detailed data regarding the harmonic injection pattern of nonlinear sources is not available. The proposed framework is implemented on the IEEE 18, 34, and 69‐bus test systems, and the results demonstrate its advantages, especially in larger grids. [ABSTRACT FROM AUTHOR]

The separation of the data capture and analysis in modern vision systems has led to a massive amount of data transfer between the end devices and cloud computers, resulting in long latency, slow response, and high power consumption. Efficient hardware architectures are under focused development to enable Artificial Intelligence (AI) at the resource-limited sensing devices. One of the most promising solutions is to enable Processing-in-Pixel (PIP) scheme. However, the conventional schemes suffer from the low fill-factor issue. This paper proposes a PIP based Complementary Metal-Oxide-Semiconductor (CMOS) sensor architecture, which allows convolution operation before the column readout circuit to significantly reduce the overall power consumption while improving the resource utilization of the succeeding deep learning accelerator. The simulation results show that the proposed architecture could support the computing efficiency up to 3.37 TOPS/W at the 8-bit weight configuration, which is four times as high as the conventional schemes after normalization. The transistors required for each pixel are only 3.5T, significantly improving the fill-factor. [ABSTRACT FROM AUTHOR]

In this paper, an efficient frequency compensation method is investigated for a four-stage CMOS amplifier. The frequency compensation network includes two sets of capacitors at the differential block output. The proposed compensated amplifier is described symbolically to obtain the transfer function. Meanwhile, the proposed configuration is designed at the circuit level and is simulated via 0.18 μ m CMOS technology. Compared to the other existing methods, the proposed amplifier satisfies the figure of merits considerably. This stems from the fact that lower capacitor values are used to perform compensation, leading to lower die occupation, and reach boosted gain bandwidth products. Leveraging both the configuration and design procedure, a high-performance four-stage is presented in this paper. [ABSTRACT FROM AUTHOR]

When a fault occurs on the dc side of the voltage source converter based high voltage direct current (VSC-HVDC) transmission system, the fault current rises quickly due to the low damping of the dc system. Using a dc fault current limiter (DC-FCL) to limit the rise of the fault current can significantly reduce the breaking requirements of the DCCB. A topology of a bidirectional active dc fault current limiter (BA-FCL) based on coupled inductor is proposed in this paper. No expensive full-controlled power electronic devices are used in this topology. Only a few half-controlled power electronic devices are used to achieve active control of the current limiting unit. Compared with many topologies of current limiter at present, the fault current limiting effect of BA-FCL is improved significantly while the cost, volume, topology complexity, and control complexity are reduced. The stress analysis and parameter design of the proposed current limiter are carried out. Finally, the simulation case study and hardware experiment are implemented to verify the good economy and current limiting performance of the proposed topology. [ABSTRACT FROM AUTHOR]

As the weakest components of wind turbine converters, dc-link capacitor withstands high-frequency ripple currents from both rectifier and inverter. Traditional wind turbine control strategy does not consider the influence of the harmonic current generated by both side converters on the dc-link capacitor, and ignores the restriction on the reliability of direct-drive wind turbine converter. For the reason, this paper synthesized the wind turbine model and dc-link capacitor harmonic spectrum analytical approach to derive the connection between mission profile and harmonic spectrum. Regarding with the capacitor lifetime model, the optimal mapping from control strategy to mission profile, maximizing the service life of capacitor, was solved. With the proposed health-oriented control strategy, the core temperature of dc-link capacitor can be effectively reduced, which can increase the service life of capacitor, making the dc-link capacitor no longer the most fragile component in wind turbine converter and ultimately improving the reliability of converters. [ABSTRACT FROM AUTHOR]

As high-speed railways develop rapidly worldwide, the problems of neutral section and power quality are becoming increasingly prominent. These problems affect the normal operation of the power grid and the electric locomotives. The co-phase power supply schemes were proposed by researchers, which can solve these problems well. Among them, the MMC-based scheme (MMC-5 L) is a representative one. The existing scheme, when applied to the auto-transformer (AT)-fed system which is usually adopted by high-speed railways, needs to install an auto-transformer on the output side. To eliminate the auto-transformer and to obtain the more suitable and superior co-phase power supply schemes to AT-fed system, two improved schemes are proposed in this paper based on the novel MMC-based scheme (MMC-6 L) we proposed before. While establishing the mathematical model, creating the control system, and carrying out simulation verification of the proposed schemes, the proposed schemes are compared with MMC-6 L and MMC-5 L in terms of topological characteristics, control system complexity, power loss, and functionality. The results show that while the proposed schemes can fulfill the functions of the co-phase power supply scheme well like the MMC-5 L and MMC-6 L, they are more suitable and superior for the AT-fed system in terms of control system complexity and power loss. Among them, MMC-5L1CB performs best in power loss, and MMC-4L2CB performs best in control system complexity. [ABSTRACT FROM AUTHOR]

This paper presents a photovoltaic (PV) system designed to reduce the DC-link capacitance present in double-stage PV microinverters without increasing the capacitor interfacing the PV source. This solution is based on a modified boost topology, which exhibits continuous current in both input and output ports. Such a characteristic enables the implementation of PV microinverters without electrolytic capacitors, which improves the reliability in comparison with solutions based on classical converters with discontinuous output current and electrolytic capacitors. However, the modified boost converter exhibits different dynamic behavior in comparison with the classical boost converter; thus, design processes and controllers developed for the classical boost converter are not applicable. This paper also introduces a sliding-mode controller designed to ensure the stable operation of the PV microinverter around the maximum power point. Moreover, this solution also rejects the voltage oscillations at double the grid frequency generated by the grid-connection. The global stability of the complete PV system is formally demonstrated using mathematical analyses, and a step-by-step design process for both the power stage and control system is proposed. Finally, the design process is illustrated using a representative application example, and the correct operation of the PV system is validated using realistic circuital simulations. The results validate the accuracy of the theoretical equations proposed for both the design and control of the novel PV system, where errors below 4.5% were obtained for the ripple prediction, and below 1% for the prediction of the dynamic behavior. [ABSTRACT FROM AUTHOR]

In this paper, a 7.75 kHz line rate analog domain time delay integration (TDI) CMOS analog accumulator with 128-stage is proposed. An adaptive compensation for the charge loss due to parasitic effects is adopted. Based on the influence mechanism of parasitic effects, alternately charging the top and bottom plates of the storage capacitor while cooperate positive feedback capacitor dynamically compensates for the charge loss of the sampling phase and the holding phase. Using the proposed circuit, after the post-layout simulation verification, the SNR of 128 stage accumulation can be improved by as much as 20.9 dB. [ABSTRACT FROM AUTHOR]

The paper develops two computationally efficient models, namely a detailed equivalent model and an average-value model, with provisions for representation of the critical state of converter blocking, for modular multilevel converters with embedded storage. These models are indispensable in the simulation of dc faults. The developed detailed equivalent model provides accuracy that matches electromagnetic transient (EMT) simulations, with much reduced computational burden; the developed average-value model represents the averaged behavior of the converter by neglecting switching transients. Both models are extensively evaluated in the context of an HVDC system against benchmark results form a detailed switching model developed in PSCAD/EMTDC. The results confirm the validity and accuracy of the models for steady state, transient, and faulted operating conditions including when the converter is blocked in response to a dc fault. [ABSTRACT FROM AUTHOR]

This paper applies the principles of distribution locational marginal pricing (DLMP) to unbalanced three-phase distribution networks. We first propose a linear model for AC optimal power flow derived through a series of approximation and reformulation techniques. Then a scenario-generation algorithm is proposed to properly model the uncertain parameters in the linear model. Through a proposed No U-Turn sampler (NUTS) based algorithm, probability density functions (PDFs) of DLMPs are calculated. These PDFs provide statistical information about the locational and temporal price risks. By means of applications to two IEEE unbalanced test networks, the numerical results show promising performance for the proposed linear model and the NUTS-based algorithm in creating PDFs of DLMPs. DLMP price densities will be increasingly useful as distribution system operators seek flexible, low risk solutions from embedded generators and aggregators of distributed energy resources. [ABSTRACT FROM AUTHOR]

This paper presents a quantization noise cancellation technique for frequency-to-digital converter-based fractional-$N$ phase-locked loops (FDC-PLLs). The technique cancels quantization noise prior to the loop filter so the PLL bandwidth can be increased without a significant phase noise penalty. The paper also presents an FDC-PLL architecture enhancement that achieves the effect of a charge pump offset current to improve linearity without the extra current source required by previous implementations. [ABSTRACT FROM PUBLISHER]

Recently, voltage-source converter (VSC)-based high-voltage dc (HVDC) transmission systems have gained more attention. In this paper, a control method for a modular VSC-based HVDC transmission system with high-frequency isolation referred to as high-frequency isolated modular converter is proposed. In the high-frequency isolated modular converter configuration, several floating dc capacitors in all three phases are connected in series, and voltage balancing control of these floating dc capacitors is required. In this paper, an appropriate control structure with the capacitor voltage balancing controller is proposed. The proposed control scheme consists of three layers to control terminal dc bus voltage and balance dc capacitor voltages of each building block. Detailed PSCAD simulation results are presented to evaluate the performance of high-frequency isolated modular converter. Controller hardware-in-the-loop simulation of the high-frequency isolated modular converter is also performed by real-time digital simulator (RTDS), and RTDS results are presented to verify the control structure. Finally, laboratory-scale experimental results are presented to validate the proposed control method. [ABSTRACT FROM PUBLISHER]

This paper is concerned with the use of a three-level inverter for a synchronous reluctance machine (SynRM). The SynRM suffers from a poor power factor due to poor machine saliency. This makes it harder to operate the three-level neutral-point-clamped inverter due to a strict requirement to have the two dc-link capacitor voltages balanced. This paper proposes a new nearest three vector modulation algorithm which can balance the two dc-link capacitors even at poor machine saliency ratio (poor power factor). In this paper, a method of sizing the two dc-link capacitors based on the machine power is also proposed. A comparison between two- and three-level inverters was conducted. The SynRM registered lower $d$-axis current ripple with a three-level inverter, indicating lower core losses in the machine. [ABSTRACT FROM PUBLISHER]

In analog designs, the most widely adopted layout practice to improve matching is the symmetrical common-centroid placement. However, this arrangement cannot be obtained in general. In this paper, it is shown that there are asymmetrical placements with a common centroid which are also immune to process gradients and suitable for designs where a symmetrical layout is not possible. In addition, this paper proposes an automated method, based on a standard simulated annealing framework, to arrange fully-integrated capacitors in a layout to improve their matching. [ABSTRACT FROM PUBLISHER]

Risk of arcing in space plasma environment on satellite solar panel has always been an issue of major concern in the aerospace community. The outcome of round robin tests performed in various laboratories has resulted in finalization of the guidelines for the ground test of satellite solar panel coupons (SSPCs). This is documented as ISO-11221 standards. Authenticity of arc plasma flashover (FO) parameters are still under debate. Some experimental findings that support the perimeter theory of arc FO on geostationary (GEO) satellites are discussed in this paper. It has been observed that characteristics of an the arc are dependent on its location on the solar coupon, bias charge (charge due to bias voltage and external capacitance), and the total charge dissipated during the arc discharge. It is also observed that the duration between the two consecutive arcs is directly proportional to the dissipated charge or energy of the latter arc. A combined dielectric consisting of solar cell, adhesive, Kapton, and Carbon Fiber Reinforced Polymer sheet holds charge during irradiation by the electron gun. This resembles surface FO capacitance. Arc energy is governed by the combined effects of a surface flashover capacitor (C-sf) and an external capacitor. It is observed that if intermittent arc duration is sufficiently longer than the gradual accumulation of charge on the SSPC, body may lead to a major arc. This would increase the probability of secondary arcs when the sustained arc environment is experienced by the satellite. To understand primary arcs on dielectrics, an artificial triple junction is prepared and exposed under adverse GEO-like space conditions. Various signatures identified from the arc current and arc neutralization current waveforms specify the behavior of these arcs at different locations on the coupon surface. In this paper, current waveforms of arcs captured on different types of solar panel coupons and their significance are studied. Information about arc energy, arc velocity, and neutralization velocity are extracted from the measured waveforms. [ABSTRACT FROM PUBLISHER]