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The importance of crucial current technical advancements, particularly those centered on the cryptography process such as Cryptographic advanced encryption standard (AES) hardware architectures are gaining momentum with respect to improving the speed and area optimizations. In this paper, we have proposed a novel architecture to implement AES on a reconfigurable hardware i.e., field programmable gate arrays (FPGA). The controller in AES algorithm is responsible to generate the signals to perform operations to generate the 128 bits ciphertext. The proposed controller uses multiplexer and synchronous register-based approach to obtain area and speed efficient on the FPGA hardware. The entire architecture of AES with proposed controller is implemented on Virtex 5, Virtex 6, and Virtex 7series using XilinxISE 14.7 and tested for critical path delay, frequency, slices, efficiency and throughput. It is observed that all the parameters are improved compared to existing architectures achieving the throughput of 32.29, 40.01, and 43.01 Gbps respectively. The key benefit of this approach is the high level of parallelism it displays in a quick and efficient manner. [ABSTRACT FROM AUTHOR]

Nonlinear model predictive control (NMPC) requires a repeated online solution of a nonlinear optimal control problem. The computation load remains the main challenge for the real-time practical application of the NMPC technique, particularly for fast systems. This paper presents a fast NMPC algorithm implemented on a field-programmable gate array (FPGA) that employs a particle swarm optimization (PSO) algorithm to handle nonlinear optimization. The FPGA is used to explore the possibilities of parallel architecture for the substantial acceleration of NMPC. PSO is employed to achieve real-time operation due to its naturally parallel capabilities. The proposed FPGA-based NMPC-PSO controller consists of a random-number generator, a fixed-point arithmetic, a PSO solver, and a universal asynchronous receiver/transmitter communication interface. Then, this controller is applied to an engine idle speed control problem and demonstrated with an FPGA-in-the-loop testbench. The experimental results indicate that the NMPC-on-FPGA-chip strategy has good computational performance and achieves satisfactory control performance. [ABSTRACT FROM AUTHOR]

Automatic detection of road networks from the satellite and aerial images is the most demanded research area, and it is used for various remote sensing applications. The Simplified Gabor Wavelet based approaches are used to extract the road network automatically. In this paper, a field programmable gate array architecture designed for automatic extraction of road network using Simplified Gabor Wavelet is proposed. The hardware implementation results are compared with software implementation results. The performance measures such as completeness, correctness and quality are calculated. In the software implementation, the average value of completeness, correctness, and quality of various images are 91%, 98%, and 89% respectively. In the hardware implementation, the average value of completeness, correctness, and quality are 89%, 97%, and 87% respectively. The performance of the proposed algorithm is also proved in noisy images. These measures prove that the proposed work yields road network very resembling to reference road map. [ABSTRACT FROM AUTHOR]

In order to achieve the requirements of high anti-disturbance and robustness performance for servo system, the acceleration control with disturbance observer is adopted in this paper, where the disturbance observer is used to estimate and compensate the load disturbance. To accomplish the accurate disturbance estimation, higher cut-off frequency of disturbance observer and exact acceleration information are required, where accurate speed estimation is crucial. Thus, a novel velocity acquisition method for servo control system with optical encoder is proposed. At the same time, dynamic error is put forward as a new performance metrics to scientifically explain the dynamic performance of this algorithm. The proposed velocity acquisition method is implemented based on a field programmable gate array. Experimental results show that this novel velocity acquisition method can improve dynamic response performance on the premise of guaranteeing the invariable velocity precision, and at the same time can effectively improve the anti-disturbance and robustness performance of the servo system. [ABSTRACT FROM AUTHOR]

As safety and reliability critical components, lithium-ion batteries always require real-time diagnosis and prognosis. This often involves a large amount of computation, which makes diagnosis and prognosis difficult to implement, especially in embedded or mobile applications. To address this issue, this paper proposes a run-time Reconfigurable Computing (RC) system on Field Programmable Gate Array (FPGA) for Relevance Vector Machine (RVM) to realize real-time Remaining Useful Life (RUL) estimation. The system leverages state-of-the-art run-time dynamic partial reconfiguration technology and customized computing circuits to balance the hardware occupation and computing efficiency. Optimal hardware resource consumption is achieved by partitioning the RVM algorithm according to a multi-objective optimization. Moreover, pipelined and parallel computation circuits for kernel function and matrix inverse are proposed on FPGA to further accelerate the computation. Experimental results with two different battery data sets show that, without sacrificing the RUL prediction performance, the embedded RC platform significantly reduces the computation time and the requirement of hardware resources. This demonstrates that complex prognostic tasks can be implemented and deployed on the proposed system, and it can be extended to the embedded computation of other machine learning algorithms. [ABSTRACT FROM AUTHOR]

Space-Time Adaptive Processing (STAP) can harness the efficacy of interference and clutter significantly. Calculations of the STAP weights involve solving linear equations which require very intensive computations. In this paper, the QR decomposition (QRD) using the modified gram-schmidt (MGS) algorithm is parameterized with vector size to create a trade-off between the hardware resources utilization and computation time. To achieve an efficient floating point structure, the proposed architecture of QRD-MGS algorithm is simulated and implemented in two modes: single-vector and multi-vector. Results show that the multi-vector method can lead to a high-performance design with higher operating frequency, lower power consumption, and less resource utilization than the single-vector method. For example, Modelism simulations show that the decomposition of a 1 2 × 5 1 matrix with vector size of 17 takes 7.86 μ s with the maximum clock frequency of 282 MHz, for implementation on the Arria10 FPGA. In real STAP applications, the matrix sizes are too large to be fit on FPGAs and the update rate of the weights are high. Therefore, this method can fit any matrix in the contemporary FPGAs with an acceptable update rate. [ABSTRACT FROM AUTHOR]

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Tool-path generation is one of the most complex problems in computer-aided manufacturing. Although some efficient strategies have been developed to solve it, most of them are only useful for 3- and 5-axis standard machining. The algorithm called virtual digitising computes the tool path by means of a “virtually digitised” model of the surface and a geometry specification of the tool and its motion, so it can be used even in non-standard machining (retrofitting). This algorithm is simple, robust, and avoids the problem of tool-surface collision. However, its computing cost is high. Presented in the paper there is a virtual digitising optimisation that takes advantage of reconfigurable computing (using field programmable gates arrays) in order to improve the algorithm speed. A comparative study will show the gain and precision achieved. [ABSTRACT FROM AUTHOR]

In recent years, machine vision algorithms have played an influential role as core technologies in several practical applications, such as surveillance, autonomous driving, and object recognition/localization. However, as almost all such algorithms are applicable to clear weather conditions, their performance is severely affected by any atmospheric turbidity. Several image visibility restoration algorithms have been proposed to address this issue, and they have proven to be a highly efficient solution. This paper proposes a novel method to recover clear images from degraded ones. To this end, the proposed algorithm uses a supervised machine learning-based technique to estimate the pixel-wise extinction coefficients of the transmission medium and a novel compensation scheme to rectify the post-dehazing false enlargement of white objects. Also, a corresponding hardware accelerator implemented on a Field Programmable Gate Array chip is in order for facilitating real-time processing, a critical requirement of practical camera-based systems. Experimental results on both synthetic and real image datasets verified the proposed method's superiority over existing benchmark approaches. Furthermore, the hardware synthesis results revealed that the accelerator exhibits a processing rate of nearly 271.67 Mpixel/s, enabling it to process 4K videos at 30.7 frames per second in real time. [ABSTRACT FROM AUTHOR]

An effective System-on-Chip (SoC) for smart Quality-of-Service (QoS) management over a virtual local area network (LAN) is presented in this study. The SoC is implemented by field programmable gate array (FPGA) for accelerating the delivery quality prediction for a service. The quality prediction is carried out by the general regression neural network (GRNN) algorithm based on a time-varying profile consisting of the past delivery records of the service. A novel record replacement algorithm is presented to update the profile, so that the bandwidth usage of the service can be effectively tracked by GRNN. Experimental results show that the SoC provides self-aware QoS management with low computation costs for applications over virtual LAN. [ABSTRACT FROM AUTHOR]

The paper describes the FPGA-based implementation of the modified speeded-up robust features (SURF) algorithm. FPGA was selected for parallel process implementation using VHDL to ensure features extraction in real-time. A sliding 84x84 size window was used to store integral pixels and accelerate Hessian determinant calculation, orientation assignment and descriptor estimation. The local extreme searching was used to find point of interest in 8 scales. The simplified descriptor and orientation vector were calculated in parallel in 6 scales. The algorithm was investigated by tracking marker and drawing a plane or cube. All parts of algorithm worked on 25 MHz clock. The video stream was generated using 60 fps and 640x480 pixel camera. [ABSTRACT FROM AUTHOR]

Abstract: Hardware implementation of Low-Density Parity-Check (LDPC) decoders using conventional algorithms such as Sum-Product or Min-Sum requires large amount of hardware resources. A rather simplistic way to reduce hardware resources is to reduce the intrinsic message quantization. However this adversely affects the bit error rate (BER) performance significantly. In this paper, a resource efficient LDPC decoder based on a reduced complexity Min-Sum algorithm is presented. It reduces the inter-connect complexity by restricting the extrinsic message length to 2 bits and also simplifies the check node operation. Simulation at the algorithmic level shows that the proposed decoder achieves BER performance better than that of a 3-bit Min-Sum decoder, and therefore addresses the problem of massive BER performance degradation of a 2-bit Min-Sum decoder. The reduction in algorithmic complexity and further hardware optimization of the variable node leads to significant savings in hardware resources compared to 3-bit Min-Sum. An LDPC decoder with a code length of 1152 bits has been implemented on a Xilinx FPGA using the proposed algorithmic and hardware enhancements. With a 0.1dB BER performance gain to that of 3-bit Min-Sum decoder, the proposed decoder saves about 18% of FPGA slices and provides a higher throughput. [Copyright &y& Elsevier]