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This paper deals with the study of technologies for flip-chip assembly of CMOS integrated power converters on standard FR4 organic substrates. Tests for the characterization of commercially available technologies for microassemblies, such as anisotropic adhesive bonding, thermocompression bonding, thermosonic/ultrasonic bonding, and solder bonding, are carried out. The aim of this paper is to determine the most suitable flip-chip bonding technology for power CMOS circuits with more than 50 pads. First, the coupled design of the CMOS chip and the corresponding substrate dedicated to low-power microconversion (10 W) is presented. It is shown that the parasitic resistances and inductances of the interconnections increase the conduction and switching losses of the device. This leads to a temperature rise, which can limit the operating ratings of the circuit. The experimental results are provided to evaluate each technology for flip-chip assembly. [ABSTRACT FROM PUBLISHER]

This paper deals with the design and the realization of an integrated isolated HF dc-to-dc converter for low-voltage and low-power conditioning applications (3.3 V and 1 W) including galvanic isolation. It is based on the 3-D integration of several elementary silicon dies in which essential components such as the inverter, the rectifier, the HF transformer, the input and output capacitors, and the output inductor have been integrated. The paper deals with the silicon integration of all these elements, with the presentation of our work being related with the state of the art. Then, it focuses on an estimate of the whole converter functional performance at 1-MHz switching frequency. Practical but partial implementation was carried out. The inverter and the rectifier are designed in CMOS technology (Austria Micro Systems 0.35 \mu\m) and have been optimized to operate at HF (1 MHz) to reduce the size of passive devices. We have monolithically integrated all that is necessary for this function. The transformer, as well as the inductor and the capacitors, is also integrated on separate silicon dies. Their integration is discussed, as well as their design and practical characterization. Based on a distributed construction, the overall converter efficiency is estimated in simulation based on practical characterizations. It appears that correct efficiency with a reasonable silicon surface and volume can be reached. [ABSTRACT FROM PUBLISHER]