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In this paper, a new structure for a 1-bit full adder is proposed based on dynamic logic methodology, which utilises pass transistors. The clocking operation falls into two phases. The clocking operation consists of a pre-discharged cycle, during which pseudo capacitors are reset to zero when the clock signal is high, and an evaluation cycle, during which the circuit outputs the adder function when the clock signal is low. The circuit uses a combination of 12 pass-transistors to better implement the full adder logic function with the maximum of a NMOS threshold voltage drop. Moreover, the circuit has no direct connection to the power-supply node and so this can possibly save the power dissipation. Our new adder outperforms other 1-bit full adder structures in terms of power-delay factor, according to simulation results. [ABSTRACT FROM AUTHOR]

The Internet of Things (IoT) and blockchain are emerging technologies that have attracted attention in many industries, including healthcare, automotive, and supply chain. IoT networks and devices are typically low-powered and susceptible to cyber intrusions. However, blockchains hold considerable potential for securing low-power IoT networks. Blockchain networks provide security features such as encryption, decentralisation, time stamps, and ledger functions. The integration of blockchain and IoT technologies may address many of the security concerns. However, integrating blockchain with IoT raises several issues, including the security vulnerabilities and anomalies of blockchain-based IoT networks. In this paper, we report on our experiments using our blockchain test bed to demonstrate that blockchains on IoT platforms are vulnerable to DDoS attacks, which can also potentially lead to device hardware failures. We show that a number of anomalies are visible during either a DDoS attack or IoT device failure. In particular, the temperature of IoT hardware devices can exceed 90 °C during a DDoS attack, which could lead to hardware failure and potential fire hazards. We also found that the Block Transaction Rate (BTR) and network block loss percentage can increase due to corrupted hardware, with the BTR dropping to nearly zero blocks/sec and a block loss percentage of over 50 percent for all evaluated blockchains, and as high as 81.3 percent in one case. Our experiments demonstrate that anomalous temperature, latency, bandwidth, BTR, and network block loss percentage can potentially be used to identify DDoS attacks. [ABSTRACT FROM AUTHOR]

Edge computing enables prompt responses in IoT environments, such as the operation of autonomous vehicles and unmanned aerial vehicles. However, with the increase in sensor nodes, the computational burden on the computing node also increases. Specifically, data filtering and reduction at application nodes add to the energy burden for battery-operated devices. In this paper, we propose a preprocessing system at the application node that requires low power consumption for data transmission reduction. Based on our simulations, we identify the minimum data size needed to preserve the signal. We first design the preprocessing system using a hardware description language to evaluate its performance. Then, we implement the open-library-based MCU system, including the proposed preprocessing IP, to assess its operation and overhead. Our implementation of the preprocessing system reduces data transmission by 50% with acceptable information loss. Additionally, the area and power consumption after the logic synthesis of the preprocessing IP within the entire MCU system are evaluated at only 3.6% and 13.1%, respectively. By performing preprocessing using the MCU and proposed IP, nearly 74.4% power reduction is achieved compared to using the existing MCU core. [ABSTRACT FROM AUTHOR]

Brain-inspired flexible neuromorphic devices are of great significance for next-generation high-efficiency wearable sensing and computing systems. In this paper, we propose a flexible organic electrochemical transistor using poly[(bithiophene)-alternate-(2,5-di(2-octyldodecyl)- 3,6-di(thienyl)-pyrrolyl pyrrolidone)] (DPPT-TT) as the organic semiconductor and poly(methyl methacrylate) (PMMA)/LiClO4 solid-state electrolyte as the gate dielectric layer. Under gate voltage modulation, an electric double layer (EDL) forms between the dielectric layer and the channel, allowing the device to operate at low voltages. Furthermore, by leveraging the double layer effect and electrochemical doping within the device, we successfully mimic various synaptic behaviors, including excitatory post-synaptic currents (EPSC), paired-pulse facilitation (PPF), high-pass filtering characteristics, transitions from short-term plasticity (STP) to long-term plasticity (LTP), and demonstrate its image recognition and storage capabilities in a 3 × 3 array. Importantly, the device's electrical performance remains stable even after bending, achieving ultra-low-power consumption of 2.08 fJ per synaptic event at −0.001 V. This research may contribute to the development of ultra-low-power neuromorphic computing, biomimetic robotics, and artificial intelligence. [ABSTRACT FROM AUTHOR]

Bluetooth Low Energy Mesh (BLE Mesh) enables Bluetooth flexibility and coverage by introducing Low-Power Nodes (LPNs) and enhanced networking protocol. It is also a commonly used communication method in sensor networks. In BLE Mesh, LPNs are periodically woken to exchange messages in a stop-and-wait way, where the tradeoff between energy and efficiency is a hard problem. Related works have reduced the energy consumption of LPNs mainly in the direction of changing the bearer layer, improving time synchronization and broadcast channel utilization. These algorithms improve communication efficiency; however, they cause energy loss, especially for the LPNs. In this paper, we propose a constrained flooding algorithm based on time series prediction and lightweight GBN (Go-Back-N). On the one hand, the wake-up cycle of the LPNs is determined by the time series prediction of the surrounding load. On the other, LPNs exchange messages through lightweight GBN, which improves the window and ACK mechanisms. Simulation results validate the effectiveness of the Time series Prediction and LlightWeight GBN (TP-LW) algorithm in energy consumption and throughput. Compared with the original algorithm of BLE Mesh, when fewer packets are transmitted, the throughput is increased by 214.71%, and the energy consumption is reduced by 65.14%. [ABSTRACT FROM AUTHOR]

Although CNN shows high performance in the image recognition field, it has great disadvantages. They are to take a long time to perform machine learning due to a lack of system resources, and to consume a lot of power due to the great volume of computation. A convolution layer is a key element of convolutional neural network processing. This paper presents a convolution layer hardware using processing elements with a low-power multiplier. The low-power multiplier reduces the switching activity by increasing the exchange rate between the multiplier and multiplicand. The proposed convolution layer hardware was implemented on the Intel DE1-SoC FPGA Board using Verilog-HDL. The performance was verified by comparing the exchange rate with the existing multipliers when performing multiplications to process convolutional operations for the MNIST image database. [ABSTRACT FROM AUTHOR]

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Modern processors often face challenges when handling instructions that overwhelm the branch target buffer (BTB), leading to front-end bottlenecks. As the BTB's capacity increases, its prediction module can become slower and power-hungry. In this paper, we introduce a straightforward yet highly effective two-level prediction mechanism to mitigate the escalating power consumption in the BTB structure, achieved by reducing the number of accesses. Our approach incorporates two main elements: M-BTB and V-BTB. M-BTB encompasses the first-level prediction mechanism and a fully associative BTB, while V-BTB houses the second-level prediction mechanism and a set-associative BTB. To implement our prediction mechanism, we optimize the traditional two-level BTB structure. The first level employs the skew mechanism, and the second level dissects the tag bits to create the Partial tag. These two levels of prediction mechanism correspond to the bank/way prediction for the two-level BTB structure. Our experimental results show that the first-stage prediction mechanism reduces M-BTB accesses by 75%, while the second-stage prediction mechanism ensures that over 98% of addresses require just zero or one way of the V-BTB to achieve a hit result. Our proposed approach achieves a remarkable 86–97% reduction in power consumption, with a minimal impact on performance and an increase in overall area efficiency. [ABSTRACT FROM AUTHOR]

In this paper, we present an analysis of an operational trans-conductance amplifier (OTA) with two positive feedback. The direct current (DC) transfer function is obtained by analyzing the OTA using the drain current in the weak inversion region. The analysis results were verified through comparison with SPICE simulations, and the characteristics of the DC transfer function analysis for the OTA design are well matched with the simulation results. The designed OTA dissipates a low power of 41.4 nW, and features the slew rate is improved by 436% compared to a conventional OTA without two positive feedback. Additionally, a DC gain and a unity-gain bandwidth is improved by 36 dB and 6.7 times, respectively. The OTAs are designed for the 0.18 µm complementary metal-oxide-semiconductor (CMOS) process. [ABSTRACT FROM AUTHOR]

This paper proposes a novel analog front end to filter edges in captured images. The proposed architecture employs the Sobel algorithm and uses a 3 × 3 kernel to process the input images. We used 180 nm Semi-Conductor Laboratory (SCL) CMOS fabrication technology for implementation with a power supply of 1.8 V. The proposed design employs six analog differential pairs in each horizontal and vertical gradient unit. The inputs to the differential pairs are the active signals fed from the 3 × 3 kernel using the Sobel weight masks. We connected the differential datum pairs in cascade to estimate the gradient index in horizontal/vertical direction using the net difference current between the output terminals. The horizontal and vertical gradient units, viz., G H and G V , respectively, are configured based on the polarity of weights in respective Sobel masks. The gradient (G) of the processing pixel (PP) is estimated using the net difference current in the combined circuitry employing G H and G V cells. The key advantages of the proposed design are very low area realization, high accuracy, and low power dissipation. The efficacy of the proposed edge filter analog front end is estimated through simulations and analysis with two sets of test signals in the processing window. [ABSTRACT FROM AUTHOR]

Summary This paper introduces an area‐effective and low‐power readout circuit structure tailored for high dynamic range (HDR) CMOS image sensors (CISs) utilizing dual conversion gain (DCG) imaging technology. A switched capacitor amplifier, which is applied at the comparator input port of the column‐parallel single‐slope analog‐to‐digital converter (SS ADC), is proposed to compensate for the charge injection and clock feed‐through introduced when the pixel switches between high conversion gain (HCG) and low conversion gain (LCG) modes. The proposed SS ADC is supplemented by the integration of a configurable counter, and the counter is specifically crafted for performing the A/D conversion of the readout voltage within a DCG pixel. Compared to the conventional DCG readout circuit, the proposed readout circuit use only one ADC for A/D conversion of HCG signals and LCG signals, which greatly reduces the area and power consumption of the readout circuit. Simulation results under 110 nm CMOS technology illustrate that the proposed 10‐bit SS ADC has a DNL of +0.78/−0.91 LSB and an INL of +1.91/−1.69 LSB, with a SNR of 57.2 dB and a SNDR of 55.95 dB, corresponding to an ENOB of 9 bits. The power consumption of the proposed SS ADC is 56.4 μW per column with a conversion time of 12 μs, and the simulation results show that the power consumption is 23.35% lower than the conventional structure and the area is saved by 24.69%. [ABSTRACT FROM AUTHOR]

IoT and wearable medical devices frequently require ultra-low power solutions that can support long spells of inactivity. This study presents a buck converter to control power stages using a novel pulse frequency modulation (PFM) system that reduces switching losses for low-power systems. The modulation of high and low-frequencies was demonstrated, where the high-frequencies exhibited better energy transformation between the inductor and capacitor, and the low-frequencies could be adjusted for different current loads, to reduce switching losses. This circuit is optimized for light load applications. Using voltage control oscillation (VCO), the frequency range of 0.5 MHz – 2.0 MHz can be adjusted to influence conversion efficiency for different loads. The design was simulated and then fabricated using TSMC 0.18um process. The core size was about 1500 × 1000um that includes power MOS. Measurements result an average conversion efficiency of 91% under a load of 0.1 mA – 10 mA. This chip is suitable for battery-based IoT systems, or wearable medical devices. [ABSTRACT FROM AUTHOR]

This paper proposed a 12-bit 2.5-bit/phase two-stage cyclic Analog-to-Digital Converter (ADC) with phase scaling and low-power Sub-ADC for CMOS image sensors. The phase scaling technique reduces the performance requirements of operational amplifiers for the cyclic ADC. Furthermore, the Sub-ADC architecture based on tri-state comparators reduces the power consumption of the Sub-ADC. The implemented cyclic ADC is designed with 110 nm process. Simulation results demonstrate that the proposed 12-bit, 1 MS/s, 2.5-bit/phase, two-stage cyclic ADC achieves an effective number of bits (ENOB) of 11.4-bit with a power consumption of 0.185 mW per column. Compared with the traditional fixed phase structure, the power consumption of the phase scaling structure is reduced by 22.3 %. Additionally, the cyclic ADC attains a Figure of Merit (FoM) of 68.5fJ/step. [ABSTRACT FROM AUTHOR]

This paper presents a power-efficient CMOS image sensor (CIS) for always-on object detection by using 1-bit log-gradient feature extraction in analog current domain. Compared with traditional image sensors with high-resolution ADCs, the proposed CIS extracts gradients in ratio form and generates feature maps at 1-bit resolution, which eliminates unnecessary background information and illumination-related data, and reduces the data computation in the later detector. The system containing the proposed CIS and back-end ANN detector is modeled with python and the simulation achieves an accuracy of 93.2 % for person detection. The CIS employs current mode divider and comparator to compute the gradient ratios. An accurate and configurable muti-input and muti-output (MIMO) current divider is proposed, composed of two cascaded modified second generation current controlled conveyors (M-CCCIIs). The proposed CIS was fabricated in a 0.18 μm standard CMOS process and realized a frame rate of 170 fps and an energy efficiency of 337 pJ/pixel in a power consumption of 1.1 mW. Experimental results show that the proposed CIS can realize the function of extracting log-gradients. [ABSTRACT FROM AUTHOR]

【Objective】In this paper, an ultra-low power consumption optical transmitter is developed to broaden the application of optical communication in short-reach interconnection such as board level and backplane level. The basic principle of the scheme is that the Vertical-Cavity Surface-Emitting Laser (VCSEL) laser generates an optical pulse signal after loading a bias current and a modulation signal through a Bias-T circuit.【Methods】In this work, the feasibility of the scheme is verified by means of simulation. It is also found that the main factors affecting the increase of the transmission rate are the parasitic parameters of the laser device and the impedance matching of the drive circuit. The two electrical transmission distances of 200 and 10 mm are studied by experiments. And the law of eye diagram quality and bit error rate as a function of driving voltage and bias current is studied through experiments under two electrical transmission distances.【Results】The results show that a larger effective extinction ratio ranging from 0.84 to 6.69 dB can be obtained by shortening the electrical transmission distance to 10 mm with the minimum differential driving voltage of 200 mV, the minimum bias current of 15 mA, and the power consumption of 1.2 mW/Gbit/s. Compared with traditional optical modules, the power consumption of optical transmission is reduced by about 80%.【Conclusion】This optical transmitter solution can be applied to intra-data center. Combined with low-power optical receivers, the overall power consumption of the data center can be significantly reduced.

This paper proposes a 4th-order class-AB low-pass filter (LPF) for wearable biological healthcare applications designed by cascading two 2nd-order LPFs. The proposed class-AB LPF uses quasi-floating gate (QFG), flipped source follower (FSF) and level-shifter (LS) techniques to boost its performance. The LPF is designed and validated in CMOS 180 nm technology which emulates the post-layout gain of −0.212 dB, bandwidth of 100 Hz, dynamic range (DR) of 50.26 dB, total harmonic distortion (THD) of −52.5 dB and figure of merit (FOM) of 1.71 × 10-15 J. The class-AB QFG FSF LPF consumes power and area of 0.224 nW and 0.0196 mm2, respectively. Furthermore, the statistically determined coefficient of variation for proposed LPF with 1000 iterations for gain is −0.035, THD is −0.172 and DR is 0.04, respectively. The class-AB QFG FSF LPF is compared with other LPFs which establishes its advantage in terms of low-power consumption and least figure of merit thus confirming its suitability for wearable healthcare applications. [ABSTRACT FROM AUTHOR]

This paper presents a 10 bits low-power direct digital IF to RF digital-to-analog (RF-DAC) fabricated in a 110 nm CMOS technology with a core area of 0.08 mm 2. The DAC uses sixteen current mode double balanced mixers designed without a tail transistor with different weights to convert IF output to RF output. The digital IF signal is modulated by a digital Σ − Δ modulator with 1-bit IF output. The RF-DAC with a bandwidth of 300 KHz consumes 17.3 mA from a 1.5 V supply. [ABSTRACT FROM AUTHOR]

This article presents the design of a low-power low noise amplifier (LNA) implemented in 45 nm silicon-on-insulator (SOI) technology using the g m / I D methodology. The Ka-band LNA achieves a very low power consumption of only 1.98 mW andis the first time the g m / I D approach is applied at such a high frequency. The circuit is suitable for Ka-band applications with a central frequency of 28 GHz, as the circuit is intended to operate in the n257 frequency band defined by the 3GPP 5G new radio (NR) specification. The proposed cascode LNA uses the g m / I D methodology in an RF/MW scenario to exploit the advantages of moderate inversion region operation. The circuit occupies a total area of 1.23 mm2 excluding pads and draws 1.98 mW from a DC supply of 0.9 V. Post-layout simulation results reveal a total gain of 11.4 dB, a noise figure (NF) of 3.8 dB, and an input return loss (IRL) better than 12 dB. Compared to conventional circuits, this design obtains a remarkable figure of merit (FoM) as the LNA reports a gain and NF in line with other approaches with very low power consumption. [ABSTRACT FROM AUTHOR]

Peripheral nerve injuries pose significant health challenges leading to loss of motor control and sensation. These injuries can result from trauma, surgery, tumors, and neurological disorders. Peripheral nerve injuries mainly lead to paralysis such as facial paralysis. Patients with facial paralysis often face loss of facial expression control affecting their quality of life. Research studies have explored peripheral nerve recording to address these challenges, aiming to understand nerve impulses and develop effective neural interfaces for functional restoration. Neural amplifier chips characterized by low noise, high gain, and small size have been integrated with nerve cuff electrodes to capture neural signals efficiently. This paper reviews the applications of cuff electrodes simulating the facial nerve for facial muscle contractions and various neural recording system architectures interfaced with a peripheral nerve cuff electrode. Diverse types of cuff electrodes and their configuration have been drawn pointing out their advantages and limitations. Neural amplifier topologies susceptible to neural recording are outlined with their main characteristics including noise, speed, and power consumption relative to their general architectures.

This paper presents a static sequential-random-access memory (S2RAM) designed to enable low-power and high-performance operations for workloads involving sequential memory accesses. Considering the address configuration and internal operation of column-interleaved SRAM, we propose an optimized memory structure and peripheral circuitry that can exploit access patterns as opportunities for low-cost operation. In the proposed S2RAM, word-line (WL) activation is restricted by using bit-line (BL) as temporary storage in case of memory access in which only column addresses are sequentially changed. In order to prevent the BL leakage-induced data corruption, a BL clamper is also proposed. The optimized design method of the controller and assist scheme for using reconfigurable access modes in the proposed S2RAM is also presented. The proposed 16Kb S2RAM macro has been implemented using a 28nm CMOS technology. Numerical results show that the proposed S2RAM saves up to 76% of operating energy compared to conventional SRAM at the cost of 8% increased area.

Modern battery-enabled systems, such as IoT, require SRAM cells that can maintain data and respond quickly to requests. However, achieving low-power and stable SRAM cells, which are essential for IoT systems, is not possible with CMOS technology due to scaling issues. As a result, new nanoscale devices, such as FinFET, have been introduced as a potential replacement for CMOS in SRAM design. This paper presents a new FinFET-based 8 T SRAM cell with separate reading and writing paths. The cell uses read-decoupling and write-assist pull-down path cut techniques to improve read stability and writability, respectively. Single-ended reading and writing structures reduce power consumption, and stacking transistors, along with read bitline leakage elimination, reduces leakage power dissipation. The proposed cell's efficiency is evaluated using HSPICE simulator with 10-nm FinFET technology and is compared with conventional 6 T, single-bitline 7 T (SB7T), single-ended 8 T (SE8T), and transmission gate read-decoupled 9 T (TRD9T) SRAM cells at V DD = 0.35 V. The proposed cell improves read stability by 2.59×/1.04 × and enhances writability by 1.38×/1.01 × compared to 6 T/TRD9T and 6 T/SB7T, respectively. It also reduces read power by 28.25 %/19.60 % compared to the 6 T/SB7T and reduces write power by at most 33.40 % and at least 5.46 %. Moreover, the leakage power is reduced by at least 5.80 %. However, the proposed cell increases read/write delay by 1.77×/1.40 × and shows 1.23 × larger layout area compared to 6 T. [ABSTRACT FROM AUTHOR]

In this paper, a high current efficiency two-stage amplifier using multipath nested feedforward compensation (MNFC) method is proposed. For the purpose of achieving the high current efficiency, the first stage of the amplifier uses a recycling folded cascode amplifier (RFC) and a nested small-gain stage is added between the two stages of the amplifier so that there are two paths in the feedforward path. This two-stage amplifier improves the phase margin (PM) and extends the gain bandwidth (GBW) by using the MNFC technique which can eliminate the non-dominant pole. The chip area of this two-stage MNFC amplifier which using 0. 18 μ m CMOS process is 0.01272 mm 2. The simulated and measured results shows that the phase margin(PM), DC gain, gain-bandwidth(GBW), average 1% settling time, slew rate- (SR-) and slew rate+ (SR+) is 72.7°, 104.4 dB, 4.29 MHz, 246.2 ns, 16 V/ μ s , and 6.15 V/ μ s , respectively, when the load capacitance is 120 pF. The supply voltage of this circuit is 1.8 V and the power consumption is 0.13 mW. • This multipath nested feedforward compensation (MNFC) method has higher current efficiency. • The frequency compensation effect is better than that of traditional feedforward compensation methods. • The gain-bandwidth is extended and the phase margin is improved. [ABSTRACT FROM AUTHOR]

Implantable neuromodulation devices have significantly advanced treatments for neurological disorders such as Parkinson's disease, epilepsy, and depression. Traditional open-loop devices like deep brain stimulation (DBS) and spinal cord stimulators (SCS) often lead to overstimulation and lack adaptive precision, raising safety and side-effect concerns. Next-generation closed-loop systems offer real-time monitoring and on-device diagnostics for responsive stimulation, presenting a significant advancement for treating a range of brain diseases. However, the high false alarm rates of current closed-loop technologies limit their efficacy and increase energy consumption due to unnecessary stimulations. In this study, we introduce an artificial intelligence-integrated circuit co-design that targets these issues and using an online demonstration system for closedloop seizure prediction to showcase its effectiveness. Firstly, two neural network models are obtained with neural-network search and quantization strategies. A binary neural network is optimized for minimal computation with high sensitivity and a convolutional neural network with a false alarm rate as low as 0.1/h for false alarm rejection. Then, a dedicated low-power processor is fabricated in 55 nm technology to implement the two models. With reconfigurable design and event-driven processing feature the resulting application-specific integrated circuit (ASIC) occupies only 5mm2 silicon area and the average power consumption is 142 µW. The proposed solution achieves a significant reduction in both false alarm rates and power consumption when benchmarked against state-of-the-art counterparts. [ABSTRACT FROM AUTHOR]

Multiplication is a fundamental arithmetic operation in electronic processing units such as microprocessors and digital signal processors as it plays an important role in various computational tasks and applications. There exist many designs of synchronous multipliers in the literature. However, in the domain of Input–Output Mode (IOM) asynchronous design, there is relatively less published research on multipliers. Some existing works have considered quasi-delay-insensitive (QDI) asynchronous implementations of multipliers. However, the QDI asynchronous design paradigm, in general, is not area- and speed-efficient. This article presents an efficient alternative implementation of IOM asynchronous multipliers based on the concept of monotonic Boolean networks. The array multiplier architecture has been considered for demonstrating the usefulness of our proposition. The building blocks of the multiplier, such as the partial product generator, half adder, and full adder, were implemented monotonically. The popular dual-rail encoding scheme was considered for encoding the multiplier inputs and outputs, and four-phase return-to-zero handshaking (RZH) and return-to-one handshaking (ROH) were separately considered for communication. Compared to the best of the existing QDI asynchronous array multipliers, the proposed monotonic asynchronous array multiplier achieves the following reductions in design metrics: (i) a 40.1% (44.3%) reduction in cycle time (which is the asynchronous equivalent of synchronous clock timing), a 37.7% (37.7%) reduction in area, and a 4% (4.5%) reduction in power for 4 × 4 multiplication corresponding to RZH (ROH), and (ii) a 58.1% (60.2%) reduction in cycle time, a 45.2% (45.2%) reduction in area, and a 10.3% (11%) reduction in power for 8 × 8 multiplication corresponding to RZH (ROH). The multipliers were implemented using a 28 nm CMOS process technology. [ABSTRACT FROM AUTHOR]

Implantable microelectrodes arrays are used to record electrical signals from surrounding neurons and have led to incredible improvements in modern neuroscience research. Digital signals resulting from conditioning and the analog-to-digital conversion of neural spikes captured by microelectrodes arrays have to be elaborated in a dedicated DSP core devoted to a real-time spike-sorting process for the classification phase based on the source neurons from which they were emitted. On-chip spike-sorting is also essential to achieve enough data reduction to allow for wireless transmission within the power constraints imposed on implantable devices. The design of such integrated circuits must meet stringent constraints related to ultra-low power density and the minimum silicon area, as well as several application requirements. The aim of this work is to present real-time hardware architecture able to perform all the spike-sorting tasks on chip while satisfying the aforementioned stringent requirements related to this type of application. The proposed solution has been coded in VHDL language and simulated in the Cadence Xcelium tool to verify the functional behavior of the digital processing chain. Then, a synthesis and place and route flow has been carried out to implement the proposed architecture in both a 130 nm and a FD-SOI 28 nm CMOS process, with a 200 MHz clock frequency target. Post-layout simulations in the Cadence Xcelium tool confirmed the proper operation up to a 200 MHz clock frequency. The area occupation and power consumption of the proposed detection and clustering module are 0.2659 mm2/ch, 7.16 μW/ch, 0.0168 mm2/ch, and 0.47 μW/ch for the 130 nm and 28 nm implementation, respectively. [ABSTRACT FROM AUTHOR]

Static random access memory (SRAM) is a sort of RAM where information is not permanently stored and does not require routine updating. To reduce leakage power without sacrificing performance, a variety of approaches have been applied to SRAM cells. In this study, we suggest a new 16T SRAM design that can function in active, park, standby, or hold modes. A fully static mode of operation for SRAM is made possible by the 16T SRAM structure, which also enhances write margin (WM) and removes charging conflict between devices during read and write operations. The key objectives of the suggested architecture are to retain logic state in park mode while maintaining stability and reducing standby time in active mode, as well as to reduce leakage current in standby mode. This is done by removing feedback from the back-to-back inverters during write operations via the data-dependent supply block. This makes it possible for the suggested bitcell to considerably increase the WM. A novel SRAM cell with 16 transistors is created with subthreshold operation and enhanced data stability. By using an equalized bit line technique to avoid leakage due to enhanced data pattern and RBL detection, the suggested single-ended SRAM cell with dynamic feedback control lowers the static noise margin for ultra-low power transfer. A sleep transistor is incorporated into the architecture to save power consumption when the system is in standby mode due to inefficient voltage transmission. Tanner EDA tool V.14.1 on 45-nm CMOS was used for design and simulation. The outcomes demonstrate a considerable decrease in no-load current and power loss. [ABSTRACT FROM AUTHOR]

This article describes a low-voltage, low-power fractional-order low-pass filter (FO-LPF) of order 1 + α, which is implemented using a voltage differencing differential difference amplifier (VDDDA). The VDDDA structure is implemented using the bulk-driven metal oxide semiconductor transistor technique. The transistors operate in the subthreshold region to maintain low-supply voltage and low-power consumption. The FO-LPF structure implemented using this VDDDA structure is compact. It includes three VDDDAs and three grounded capacitors along with two active resistors implemented using MOS transistors. In addition, this filter structure provides electronic tuning of its order and cut-off frequency through the bias current of the active component used. The effects of tracking error and parasitics on the functionality of the proposed FO-LPF were investigated. The VDDDA and filter operate at ±300 mV and dissipate only 207 nW and 663 nW of power, respectively. Thus, the VDDDA structure and filter are suitable for low-voltage and low-power operation. Layouts of the proposed VDDDA as well as the FO-LPF were designed in the Cadence Virtuoso environment. Post-layout simulation results of the designed circuits imply that they are suitable for fabrication. Noise, total harmonic distortion, Monte-Carlo, and PVT analyses were also performed. [ABSTRACT FROM AUTHOR]

Brain-inspired flexible neuromorphic devices are of great significance for next-generation high-efficiency wearable sensing and computing systems. In this paper, we propose a flexible organic electrochemical transistor using poly[(bithiophene)-alternate-(2,5-di(2-octyldodecyl)- 3,6-di(thienyl)-pyrrolyl pyrrolidone)] (DPPT-TT) as the organic semiconductor and poly(methyl methacrylate) (PMMA)/LiClO4 solid-state electrolyte as the gate dielectric layer. Under gate voltage modulation, an electric double layer (EDL) forms between the dielectric layer and the channel, allowing the device to operate at low voltages. Furthermore, by leveraging the double layer effect and electrochemical doping within the device, we successfully mimic various synaptic behaviors, including excitatory post-synaptic currents (EPSC), paired-pulse facilitation (PPF), high-pass filtering characteristics, transitions from short-term plasticity (STP) to long-term plasticity (LTP), and demonstrate its image recognition and storage capabilities in a 3 × 3 array. Importantly, the device’s electrical performance remains stable even after bending, achieving ultra-low-power consumption of 2.08 fJ per synaptic event at −0.001 V. This research may contribute to the development of ultra-low-power neuromorphic computing, biomimetic robotics, and artificial intelligence.

Bluetooth Low Energy Mesh (BLE Mesh) enables Bluetooth flexibility and coverage by introducing Low-Power Nodes (LPNs) and enhanced networking protocol. It is also a commonly used communication method in sensor networks. In BLE Mesh, LPNs are periodically woken to exchange messages in a stop-and-wait way, where the tradeoff between energy and efficiency is a hard problem. Related works have reduced the energy consumption of LPNs mainly in the direction of changing the bearer layer, improving time synchronization and broadcast channel utilization. These algorithms improve communication efficiency; however, they cause energy loss, especially for the LPNs. In this paper, we propose a constrained flooding algorithm based on time series prediction and lightweight GBN (Go-Back-N). On the one hand, the wake-up cycle of the LPNs is determined by the time series prediction of the surrounding load. On the other, LPNs exchange messages through lightweight GBN, which improves the window and ACK mechanisms. Simulation results validate the effectiveness of the Time series Prediction and LlightWeight GBN (TP-LW) algorithm in energy consumption and throughput. Compared with the original algorithm of BLE Mesh, when fewer packets are transmitted, the throughput is increased by 214.71%, and the energy consumption is reduced by 65.14%.

The Internet of Things (IoT) and blockchain are emerging technologies that have attracted attention in many industries, including healthcare, automotive, and supply chain. IoT networks and devices are typically low-powered and susceptible to cyber intrusions. However, blockchains hold considerable potential for securing low-power IoT networks. Blockchain networks provide security features such as encryption, decentralisation, time stamps, and ledger functions. The integration of blockchain and IoT technologies may address many of the security concerns. However, integrating blockchain with IoT raises several issues, including the security vulnerabilities and anomalies of blockchain-based IoT networks. In this paper, we report on our experiments using our blockchain test bed to demonstrate that blockchains on IoT platforms are vulnerable to DDoS attacks, which can also potentially lead to device hardware failures. We show that a number of anomalies are visible during either a DDoS attack or IoT device failure. In particular, the temperature of IoT hardware devices can exceed 90 °C during a DDoS attack, which could lead to hardware failure and potential fire hazards. We also found that the Block Transaction Rate (BTR) and network block loss percentage can increase due to corrupted hardware, with the BTR dropping to nearly zero blocks/sec and a block loss percentage of over 50 percent for all evaluated blockchains, and as high as 81.3 percent in one case. Our experiments demonstrate that anomalous temperature, latency, bandwidth, BTR, and network block loss percentage can potentially be used to identify DDoS attacks.

A novel LTPS‐based compensation circuit is adopted to reduce the power consumption, which is reduced by 16.63% due to the special design is set to reduce the source‐drain voltage (Vds) of the DTFT. Furthermore, some signals are simultaneously set for the entire panel to eliminate color shift and screen tearing problems. The novel circuit is suitable for MLED splicing display products which have less power consumption and can generate high‐quality images with excellent gamma curves. [ABSTRACT FROM AUTHOR]

In this study, the periodic nanostructures of various shapes were fabricated using a low‐cost, low‐power continuous wave laser. The nanostructures can be easily fabricated with a low‐cost and simple process using a laser interference lithography technology. In addition, we demonstrated that various shapes such as spherical, hemispherical, and wavy can be easily controlled by adjusting the surface energy of the substrate and process parameters. [ABSTRACT FROM AUTHOR]