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This article proposes a methodology for critical path selection and delay sensor insertion for aging monitoring in field-programmable gate arrays (FPGAs). The aging information can be used to reconfigure FPGAs to achieve better performance or wear leveling. To filter out the paths aging less aggressively, our methodology decides based on both physical-level parameters [e.g., path delay, process variation, temperature, static stress (duty cycle), and dynamic stress (switching activity) as well as aging-relevant parameters (e.g., fan-out, and endpoint physical location)]. After selection of an optimal set of paths, age sensors, introduced in our earlier work, are placed in a distributed fashion throughout the FPGA area to provide aging information of its various parts as they are being used. Accurate aging models for FPGAs are required to determine the contribution of the above-mentioned parameters in aging. In this article, ASICs’ aging models are adapted for FPGAs through measurement-based fitting approach. The experimental results using various benchmarks reveal that our algorithm selects paths with a minimum error. [ABSTRACT FROM AUTHOR]

In this article, we propose a fine-grained FPGA aging mitigation method. Our method focuses on Look Up Tables (LUTs) on which Boolean functions are mapped. Based on our observations, for any configuration, even if it is carefully selected, a number of LUT transistors experience severe stress rates. Therefore, an algorithm is presented to select several alternative configurations for each LUT. Alternative configurations are obtained by LUT input reordering. These alternative configurations are rotationally loaded into the FPGA. Experimental results shows that our method achieves 263 and 14.1 percent Mean Time To Failure (MTTF) improvement for Hot Carrier Injection (HCI) and Bias Temperature Instability (BTI), respectively. Additionally, due to changing only local routings, our method imposes up to 1 percent performance overhead to the systems. [ABSTRACT FROM AUTHOR]

Having an automatic tool capable of completing all steps of debugging including correction specially for complex designs such as modern processors is ideal for every debugging engineer. Although in theory, quantified Boolean formulas (QBFs) can be used to formulate this class of problems effectively, current solvers are still too immature for accomplishing this goal. In this paper, we propose a scalable symbolic simulation-based method utilizing QBF to correct the candidate bug locations in abstract formal models. We assume that candidate bug locations are determined already, the bug is located in bit-level logic, and the input arguments are known. We define correcting functions and adjust their parameters by formulating the problem as QBF and solving it using symbolic simulation-based method. To further improve scalability, we propose dynamic pruning which breaks the main problem into several smaller subproblems. The efficiency of the proposed method is proved by solving problems for which existing methods are not capable of providing results. [ABSTRACT FROM AUTHOR]

The increasing demand for lower power forces designers to use sophisticated power management strategies such as multivoltage and power gating which are often accompanied with many design bugs. Correcting such bugs can be a timeconsuming process that requires considerable manual efforts. In this paper, we propose a scalable automated method for correcting dynamic power management architectures by an incremental SAT-based mechanism. First, an initial counterexample (CEX) is generated by checking the equivalency between the specification model of the processor and its buggy implementation model. Then, we find two candidate solutions instead of one to satisfy this CEX. If two solutions are not equivalent, we generate new CEX in an iterative process which effectively converges into the final solution. The proposed method enables designers to correct multiple bugs such as missing isolation cells between two power domains, disordering in the sequence of control signals, error in the data restoring or saving, and powering off in always-on domains which are not addressed by existing methods. We have shown the effectiveness of our method on modern processors supporting complex power management mechanisms. The results confirm that our proposed method, respectively, reduces symbolic simulation steps and runtime by 2.33× and 47.93× compared to the state-of-the-art methods. [ABSTRACT FROM AUTHOR]

Although using presilicon information in postsilicon debugging phase seems interesting, space and time limitations of existing formal verification tools restrict the possibility of this idea. In this paper, the effective usage of presilicon information to enhance postsilicon trace signal selection in modern processors is discussed. Furthermore, a novel architecture for dynamic per-cycle selection of signals based on the present instruction is implemented and synthesized. In presilicon phase, first, a set of controlling signals and their corresponding rules are extracted manually. Based on these rules, a set of data from model is extracted using an automatic formal method, which determines which signals should be traced at postsilicon according to the values of controlling signals. This mechanism alone results in an average of 79% and 54% bits to be pruned from the traceable signals for Leon3 and multithreaded DLX processors and 86% and 75% improvement when used in conjunction with traditional methods, respectively. [ABSTRACT FROM AUTHOR]

This paper proposes a highly scalable sensor design for late transition detection in FPGA based platforms. Transition delays occur because of aging mechanisms such as Biased Temperature Instability (BTI) and Hot Carrier Injection (HCI). We propose a sensor clock (SCLK) that is a function of minimum slack time of a set of paths selected for age monitoring. There will be one such clock for many sensors as are needed in an entire FPGA. Our proposed sensor architecture makes it possible for a single SCLK to be shared by all sensors. Additionally, the proposed sensor occupies one slice (basic FPGA logic block), which leads to low area, power, and performance overhead. Using Artix-7-based board, experimental results demonstrate that the proposed aging sensor detects aging earlier than existing sensors and provides less power and performance overheads. [ABSTRACT FROM AUTHOR]

This paper concentrates on high-level data-flow optimization and synthesis techniques for datapath intensive designs such as those in Digital Signal Processing (DSP), computer graphics and embedded systems applications, which are modeled as polynomial computations over Z2^{n_1 } \times Z2^{n_2 } \times \cdots \times Z2^{n_d } to Z2^m . Our main contribution in this paper is proposing an optimization method based on functional decomposition of multivariate polynomial in the form of f(x) = g(x) \;o \;h(x) + f0 = g(h(x)) + f0 to obtain good building blocks, and vanishing polynomials over Z2^m to add/delete redundancy to/from given polynomial functions to extract further common sub-expressions. Experimental results for combinational implementation of the designs have shown an average saving of 38.85 and 18.85 percent in the number of gates and critical path delay, respectively, compared with the state-of-the-art techniques. Regarding the comparison with our previous works, the area and delay are improved by 10.87 and 11.22 percent, respectively. Furthermore, experimental results of sequential implementations have shown an average saving of 39.26 and 34.70 percent in the area and the latency, respectively, compared with the state-of-the-art techniques. [ABSTRACT FROM PUBLISHER]

Time, power, and data volume are among some of the most challenging issues for testing System-on-Chip (SoC) and have not been fully resolved, even if a scan-based technique is employed. A novel architecture, referred to the Selective Trigger Scan architecture, is introduced in this paper to address these issues. This architecture reduces switching activity in the circuit-under-test (CUT) and increases the clock frequency of the scanning process. An auxiliary chain is utilized in this architecture to avoid the large number of transitions to the CUT during the scan-in process, as well as enabling retention of the currently applied test vectors and applying only necessary changes to them. The auxiliary chain shifts in the difference between consecutive test vectors and only the required transitions (referred to as trigger data) are applied to the CUT. Power requirements are substantially reduced; moreover, DFT penalties are reduced because no additional multiplexer is utilized along the scan path. Data reformatting is applied in order to make the proposed architecture amenable to data compression, thus permitting a further reduction in test time. It also permits delay fault testing. Using ISCAS 85 and 89 benchmark circuits, the effectiveness of this architecture for improving SoC test measures (such as power, time, and data volume) is experimentally evaluated and confirmed. [ABSTRACT FROM AUTHOR]

Compression has been used in automatic test equipment (ATE) to reduce storage and application time for high volume data by exploiting the repetitive nature of test vectors. The application of a binary compression method to an ATE environment for manufacturing is studied using a technique, referred to as reuse. In reuse, compression is achieved by partitioning the vector set and removing repeating segments. This process has O(n²) time complexity for compression (where n is the number of vectors) with a simple hardware decoding circuitry. It is shown that for industrial system-on-chip (SoC) designs, the efficiency of the reuse compression technique is comparable to sophisticated software techniques with the advantage of easy and fast decoding. Two shift register-based decompression schemes are presented; they can be either incorporated into internal scan chains or built in the tester's head. The proposed compression method has been applied to industrial test and data and an average compression rate of 84% has been achieved. [ABSTRACT FROM AUTHOR]