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In digital circuit designs, sequential components such as flip-flops are used to synchronize signal propagations. Logic computations are aligned at and thus isolated by flip-flop stages. Although this fully synchronous style can reduce design efforts significantly, it may affect circuit performance negatively, because sequential components can only introduce delays into signal propagations but never accelerate them. In this article, we propose a new timing model, VirtualSync+, in which signals, specially those along critical paths, are allowed to propagate through several sequential stages without flip-flops. Timing constraints are still satisfied at the boundary of the optimized circuit to maintain a consistent interface with existing designs. By removing clock-to-q delays and setup time requirements of flip-flops on critical paths, the performance of a circuit can be pushed even beyond the limit of traditional sequential designs. In addition, we further enhance the optimization with VirtualSync+ by fine-tuning with commercial design tools, e.g., design compiler from Synopsys, to achieve more accurate result. To achieve this fine-tuning, we first optimize the circuits by reallocating sequential components with sequential and combinational components as delay units. Afterward, the removal locations of flip-flops with respect to the circuits under optimization are extracted and the corresponding wave-pipelining timing constraints compatible with commercial design tools are established. These timing constraints are then incorporated into the optimization flow of commercial tools to generate the optimized circuits. The experimental results demonstrate that circuit performance can be improved by up to 4% (average 1.5%) compared with that after extreme retiming and sizing, while the increase of area is still negligible. This timing performance is enhanced beyond the limit of traditional sequential designs. It also demonstrates that compared with those after retiming and sizing, the circuits with VirtualSync+ can achieve better timing performance under the same area cost or smaller area cost under the same clock period, respectively. [ABSTRACT FROM AUTHOR]

Viewing various stereo images under different viewing conditions has escalated the need for effective object-level remapping techniques. In this paper, we propose a new object spatial mapping scheme, which adjusts the depth and size of the selected object to match user preference and viewing conditions. Existing warping-based methods often distort the shape of important objects or cannot faithfully adjust the depth/size of the selected object due to improper warping such as local rotations. In this paper, by explicitly reducing the transformation freedom degree of warping, we propose an optimization model based on axis-aligned warping for object spatial remapping. The proposed axis-aligned warping based optimization model can simultaneously adjust the depths and sizes of selected objects to their target values without introducing severe shape distortions. Moreover, we propose object consistency constraints to ensure the size/shape of parts inside a selected object to be consistently adjusted. Such constraints improve the size/shape adjustment performance while remaining robust to some extent to incomplete object extraction. Experimental results demonstrate that the proposed method achieves high flexibility and effectiveness in adjusting the size and depth of objects compared with existing methods. [ABSTRACT FROM AUTHOR]

Reported researches on smart charging methods have the disadvantages of low calculation efficiency or have not simultaneously taken the three-phase imbalance, voltage, and power flow constraints into account. It is an important topic to improve the computational speed to meet the online rolling optimization requirement for EVCC problems. In this paper, the branch power flow equations of balanced and unbalanced distribution system are derived. The linearization methods for the nonlinear terms of the branch power flow equations are proposed. Two stages linear programming (LP) is introduced for EVCC to minimize the total charging costs of the holders where three-phase imbalance, charging demand, voltage, and power flow constraints have been taken into account. Via ignoring the nonlinear terms of the branch power flow equations, the first stage LP is formulated to calculate the estimated branch power and node voltages as the initial points for linearizing the nonlinear terms of branch power flow equations. The second stage LP is formulated to calculate the optimal charging power using the linearized branch power flow equations. Four case studies show that the proposed method without the compromise of precision is significantly faster than state-of-the-art works with respect to the computational speed. [ABSTRACT FROM AUTHOR]

Wheels are one of the three components of rail vehicles that are most affected by wear, having significant implications on safety and comfort. For the safety of vehicles, maintenance activities are needed for worn wheels to ensure their normal geometry, where reprofiling plays the most important role in maintenance. How to reprofile wheels scientifically and economically has become a vital issue, which needs to be solved in the field of wheel maintenance. This study focuses on high-speed train wheels and proposes a dynamic reprofiling policy based on condition monitoring at equidistant discrete time inspections. The problem is modeled in the framework of a semi-Markov decision process considering both wear and external shocks. The objective of the maintenance model is to minimize the long-term expected cost per unit time. We apply a policy-iteration algorithm to determine the optimal reprofiling policy. To demonstrate the model's effectiveness, actual degradation data on high-speed train wheels are used as an illustration. The results show that the dynamic reprofiling policy reduces wheel maintenance costs and extends their service life, also ensuring wheels’ safety. [ABSTRACT FROM AUTHOR]

At submicrometer manufacturing technology nodes, process variations affect circuit performance significantly. To counter these variations, engineers are reserving more timing margin to maintain yield, leading to an unaffordable overdesign. Most of these margins, however, are wasted after manufacturing, because process variations cause only some chips to be really slow, while other chips can easily meet given timing specifications. To reduce this pessimism, we can reserve less timing margin and tune failed chips after manufacturing with clock buffers to make them meet timing specifications. With this post-silicon clock tuning, critical paths can be balanced with neighboring paths in each chip specifically to counter the effect of process variations. Consequently, chips with timing failures can be rescued and the yield can thus be improved. This is specially useful in high-performance designs, e.g., high-end CPUs, where clock binning makes chips with higher performance much more profitable. In this paper, we propose a method to determine where to insert post-silicon tuning buffers during the design phase to improve the overall profit with clock binning. This method learns the buffer locations with a Sobol sequence iteratively and reduces the buffer ranges afterward with tuning concentration and buffer grouping. Experimental results demonstrate that the proposed method can achieve a profit improvement of about 14% on average and up to 26%, with only a small number of tuning buffers inserted into the circuit. [ABSTRACT FROM AUTHOR]

In real-time movement controlling systems, it is essential to deploy a suitable sensor to measure tilt angle on-line. When the tilt angle is bigger than the preset threshold, the remedial operation should be made timely. This paper proposes an on-line dynamic tilt angle measurement method by compensating gyroscope drift error. First, gyroscope is selected as a measuring unit because it can overcome the interference of external forces to measure dynamic angular speed. Second, an improved least squares support vector machine (LSSVM) is proposed for gyroscope drift-error compensation. The vector base learning method is used to reduce those less important support vectors, and the sparsity of LSSVM can be changed by adjusting the value of $\theta $. Third, the quantum-behaved particle swarm optimization algorithm is introduced as the optimization method to optimize regularization parameter C and kernel parameter $\gamma $ of LSSVM model because it has good optimization result and fast convergence speed. Fourth, the experiment platform and implementation process are illustrated in detail. Finally, the corresponding experimental results demonstrate that the proposed methodology could measure the dynamic tilt angle accurately. [ABSTRACT FROM AUTHOR]

System-architecture design optimization of flow-based microfluidic biochips has been extensively investigated over the past decade. Most of the prior work, however, is still based on chip architectures with dedicated storage units and this, not only limits the performance of biochips, but also increases their fabrication cost. To overcome this limitation, a distributed channel-storage architecture can be implemented, where fluid samples can be cached temporarily in flow channels instead of using a dedicated storage. This new concept of fluid storage, however, requires a careful arrangement of fluid samples to enable the channels to fulfill the dual functions of transportation and caching. Moreover, to avoid cross-contamination between different fluidic flows, wash operations are necessary to remove the residue left in flow channels. In this article, we formulate the first practical system level design and wash optimization problem for microfluidic biochips with distributed channel storage architecture, considering high-level synthesis, physical design, and wash optimization simultaneously, and present a top-down design flow to solve this problem systematically. Given the protocol of a biochemical application and the corresponding design requirements, our goal is to generate a chip architecture with low fabrication cost. Meanwhile the biochemical application can be executed efficiently with an optimized wash scheme. Experimental results on multiple benchmarks confirm that our approach leads to short completion time of biochemical applications, low chip cost, as well as high wash efficiency. [ABSTRACT FROM AUTHOR]

On-line tilt angle detection and prognosis are the important prerequisites of real-time movement controlling. This paper develops a time-effective tilt angle prognosis methodology and its evaluation prototype. First, a complementary filter is imported to extend both the superiorities sufficiently of accelerometer and gyroscope, accurate tilt angle detection then can be achieved in a wide range of frequency. Second, an improved sparse least-squares support vector regression is proposed for tilt angle prognosis, its configurable singularity spectrum technology keeps away from the high-order matrix operation through eliminating nonprincipal components among raw vectors. Third, novel composite judgment criteria and its derived dynamic sliding window mechanism are proposed to pursue scientific balance of the prediction precision and computational cost. Fourth, double chains quantum genetic algorithm is introduced as the optimization tool to search optimal parameters of the above-mentioned models. Finally, the prototype setup and the corresponding experimental results are demonstrated and discussed in detail, which promise that our proposed methodology could be potentially applied to the actual motion control systems. [ABSTRACT FROM AUTHOR]