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This article proposes a systematic synthesis method to identify the optimum converter topology for a specified voltage conversion ratio. This gain-oriented converter synthesis is formulated as an inverse problem around the inductor flux balance equations. The proposed synthesis method consists of two processes. A set of distinct converter topologies is first synthesized from the specified voltage conversion ratio by obtaining the solutions for a set of six inverse equations in twelve unknowns. The optimal topology for any intended application can be identified based on the desired performance metrics. The complete synthesis method is illustrated with quadratic buck–boost gain as an example. In total, 25 distinct topologies are synthesized using the first process, and their feasibility is validated by PLECS simulation. In total, three case studies are reported to explain the second process. Ground-referenced output and the minimum number of switches are used as the first two selection criteria in all the case studies. Minimum peak inductor current, minimum component stress factor, and minimum voltage and current stress are the third selection criterion in Case Studies-1, 2, and 3, respectively. The steady-state operations of two optimal converters selected in Case Study-1 were verified experimentally. [ABSTRACT FROM AUTHOR]

This article presents an analytical method to derive an optimum converter topology for a specified voltage conversion ratio (G). An optimum topology for any given G can be identified after obtaining the comprehensive pool of converter topologies. This gain-oriented converter synthesis is formulated as an inverse problem around the principle of inductor flux balance. A step-by-step method is proposed to solve the inverse problem and obtain a comprehensive set of non-redundant converter topologies for any given voltage conversion ratio. Consequently, the number of possible converter topologies for a specified voltage conversion ratio is also identified. The optimum converter topology is chosen from the comprehensive set based on three selection criteria, viz., ground-referenced output, a minimum number of switches, and minimum peak inductor current. The proposed solution methodology is illustrated with quadratic boost and quadratic buck gains as case studies. A comprehensive set of non-redundant topologies is identified in both cases. The steady-state operations of all the topologies are studied with PLECS simulation. Based on the selection criteria, an optimum topology is selected in each case, and their steady-state operation is verified experimentally using lab-developed prototypes. [ABSTRACT FROM AUTHOR]

Nonisolated dc–dc converters are fundamental building blocks in the power supply for a wide range of applications. To cater to this heterogeneity in applications, development of dc–dc converters with suitable voltage conversion ratio (G) is imperative. Given a converter topology, G can be found out uniquely by using the principle of inductor volt-second balance, and the process of obtaining the voltage conversion ratio from the topology is simple. In contrast, the inverse problem, i.e., the process of obtaining the converter topology for a given voltage conversion ratio (G) is a challenging task, and the obtained topology is also not unique. This article presents a simple method to obtain a family of converter topologies from a required voltage conversion ratio. This method utilizes the principle of inductor flux balance as a synthesis tool. The step-by-step procedure to synthesize the converter topologies is outlined. To illustrate the efficacy of the proposed method, it is applied to synthesize various quadratic buck–boost topologies, and a family of converters is identified. Operation and feasibility of two novel topologies, identified by the proposed theory, are verified experimentally. [ABSTRACT FROM AUTHOR]

The inverse problem for the dc–dc converters refers to synthesizing converter topologies from a specified voltage gain expression. Though the flux balance principle is widely used in the analysis of dc–dc converters, its application as a synthesis tool has not been explored. This letter describes a mathematical approach to synthesize converter topologies from a required voltage gain expression by utilizing the principle of inductor flux balance. At first, the general form of gain expression for second-order converters is derived. From the general form of gain expression, the inverse problem is formulated by identifying the governing equations. The mathematical formulation of the inverse problem and highlighting challenges involved in solving it are the primary subjects of this article. To outline these challenges, a probable solution strategy of this inverse problem is presented. In order to derive a converter topology, at first, the appropriate flux balance equations are determined, and then the circuit topology is derived to establish the required flux balance. In contrast to the forward problem, the solution to the inverse problem is neither direct nor unique. Hence, getting the optimum closed-form solution to this inverse problem is an open-ended challenge with many possible approaches. [ABSTRACT FROM AUTHOR]

This paper describes a theory to synthesize nonisolated dc–dc converters. It uses the fundamental flux balance equation across the inductors of a converter as a starting point in this synthesis process. The flux balance equations are the linear equations of the input voltage, capacitor voltages, and duty cycle (D). The coefficients of these linear equations can be selected from a finite set of choices. These choices define the converter topologies that are subsequently used to synthesize a converter. The synthesis procedure applies to a converter of multiple order. All the possible converters are identified for a first-order topology. In the case of second-order converters, all the choices of the flux balance equation are defined. Based on these choices, three new quadratic topologies are derived and verified to demonstrate the effectiveness of the theory. The procedure to synthesize a converter from a given voltage conversion ratio is also outlined. [ABSTRACT FROM AUTHOR]

Due to the pulsating power at the inverter output terminals, the passive storage elements of the boost stage of the current-fed switched inverter (CFSI) contain a power frequency harmonic component (100 Hz), apart from dc and switching frequency components. In prior designs, the second harmonic component is suppressed by increasing the size of the input filter inductor and capacitor or by using additional circuits. This paper presents a complete characterization of a control-based approach to suppress the power frequency harmonic component in the input inductor current of a CFSI. It also presents a comprehensive characterization of the harmonic power redistribution. Using the proposed approach, it is demonstrated that the inductor value of a CFSI is reduced by 61% for the same peak-to-peak ripple. This leads to an improvement in the conversion ratio, efficiency, and power density of the overall converter. A SiC MOSFET-based CFSI with 75-kHz switching frequency is used to verify the proposed design philosophy. [ABSTRACT FROM AUTHOR]

Impedance source inverters (ISIs) are gaining attention due to features such as single-stage conversion, buck-boost capability, and inherent shoot-through protection. To maintain the required ac output voltage, typically ISIs are operated at a higher dc-link voltage due to constrained modulation index. This also increases voltage stress across capacitors and switches of the converter. This voltage stress is approximately double compared to that of voltage source inverter with preboost stage (Boost-VSI). To mitigate this problem, a new pulsewidth modulation (PWM) scheme for the active-front-end based ISIs (AFE-ISIs) is proposed. The proposed scheme enables the ISIs to produce high ac gain with lower voltage stress across the capacitor and switches. In other words, the proposed scheme blends the advantages of Boost-VSI into ISIs. With the new PWM scheme, there are also reductions in output voltage total harmonic distortion, switching frequency ripple in the inductor current, and power loss in the converter. A prototype of the current-fed switched inverter, an AFE-ISI, is designed, and the proposed PWM scheme is implemented. Experimental results obtained are in accordance with the proposed theory and show that the voltage stress has reduced from 325 V to 203 V for an ac output of 110 V. [ABSTRACT FROM AUTHOR]

Power-hardware-in-the-loop (PHIL) simulations are used to test power hardware with the help of computer-based real-time simulations. Generally, buck-based power amplifiers that have good dynamic performance are used to construct a PHIL simulator because of their linear large signal control-to-output characteristics. However, their output voltage peak is limited to the applied dc input in the linear region of modulation. In this paper, a differential boost converter (DBC)-based power amplifier is proposed for PHIL simulations, which does not suffer from the aforementioned limitations of a buck-based amplifier. A conventional DBC exhibits highly nonlinear control-to-output behavior. A feedback linearization technique is used to linearize the DBC in a large signal and dynamic sense, which makes it suitable for PHIL applications. Using this power amplifier and a MATLAB/Simulink toolbox for real-time simulations, the PHIL simulator is constructed. Experimental results under various operating conditions of source voltages, such as unipolar, bipolar, transients in frequency, and the dc step, and various load conditions, such as reactive, nonlinear, and transient faults, are provided to confirm the efficacy of the proposed PHIL simulator. [ABSTRACT FROM PUBLISHER]

Buck-converter-based topologies are used to generate high-frequency sinusoidal outputs. Buck-based inversion circuits such as voltage source inverters or class-D amplifiers have inherent control-to-output linearity in large-signal sense. However, in these topologies, the instantaneous output is always smaller than the dc-input during linear modulation. A differential boost inverter (DBI) is a boost-based topology that is used to generate a sinusoidal output. In DBI, the instantaneous output can be higher or lower than the dc-input voltage. DBI exhibits nonlinear control-to-output behavior in large-signal dynamic sense. Therefore, generating a high-frequency sinusoidal output using this topology is a challenge. The issues associated with a DBI for high-frequency sine wave generation are characterized in this paper. Conventional linear and nonlinear control techniques fail to produce a high-quality sine wave output at higher operating frequency. A nonlinear feedback linearization technique is proposed, which forces the output to be linear with respect to the reference even at higher operating frequency. This leads to a high-frequency high-quality sine wave generation using a DBI. The proposed modulator is verified using a laboratory prototype to generate a sine wave up to 2 kHz. A triangular wave of 100-Hz frequency is also generated by the proposed technique. Superior dynamic responses of a dynamic linearizing modulator controlled DBI for a step change in frequency, load current, input voltage, and reference are also experimentally verified. [ABSTRACT FROM AUTHOR]

The Z-source inverter (ZSI) employs an LC impedance network between the main inverter bridge and the power source. The unique feature of the ZSI is that it can operate either in buck or boost mode with a wide range of obtainable output voltages from a given input voltage. This topology also exhibits better electromagnetic-interference noise immunity when compared to a traditional voltage-source inverter (VSI). However, the LC impedance network of ZSI significantly increases the size and cost of the power converter and can make it unsuitable for low-power applications. This paper proposes a novel topology called switched boost inverter (SBI) which exhibits similar advantages of ZSI with lower number of passive components and more active components compared to ZSI. The steady-state and small-signal analyses of SBI, along with its pulsewidth modulation (PWM) control strategies, have been discussed in this paper. This paper also presents a comparison of SBI and ZSI with the same input and output parameters. The theoretical analysis given in this paper has been validated using a laboratory prototype of SBI, and the experimental results are presented for verification. The experimental harmonic spectrum of the inverter's output voltage with the proposed PWM technique is also plotted and compared with that of a traditional VSI. All the experimental results show good correlation between theory and experiments. [ABSTRACT FROM PUBLISHER]

Switched boost inverter (SBI) is a single-stage power converter derived from Inverse Watkins Johnson topology. Unlike the traditional buck-type voltage source inverter (VSI), the SBI can produce an ac output voltage that is either greater or less than the available dc input voltage. Also, the SBI exhibits better electromagnetic interference noise immunity when compared to the VSI, which enables compact design of the power converter. Another advantage of SBI is that it can supply both dc and ac loads simultaneously from a single dc input. These features make the SBI suitable for dc nanogrid applications. In this paper, the SBI is proposed as a power electronic interface in dc nanogrid. The structure and advantages of the proposed SBI-based nanogrid are discussed in detail. This paper also presents a dq synchronous-reference-frame-based controller for SBI, which regulates both dc and ac bus voltages of the nanogrid to their respective reference values under steady state as well as under dynamic load variation in the nanogrid. The control system of SBI has been experimentally validated using a 0.5-kW laboratory prototype of the SBI supplying both dc and ac loads simultaneously, and the relevant experimental results are given in this paper. The low cross regulation and the dynamic performance of the control system have also been verified experimentally for a 20% step change in either dc or ac load of SBI. These experimental results confirm the suitability of the SBI and its closed-loop control strategy for dc nanogrid applications. [ABSTRACT FROM AUTHOR]

Electronic load (E-load) is commonly used to test power supplies. In order to test computer power supplies, the E-load must possess an ideal controlled current source property which draws a desired load current even in the case of a very low terminal voltage of the source under test (SUT). It also needs to have superior dynamic performance to simulate high-slew-rate load transients. This paper proposes the design of a switching-converter-based E-load with very large operational bandwidth. The overall architecture of the E-load consists of a low-bandwidth converter, which functions under steady state, and a high-bandwidth auxiliary circuit that is only active during transient state. The converter circuit is realized using a novel switched-boost topology, and the auxiliary circuit is realized using a MOSFET operating at the edge of saturation and linear region. The proposed topology is capable of sinking a specific amount of load current even with a very low SUT terminal voltage. Simulation and experimental validations are provided to verify the proposed concepts. A prototype has been built to test the proposed architecture. The operational input voltage (SUT voltage) ranges of the prototype are between 0.5 and 6 V. The load current range is between 0.75 and 7 A. The results validate the excellent dynamic characteristics of the proposed architecture. [ABSTRACT FROM PUBLISHER]

The flying capacitor multicell inverter (FCMI) possesses natural balancing property. With the phase-shifted carrier-based scheme, natural balancing can be achieved in a straightforward manner. However, to achieve natural balancing with the harmonically optimal phase-disposition (PD) carrier-based scheme, the conventional approaches require (n − 1) × (n − 1) trapezoidal carrier signals for an n-level inverter, which is ( n − 1) × (n − 2) times more than that in the standard PD scheme. This paper proposes two improved natural balancing strategies for FCMI under PD scheme, which use the same (n − 1) carrier signals as used in the standard PD scheme. In the first scheme, the on-line detections are performed of (i) the band in which the modulation signal is located, (ii) corresponding period number of the carrier, and (iii) rising or falling half cycle of the carrier waveform to generate the switching signals based on certain rules. In the second strategy, the output voltage level selection is first processed and the switching signals are then generated according to a rule based on preferential cell selection algorithm. These methods are easy to use and can be simply implemented as compared to the other available methods. Simulation and experimental results are presented for a five-level inverter to verify these proposed schemes. [ABSTRACT FROM AUTHOR]

The hysteresis modulation for power electronic converters is attractive in many different applications because of its unmatched dynamic response and wide command-tracking bandwidth. Its application and benefits for two-level converters are well understood, but the extension of this strategy to multilevel converters is still under development. This paper summarizes and reviews the various hysteresis modulation approaches available in the literature for multilevel converters. The pros and cons of various techniques are described and compared for tracking the reference signal in order to attain an adequate switching optimization, excellent dynamic responses and high accuracy in steady-state operation. By using the recently developed multilevel hysteresis modulation approaches, the advantages of using several accessible dc potentials in a multilevel inverter have been fully exploited. All of these hysteresis modulation approaches are tested for tracking a current reference when applied to a five-level inverter. The relevant simulation and experimental results are also presented. This study will provide a useful framework and point of reference for the future development of hysteresis modulation for multilevel converters. [ABSTRACT FROM AUTHOR]

In this paper, the performance of voltage-source converter-based shunt and series compensators used for load voltage control in electrical power distribution systems has been analyzed and compared, when a nonlinear load is connected across the load bus. The comparison has been made based on the closed-loop frequency response characteristics of the compensated distribution system. A distribution static compensator (DSTATCOM) as a shunt device and a dynamic voltage restorer (DVR) as a series device are considered in the voltage-control mode for the comparison. The power-quality problems which these compensator address include voltage sags/swells, load voltage harmonic distortions, and unbalancing. The effect of various system parameters on the control performance of the compensator can be studied using the proposed analysis. In particular, the performance of the two compensators are compared with the strong ac supply (stiff source) and weak ac-supply (non-stiff source) distribution system. The experimental verification of the analytical results derived has been obtained using a laboratory model of the single-phase DSTATCOM and DVR. A generalized converter topology using a cascaded multilevel inverter has been proposed for the medium-voltage distribution system. Simulation studies have been performed in the PSCAD/EMTDC software to verify the results in the three-phase system. [ABSTRACT FROM AUTHOR]

In this paper, a generalized multiband hysteresis modulation and its characterization have been proposed for the sliding-mode control of cascaded H-bridge multilevel-inverter (CHBMLI)-controlled systems. A frequency-domain method is proposed for the determination of net hysteresis bandwidth for a given desired maximum switching frequency of the inverter. The switching transition concept of Tsypkin's method and the describing function of nonlinear relay have been used for the derivation of results. A hierarchical switching algorithm has been suggested for the modular cells of the cascaded multilevel inverter. The hierarchy of each cell is swapped sequentially to provide the self-balancing capability in case the dc-link voltage is supported by the capacitors. The simulation and experimental verification of the derived results are provided through a single-phase distribution static compensator (DSTATCOM) model. The application in the three-phase system has been shown through simulation studies on a 3.3-kV distribution-system compensation using DSTATCOM. Verification on both single- and three-phase systems is obtained using a five-level cascaded-multilevel-inverter topology. [ABSTRACT FROM AUTHOR]

This paper proposes a flying-capacitor-based chopper circuit for dc capacitor voltage equalization in diode-clamped multilevel inverters. Its important features are reduced voltage stress across the chopper switches, possible reduction in the chopper switching frequency, improved reliability, and ride-through capability enhancement. This topology is analyzed using three-and four-level flying-capacitor-based chopper circuit configurations. These configurations are different in capacitor and semiconductor device count and correspondingly reduce the device voltage stresses by half and one-third, respectively. The detailed working principles and control schemes for these circuits are presented. It is shown that, by preferentially selecting the available chopper switch states, the dc-link capacitor voltages can be efficiently equalized in addition to having tightly regulated flying-capacitor voltages around their references. The various operating modes of the chopper are described along with their preferential selection logic to achieve the desired performances. The performance of the proposed chopper and corresponding control schemes are confirmed through both simulation and experimental investigations. [ABSTRACT FROM AUTHOR]

In this paper, a fixed-switching-frequency closed-loop modulation of a voltage-source inverter (VSI), upon the digital implementation of the modulation process, is analyzed and characterized. The sampling frequency of the digital processor is considered as an integer multiple of the modulation switching frequency. An expression for the determination of the modulation design parameter is developed for smooth modulation at a fixed switching frequency. The variation of the sampling frequency, switching frequency, and modulation index has been analyzed for the determination of the switching condition under closed loop. It is shown that the switching condition determined based on the continuous-time analysis of the closed-loop modulation will ensure smooth modulation upon the digital implementation of the modulation process. However, the stability properties need to be tested prior to digital implementation as they get deteriorated at smaller sampling frequencies. The closed-loop modulation index needs to be considered maximum while determining the design parameters for smooth modulation. In particular, a detailed analysis has been carried out by varying the control gain in the sliding-mode control of a two-level YSI. The proposed analysis of the closed-loop modulation of the VSI has been verified for the operation of a distribution static compensator. The theoretical results are validated experimentally on both single- and three-phase systems. [ABSTRACT FROM AUTHOR]

This paper examines the application of a diodeclamped multilevel inverter (DCMLI).based distribution static compensator (DSTATCOM) connected to a three-phase, four-wire (3p4w) distribution system. The DCMLI has an inherent unbalancing problem among its dc capacitor voltages. Additionally, when the load contains a dc part, the neutral point of the compensator also becomes unbalanced. In this paper, the effects of different loading conditions on the dc capacitor voltages of the inverter are studied. Two new control circuits are proposed for equalizing the capacitor voltages. Different control techniques are presented for the equalizing circuits. Equations of the proposed equalizing controllers are developed corresponding to the control of the switching devices. Comparative studies of different control techniques and the performances of the two controllers are performed. Simulation studies are performed using PSCADIEMTDC to validate the efficacy of the proposed equalizing controller circuits. [ABSTRACT FROM AUTHOR]

This paper focuses on the development of multilevel hysteresis current regulation strategies. Two such strategies have been discussed and some modifications in their control tasks have been proposed to achieve more reliable and improved performance. In general, the multiband concept has been used while making the proposals. The hysteresis band size considerations have also been presented by taking into account the desired and existing system conditions. The proposed modulation schemes have been applied to a five-level flying-capacitor inverter, whose operation under hysteresis current control mode is much less established. A new method of flying-capacitor voltage balancing is proposed which ensures balanced flying-capacitor voltages and, at the same time, maintains the desired current profile. It uses a time-based approach for controlling the capacitor voltages and achieves appreciable voltage spectrum under wide range of load power factor conditions. The performance of the proposed strategies is confirmed through both simulation and experimental investigations. [ABSTRACT FROM AUTHOR]

In this paper, the method of triangular carrier switching control of two-level inverters is extended to cascaded multilevel inverters using phase-shifted multicarrier unipolar pulsewidth modulation (PWM). The condition for smooth modulation is obtained using the Bessel's function representation of the PWM output and the switching condition of the multilevel- inverter-controlled system. A method is proposed for the determination of the minimum amplitude of the triangular carrier for smooth modulation at fixed switching frequency. It is shown that the multilevel modulation based on the phase-shifted carriers significantly reduces the ripple magnitude in the switching function and allows the use of a smaller carrier amplitude under closed loop. This increases the forward gain and, hence, improves the tracking characteristics. The proposed cascaded multilevel inverter control is implemented for the operation of a distribution static compensator (DSTATCOM) in the voltage control mode. The experimental verification of the theoretical and simulation results is provided through a field-programmable gate array (FPGA) based control of a laboratory model of a single-phase DSTATCOM. [ABSTRACT FROM AUTHOR]

In this paper, load compensation using multilevel inverter-based distribution static compensator (DSTATCOM) is presented. The DSTATCOM is connected to a three-phase four-wire (3p4w) distribution system. Two different multilevel inverter topologies are used to realize the DSTATCOM. They are diode-clamped multilevel inverter (DCMLI) and flying capacitor multilevel inverter (FCMLI). A compensating technique has been derived, which uses the state feedback control to the multilevel inverters-based DSTATCOMs. A switching strategy for the multi-level inverters that ensures utilization of all output voltage states of the inverter for efficient tracking of references has been proposed. The schemes of dc-link capacitor volthge control for DCMLI and flying capacitor voltage control for FCMLI have been discussed. Comparative studies of performances of the two DSTATCOM topologies are performed. The simulation studies are performed using PSCAD/EMTDC to validate the efficacy of the proposed control scheme. [ABSTRACT FROM AUTHOR]

Flying capacitor multilevel inverter (FCMLI) is a multiple voltage level inverter topology intended for high voltage and power operations with low distortion. It uses capacitors, called flying capacitors for clamping the voltage across the power semiconductor devices. In this paper, the implementation of a distribution static compensator (DSTATCOM) using an FCMLI is presented. A hysteresis current control technique for controlling the injected current by the FCMLI-based DSTATCOM is discussed. A new method for controlling the flying capacitor voltages is proposed which ensures that their voltages remain constant and at the same time maintain the desired current profile under the hysteresis current control operation. Simulation studies are performed using PSCAD/EMTDC to validate the efficacy of the control scheme and the FCMLI-based DSTATCOM. [ABSTRACT FROM AUTHOR]

This paper proposes a new connection for a unified power quality conditioner (UPQC) to improve the power quality of two feeders in a distribution system. A UPQC consists of a series voltage-source converter (VSC) and a shunt VSC both joined together by a common dc bus. It is demonstrated how this device is connected between two independent feeders to regulate the bus voltage of one of the feeders while regulating the voltage across a sensitive load in the other feeder. Since the UPQC is connected between two different feeders (lines), this connection of the UPQC will be called an interline UPQC (IUPQC). The structure, control and capability of the IUPQC are discussed in this paper. The efficacy of the proposed configuration has been verified through simulation studies using PSCAD/EMTDC. [ABSTRACT FROM AUTHOR]

The flying capacitor multilevel inverter (FCMLI) is a multiple voltage level inverter topology intended for high-power and high-voltage operations at low distortion. It uses capacitors, called flying capacitors, to clamp the voltage across the power semiconductor devices. A method for controlling the FCMLI is proposed which ensures that the flying capacitor voltages remain nearly constant using the preferential charging and discharging of these capacitors. A static synchronous compensator (STATCOM) and a static synchronous series compensator (SSSC) based on five-level flying capacitor inverters are proposed. Control schemes for both the FACTS controllers are developed and verified in terms of voltage control, power flow control, and power oscillation damping when installed in a single-machine infinite bus (SMIB) system. Simulation studies are performed using PSCAD/EMTDC to validate the efficacy of the control scheme and the FCMLI-based flexible alternating current transmission system (FACTS) controllers. [ABSTRACT FROM AUTHOR]

The paper discusses the concept of a mini custom power park in which the voltage inside the park is tightly regulated by a distribution static compensator (DSTATCOM). It will be shown on the basis of simulations with ideal components that solid state protection devices, along with the DSTATCOM will eliminate many transients in all the loads of the park during disturbances. Moreover, the DSTATCOM, backed by a diesel generator, will supply the most sensitive loads during the total line outages, thereby nearly making them both transient and interruption free. In this paper, a configuration of the park is proposed and then various issues involved with the operation of the park are discussed. The proposed operation of the custom power park is verified through extensive digital computer simulation studies. [ABSTRACT FROM AUTHOR]

The paper discusses the operating principles and control characteristics of a dynamic voltage restorer (DVR) that protects sensitive but unbalanced and/or distorted loads. The main aim of the DVR is to regulate the voltage at the load terminal irrespective of sag/swell, distortion, or unbalance in the supply voltage. In this paper, the DVR is operated in such a fashion that it does not supply or absorb any active power during the steady-state operation. Hence, a dc capacitor rather than a dc source can supply the voltage source inverter realizing the DVR. The proposed DVR operation is verified through extensive digital computer simulation studies. [ABSTRACT FROM AUTHOR]

In this paper, a static synchronous series compensator (SSSC), along with a fixed capacitor, is used to avoid torsional mode instability in a series compensated transmission system. A 48-step harmonic neutralized inverter is used for the realization of the SSSC. The system under consideration is the IEEE first benchmark model on SSR analysis. The system stability is studied both through eigenvalue analysis and EMTDC/PSCAD simulation studies. It is shown that the combination of the SSSC and the fixed capacitor improves the synchronizing power coefficient. The presence of the fixed capacitor ensures increased damping of small signal oscillations. At higher levels of fixed capacitor compensation, a damping controller is required to stabilize the torsional modes of SSR. [ABSTRACT FROM AUTHOR]

Voltage imbalance in capacitors is a well-known problem in compensator topologies which use two or more capacitors. This imbalance may exist even if the load does not contain any dc component, due to practical factors. However, when the load contains a dc part, the voltage imbalance problem becomes critical. In this paper, a two-quadrant chopper has been used to regulate the capacitor voltages in a two-capacitor compensator structure. Two different control strategies for the two-quadrant chopper to equalize the voltage of the capacitors have been proposed. The strategies are validated through detailed simulation studies. Experiments have also been carried out to validate the hysteresis control of chopper. [ABSTRACT FROM AUTHOR]

Describes a public-domain simulator for power electronic circuits. Organization of the simulator; Application of the simulator; Access to expensive commercial packages.

Presents an approach for generating reference currents for an active filter and/or a static compensator in a power distribution system. Compensating star connected loads; Compensating delta connected loads; Compensator structure.

Responds to comments on an article appearing in the January 2000 issue of 'IEEE Transactions on Power Delivery,' which dealt with an approach to load balancing in power distribution system. Configuration of the load; Aim of the compensator; Plot of the voltage vector in the complex plane.