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In this article, the static, dynamic, and short-circuit properties of 1.2-kV commercial 4H-SiC planar and trench gate metal–oxide–semiconductor field-effect transistors (MOSFETs) are compared and analyzed in a wide temperature range from 90 to 493 K. The temperature-dependent specific ON-resistance (${R}_{\text {sp}- \mathrm{\scriptscriptstyle ON}}$) and threshold voltage (${V}_{\text {th}}$) are analyzed in relation to the density of the interface state. The turn-on rise and turn-off fall times (${T}_{r}$ and ${T}_{f}$) and the corresponding energy loss (${E}_{r}$ and ${E}_{f}$) are extracted from a double-pulse test from cryogenic to high temperature and analyzed. The short-circuit capability of the two structures is studied at low temperature for the first time. The comprehensive comparison and analysis of the planar and trench gate MOSFET versus temperature in this work show the importance to study applications with SiC MOSFETs in a wide temperature range, especially for the cryogenic temperatures. [ABSTRACT FROM AUTHOR]

In this paper, an improved 4H-SiC U-shaped trench-gate metal–oxide–semiconductor field-effect transistors (UMOSFETs) structure with low ON-resistance (${R}_{ \mathrm{\scriptscriptstyle ON}}$) and switching energy loss is proposed. The novel structure features an added n-type region, which reduces ON-resistance of the device significantly while maintaining the breakdown voltage (${V}_{\textsf {BR}}$). In addition, the gate of the improved structure is designed as a p-n junction to reduce the switching energy loss. Simulations by Sentaurus TCAD are carried out to reveal the working mechanism of this improved structure. For the static performance, the ON-resistance and the figure of merit (FOM $= {V}_{\textsf {BR}}^{\textsf {2}}/{R}_{ \mathrm{\scriptscriptstyle ON}}$) of the optimized structure are improved by 40% and 44%, respectively, as compared to a conventional trench MOSFET without the added n-type region and modified gate. For the dynamic performance, the turn-on time (${T}_{ \mathrm{\scriptscriptstyle ON}}$) and turn-off time (${T}_{ \mathrm{\scriptscriptstyle OFF}}$) of the proposed structure are both shorter than that of the conventional structure, bringing a 43% and 30% reduction in turn-on energy loss and total switching energy loss (${E}_{\mathbf {SW}}$). [ABSTRACT FROM AUTHOR]

A simple and cost-effective precharge method for modular multilevel converter (MMC) by using a low-voltage direct current (dc) source is proposed in this paper. The submodule (SM) capacitors in MMC are required to be precharged to their nominal voltage values at start-up to ensure MMC work normally. Conventional methods perform the precharging either through grid side or dc side by using costly high-voltage bypass breakers, charging resistors or a high-voltage dc source. Voltage of the high-voltage dc source must be equal to SM capacitor voltage and could be as high as thousands of volts. By contrast, the proposed method employs a very low voltage dc source on dc bus through a series-connected blocking diode, and requires no charging resistor and bypass breakers. It takes advantages of the existing power devices, arm inductors, and SM capacitors in MMC, and configures them into boost circuit for the precharging. The proposed method is simple and cost-effective. Moreover, the characteristics of the boost circuit render the proposed method flexible. For instance, the voltage selection of the dc source is flexible and not restricted to a fixed value. The SM capacitors can be charged in different groups. In addition, the method is applicable to different MMC SMs, including SM with different capacitor voltages. The effectiveness of the proposed method is verified through simulation and experiment. [ABSTRACT FROM AUTHOR]

A capacitor voltage-balancing method for a nested neutral point clamped (NNPC) inverter is proposed in this paper. The NNPC inverter is a newly developed four-level voltage-source inverter for medium-voltage applications with properties such as operating over a wide range of voltages (2.4–7.2 kV) without the need for connecting power semiconductor in series and high-quality output voltage. The NNPC topology has two flying capacitors in each leg. In order to ensure that the inverter can operate normally and all switching devices share identical voltage stress, the voltage across each capacitor should be controlled and maintained at one-third of dc bus voltage. The proposed capacitor voltage-balancing method takes advantage of redundancy in phase switching states to control and balance flying capacitor voltages. Simple and effective logic tables are developed for the balancing control. The proposed method is easy to implement and needs very few computations. Moreover, the method is suitable for and easy to integrate with different pulse width modulation schemes. The effectiveness and feasibility of the proposed method is verified by simulation and experiment. [ABSTRACT FROM PUBLISHER]

A virtual space vector modulation technique reducing both magnitude and third-order harmonic component of the common-mode voltage (CMV) in a two-level voltage-source inverter (VSI) is proposed in this paper. The presented method employs a set of virtual space vectors constructed from original stationary space vectors to conduct modulation. Since the created virtual vectors have the lowest instantaneous and zero average CMVs, both the magnitude and third-order harmonic component of the generated CMV are reduced, contributing to better overall CMV performance and common-mode filter design in VSI applications. Three variants of the proposed modulation method using different virtual space vector combinations are presented. The concept of the virtual space vector modulation technique demonstrated with two-level inverter in this paper can also be extended to multilevel inverters. Simulation and experimental results, as well as comparisons with existing methods are provided to verify the proposed technique. [ABSTRACT FROM AUTHOR]

In this paper, an optimized structure of 4H-SiC U-shaped trench gate MOSFET (UMOSFET) with low resistance is proposed. The optimized structure adds an n-type region, wrapping the p+ shielding region incorporated at the bottom of the trench gate. The depletion region formed by the p+ shielding region reduces greatly for the high dopant concentration of the added region. This added region also conducts electrons downward and expands the electrons to the bottom of the p+ shielding region. We discussed the influence of dopant concentration and the width of the added region on the breakdown voltage (BV) and the ON-resistance in this paper. A reasonable size and an optimized concentration were chosen for the added region in our simulation. The channel inversion layer mobility was set to 50 cm ^2 /Vs, and the specific ON-resistance and the BV were 1.64 \textm\Omega \cdot cm^2 ( V\mathrm {GS}= 15 V, V\mathrm {DS}= 1 V, and no substrate resistance was included) and 891 V, respectively, using the numerical simulation. [ABSTRACT FROM AUTHOR]

This paper proposes a novel modular multilevel dc–dc converter intended for transforming dc voltage and interconnecting dc grids for medium-voltage networks. The converter is composed by two strings of submodules, each of which consists of an upper arm and a lower arm with their middle points crossly connected through a dc capacitor. With assistant of the cross-connected capacitors, dc and ac power loops are formed for the dc–dc converter, leading to the power balance between primary and secondary sides, as well as between upper and lower arms. The avoidance of transformer brings the favorable features of low cost and light weight to the proposed dc–dc converter. In order to guarantee the normal operation of the dc–dc converter, a control strategy with focus on converter power balance control is presented. Simulation performed in MATLAB/SIMULINK validates the operation principle of the dc–dc converter. Experimental results obtained from a 300-V 3.6-kW downscaled laboratory prototype also prove the effectiveness of the proposal. [ABSTRACT FROM AUTHOR]

This paper presents an active cross-connected modular multilevel converter (AC-MMC) based on series-connected half-bridge modules. It is intended for completely enhancing the performance of a medium-voltage motor drive system in the full speed range from standstill to rated speed under all load conditions. The proposed AC-MMC circuit is characterized by the cross connection of upper and lower arm middle taps through a branch of series-connected half-bridge converters, which have an identical voltage and current rating with the submodules in the upper and lower arms. This cross-connected branch provides a physical power transfer channel for the upper and lower arms. By properly controlling the amount of high-frequency current flowing through the cross-connected branch, the power balance between the upper and lower arms is achieved even at a zero/low motor speed under constant torque condition. Meanwhile, no common-mode voltage is introduced in the whole speed range. A control strategy with focus on submodule capacitor voltage control is also proposed in this paper to guarantee the normal converter operation. Simulation results obtained from a 4160-V, 1-MW model verify the feasibility of the proposal. Experiments on a downscaled prototype also confirm the validity of the novel circuit and the associated control strategy. [ABSTRACT FROM PUBLISHER]

In Chip Multiprocessors (CMPs) architecture, it is common that multiple cores share some on-chip cache. The sharing may cause cache thrashing and contention among co-running jobs. Job co-scheduling is an approach to tackling the problem by assigning jobs to cores appropriately so that the contention and consequent performance degradations are minimized. Job co-scheduling includes two tasks: the estimation of co-run performance, and the determination of suitable co-schedules. Most existing studies in job co-scheduling have concentrated on the first task but relies on simple techniques (e.g., trying different schedules) for the second. This paper presents a systematic exploration to the second task. The paper uncovers the computational complexity of the determination of optimal job co-schedules, proving its NP-completeness. It introduces a set of algorithms, based on graph theory and Integer/Linear Programming, for computing optimal co-schedules or their lower bounds in scenarios with or without job migrations. For complex cases, it empirically demonstrates the feasibility for approximating the optimal effectively by proposing several heuristics-based algorithms. These discoveries may facilitate the assessment of job co-schedulers by providing necessary baselines, as well as shed insights to the development of co-scheduling algorithms in practical systems. [ABSTRACT FROM AUTHOR]

Considering potential applications related to superconductivity and aerospace (typically less than 100 K), in this article, the temperature dependence of silicon carbide (SiC) power diodes is systematically characterized and analyzed over a wide temperature range of 90–478 K, especially focusing on cryogenic temperature. First, the static performance degradation mechanism of SiC diodes is established in an ultrawide temperature range, including forward/reverse I-V characteristics and junction capacitance (Cj) characteristics. Second, the reverse recovery characteristics are achieved, including peak reverse recovery current (Irm), reverse recovery charge (Qrr), and switching energy (Esw), clarifying a clearer internal relationship between reverse recovery and junction temperature. Meanwhile, the aforementioned critical parameters are further analyzed on an electrical scale with normal atmosphere temperature, including switching speed range of 62.3–2054.8 A/μs, load current range of 6–30 A, and dc voltage range of 400–1000 V. Third, based on newly proposed power loss analysis method, the continuous operation performance of SiC diodes is quantified and analyzed in actual cryogenic converters. The excellent temperature dependence indicates that SiC diodes have great superiority for extreme applications. Importantly, SiC mosfet's body diode shows the great potential to operate as a freewheeling diode in the compact converter, especially at cryogenic temperature. [ABSTRACT FROM AUTHOR]

Due to the superior material properties, SiC mosfet is a promising candidate switching device for high power density and high efficiency power conversion system. The robustness of switching device under extreme temperature condition becomes a crucial factor to ensure power conversion system safely and continuously operating. In this paper, the temperature dependence of dynamic performance of 1.2-kV 4H-SiC power mosfets is systematically characterized over such wide temperature range of 90–493 K and compared with 1.2-kV Si IGBT by a layout optimized double pulse tester (DPT). The degradation of dynamic on-resistance related interface traps is analyzed specially and the energy loss caused by degradation is quantified at cryogenic temperatures. Besides, to validate the performance of SiC mosfet under safely and continuously operating conditions for cryogenic temperature application, a hard switched non-isolated dc–dc buck converter is designed and tested to estimate temperature dependence of conversion efficiency under temperature range of 90–290 K. Moreover, the further characterizations are conducted with gate resistance range of 2–20 Ω, load current range of 3–30 A, and converter output current of 5–22.5 A under different switching frequency (up to 150 kHz) to validate high power and high frequency application potential of SiC mosfet. [ABSTRACT FROM AUTHOR]

A new instrumentation has been developed for noncontact monitoring of surface potential induced by electrons, both on satellites and ground. The surface potential monitor consisted of a surface charge detector head, front-end electrostatic voltage measurement circuit (EVMC), and associated control electronics. New leakage current eliminating and zero clearing techniques were used in the detector head structure and EVMC to ensure the measurement of the surface potential for a long term with range from 1 V to 10 kV, resolution <1, which meet the general design guidelines for measurements most relevant to spacecraft charging issues. [ABSTRACT FROM PUBLISHER]