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Quantum dot gate FETs (QDGFET) produce one intermediate state between two stable on and off states due to the change in the threshold voltage. A circuit model based on Berkeley Short-channel IGFET Model that accounts for this intermediate state is developed. Different ternary logic inverters such as standard ternary inverter, positive ternary inerter, and negative ternary inverter can be designed using QDGFETs. In this work the application of different ternary logic inverter in image processing are discussed. The comparison of binary logic inverter and ternary logic inverter is also discussed. Comparison with other technology is also presented Increased number of states in three state QDGFETs will increase the image processing capacity of QDGFET based circuits. [ABSTRACT FROM AUTHOR]

The control system based on the primary current feedback mode can effectively suppress the magnetic bias and avoid the overcurrent for the full bridge inverter. But in the process of its digitalization, the magnetic bias signal can be missed easily and the control accuracy is low, resulting in poor system stability and reliability. First, a new double closed-loop digital control method is proposed, which has advantages of the magnetic bias suppression in the primary current feedback mode and fast fine current adjustment in the secondary current feedback mode. Second, results of theoretical analysis on system stability and simulation prove that the method is feasible. Third, a single-chip design idea based on analog-digital mixed field-programmable gate array (FPGA) is proposed, and the detailed design program is described for the submerged arc welding system, which has high integration and strong anti-interference. Experimental results show that the digital control system has high stability and reliability to produce high submerged arc welding quality. [ABSTRACT FROM AUTHOR]

A low voltage operating fully-differential CMOS OTA construction, which uses dual-input CMOS cascode inverters, is proposed. The OTA is a two-stage configuration with dual-input CMOS cascode inverters at the input stage, and traditional CMOS inverters in the output stage, with a common-mode feedback path from the output terminals to one of the input terminals of cascode inverters. In order to effectively reduce its threshold voltages by bulk bias technique, the OTA has been designed and fabricated by using a 0.15 μm triple-well CMOS process. The OTA successfully operated from 1-V power supply, with 59 dB of differential voltage gain, 80.9 dB of CMRR and 25 MHz of unity gain frequency, at 60 μA of current consumption. [ABSTRACT FROM AUTHOR]

This study presents an inductorless 10 Gb/s transimpedance amplifier (TIA) implemented in a 40 nm CMOS technology. The TIA uses an inverter with active common-drain feedback (ICDF-TIA). The TIA is followed by a two-stage differential amplifier and a 50 Ω differential output driver to provide an interface to the measurement setup. The optical receiver shows measured optical sensitivities of −17.7 and −16.2 dBm at BER = 10 for data rates of 8 and 10 Gb/s, respectively. The TIA has a simulated transimpedance gain of 47 dBΩ, 8 GHz bandwidth with 0.45 pF total input capacitance for the photodiode, ESD protection and input PAD. The TIA occupies 0.0002 mm whereas the complete optical receiver occupies a chip area of 0.16 mm. The power consumption of the TIA is only 2.03 mW and the complete chip dissipates 17 mW for a 1.1 V single supply voltage. The complete optical receiver has a measured transimpedance gain of 57.5 dBΩ. [ABSTRACT FROM AUTHOR]

Simple and symmetrical ultra low-voltage current mode analog circuits and autozeroing amplifiers are presented. The low-voltage analog circuits are based on low-voltage inverters resembling precharge digital logic. Ultra low-voltage analog circuits can be operated at supply voltages down to 250 mV with rail-to-rail input and output swing. The output current of the ultra low-voltage symmetrical transconductance amplifier can be quite large due to a current boost technique. Ultra low-voltage analog circuits can be operated at supply voltages down to 250 mV with rail- to-rail input and output swing. The current headroom is 3 μA and the supply voltage is 300 mV. For supply voltages down to 300 mV simulated data shows that the maximum clock frequency is approximately 600 MHz. [ABSTRACT FROM AUTHOR]

Abstract  We investigate four novel negative-differential-resistance (NDR) circuits using the combination of the standard Si-based n-channel metal-oxide-semiconductor field-effect-transistor (NMOS) and SiGe-based heterojunction bipolar transistor (HBT). By suitably designing the parameters, we can obtain the Λ- or N-type current–voltage (I–V) curve. Especially, the peak current of the combined I–V curve could be easy adjusted by the external voltage. In application, we utilize the NDR circuit to design an inverter circuit based on the monostable–bistable transition logic element. The fabrication of these NDR circuits and applications could be completely implemented by the simple and standard Si-based CMOS or SiGe-based BiCMOS process without using the complex and expensive process such as metalorganic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE). [ABSTRACT FROM AUTHOR]

Abstract  An active polyphase filter capable of high frequency quadrature signal generation has been analyzed. The resistors of the classical passive polyphase filter have been replaced by transconductors, CMOS inverters (F. Tillman and H. Sjöland, Proceedings of the Norchip Conference (pp. 12–15), Nov. 2005; Analog Integrated Circuits and Signal Processing, 50(1) 7–12, 2007). A three-stage 0.13 μm CMOS active polyphase filter has been designed. Simulations with a differential input signal show a quadrature error less than 1° for the full stable input voltage range for frequencies from 6 GHz to 14 GHz. Phase errors in the differential input signal are suppressed at least three times at the output. Corner simulations at 10 GHz show a maximum phase error of 3° with both n- and pMOS slow, in all other cases the error is less than 0.75°. The three-stage filter consumes 34 mA from a 1.2 V supply. To investigate the robustness of the filter to changes in inverter delay, an inverter model was implemented in Verilog-A. Linear c in and g in were used, whereas g m , c out , and g out were non-linear. It was found that the filter could tolerate substantial delays. Up to 40° phase shift resulted in less than 1.5° quadrature phase error at the output. [ABSTRACT FROM AUTHOR]

An analysis of additional high-frequency losses in high-speed cage induction motors with closed rotor slots under sinusoidal and inverter supply at no load is presented. Calculated losses are compared with experimental results obtained by measurement on a 270 kW, 16,200/min, prototype motor, at both the delta and star connections of the stator winding. The main additional losses of the prototype motor investigated due to inverter supply are eddy current losses in the stator winding. Both measurement and calculation show that, at the delta connection, the additional losses are higher due to the lower modulation degree of the inverter, causing higher harmonic voltage amplitudes. [ABSTRACT FROM AUTHOR]

Thyristors are a class of nonlinear electronic device that exhibit bistable resistance—that is, they can be switched between two different conductance states. Thyristors are widely used as inverters (direct to alternating current converters) and for the smooth control of power in a variety of applications such as motors and refrigerators. Materials and structures that exhibit nonlinear resistance of this sort are not only useful for practical applications: they also provide systems for exploring fundamental aspects of solid-state and statistical physics. Here we report the discovery of a giant nonlinear resistance effect in the conducting organic salt \[thetas]-(BEDT-TTF)2CsCo(SCN)4, the voltage-current characteristics of which are essentially the same as those of a conventional thyristor. This intrinsic organic thyristor works as an inverter, generating an alternating current when a static direct-current voltage is applied. Whereas conventional thyristors consist of a series of diodes (their nonlinearity comes from interface effects at the p-n junctions), the present salt exhibits giant nonlinear resistance as a bulk phenomenon. We attribute the origin of this effect to the current-induced melting of insulating charge-order domains, an intrinsically non-equilibrium phenomenon in the sense that ordered domains are melted by a steady flow. [ABSTRACT FROM AUTHOR]

Parallel operation of inverter modules is the solution to increase the reliability, efficiency, and redundancy of inverters in microgrids. Load sharing among inverters in distributed generators (DGs) is a key issue. This study investigates the feasibility of power-sharing among parallel DGs using a dual control strategy in islanded mode of a microgrid. PQ control and droop control techniques are established to control the microgrid operation. P-f and Q-E droop control is used to attain real and reactive power sharing. The frequency variation caused by load change is an issue in droop control strategy whereas the tracking error of inverter power in PQ control is also a challenge. To address these issues, two DGs are interfaced with two parallel inverters in an islanded AC microgrid. PQ control is investigated for controlling the output real and reactive power of the DGs by assigning their references. The inverter under enhanced droop control implements power reallocation to restore the frequency among the distributed generators with predefined droop characteristics. A dual control strategy is proposed for the AC microgrid under islanded operation without communication link. Simulation studies are carried out using MATLAB/SIMULINK and the results show the validity and effective power-sharing performance of the system while maintaining a stable operation when the microgrid is in islanding mode. [ABSTRACT FROM AUTHOR]