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In this paper, a structure with growing MnO nanowires (NWs) on activated carbon paper was designed and prepared using a simple hydrothermal method. Electrochemical measurements show that the specific capacitance of these MnO nanowires/ACP reached 390 F g at a scan rate of 10 mV s and 529 F g at a current density of 2.0 A g. The long-term cycle life stability for MnO nanowires/ACP was examined and the results show that the capacitance decay was ~12% over 5000 cycles, indicating its long cycle life. Furthermore, they could also be used to assemble simple solid-state supercapacitors with high capacitance. These results show that the MnO nanowires/ACP could be a promising electrode material for energy storage. [ABSTRACT FROM AUTHOR]

Extensive research on the multi-bridge extension of cascaded rectifier stages is deemed important to meet the requirements of high-voltage and high-power applications. Two control structures for capacitor voltage balancing in cascaded rectifier stages are analyzed in this paper. On this basis, the balance strategy for the multi-bridge extension of single-phase cascaded rectifiers is explored. The balance method of ultra-fast balance modulation trajectories is introduced into single-phase multi-bridge cascaded rectification, and the optimal control strategy is selected through simulation verification and comparative analysis. During the actual experiments, some disturbance factors were introduced into the system, causing an instantaneous unbalanced state. However, through the control strategy proposed in this paper, the system can quickly regain balance. Through simulation validation and analysis of the experimental results, the reliability and innovation of this control strategy have been demonstrated. [ABSTRACT FROM AUTHOR]

The capacitor voltage unbalancing is the common problem in modular multilevel converter. This problem occurs even at the fundamental frequency due to the modulation technique which generates the unequal periods of the gate signals. To reduce this problem, this paper introduced a new submodule (SM)-based modular multilevel converter (MMC). The proposed MMC can generate the 2N + 1 level at the load side. By properly controlling the arm current of the converter, DC capacitor voltage in each submodule is balanced at its base voltage and improves the circulating current during unequal periods of the gate signals without using controller. This paper presents the performance of new submodule-based modular multilevel converter. Finally, the proposed converter is compared with the conventional modular multilevel converter topologies with and without third harmonic injection method. Further the proposed structure and presented techniques have been simulated in the MATLAB/SIMULINK, and the practical implementation has been done using hardware-in-the-loop (HIL) test. [ABSTRACT FROM AUTHOR]

Integrated capacitors such as in metal–insulator–metal and metal–oxide-metal capacitors use metal as top and bottom plates while the metal–oxide–semiconductor capacitors utilize polysilicon layer as top plate and silicon substrate as bottom plate (Utmel Electronics, 2021, What is the Difference between MOM, MIM and MOS Capacitors?. https://www.utmel.com/blog/categories/capacitors/). There are three (3) major challenges and solutions were discussed in this technical paper. First is the failure site localization of a subtle defect in the capacitor plates. To determine the specific location of the defect site, electron beam-induced current (EBIC) analysis was performed while the part was biased using a nanoprobe setup under scanning electron microscopy (SEM) environment. Second is the failure mechanism that resulted to contentions between an electrically induced physical damage (EIPD) or a fabrication process defects, particularly for damage sites that are not at the edge of the capacitor and without obvious manifestations of fabrication process anomalies such as bulging, voids, unetched material or shifts in the planarity of the die layers. To further understand the defect site, scanning transmission electron microscopy coupled with energy-dispersive X-ray spectroscopy were utilized to obtain high magnification imaging and elemental area mapping. Third is the misled conclusion to be an EIPD site manifested by burnt and reflowed metallization. The EIPD site was only a secondary effect of a capacitor dielectric breakdown. This refers to the root cause (capacitor dielectric breakdown) that was successfully uncovered after the thorough review on the die circuit schematic, inspection of the capacitors connected to the EIPD sites, review of the fault isolation results and pursuing the further physical failure analysis. As a result of the failure analysis, customer and Analog Devices Incorporated manufacturing hold lots were accurately dispositioned and related corrective actions were precisely identified and implemented. [ABSTRACT FROM AUTHOR]

The paper proposed a boost five-level inverter for wireless power transfer (WPT) system. It consists of one DC source, one inductor, one capacitor, and six power switches. It can produce a five-level output with an amplitude twice that of the DC source voltage. Compared with the existing five-level inverters, the proposed topology needs fewer power switches and energy storage elements, as well as lower power switches total standing voltage. Firstly, this paper introduced the topology and operating principle of the proposed inverter, established the mathematical models of the inverter output voltage and the system output power, and compared the proposed inverter with the existing five-level inverters. On this basis, the level cascaded extension method and topology of the proposed inverter were introduced and analyzed. Then, the modulation strategy and parameters of the proposed inverter were designed. Furthermore, the power loss of the proposed inverter was calculated. Finally, simulation and experimental verification were conducted. The results show that the inverter efficiency can reach up to about 94.5%, and the output THD can be as low as 24.47% or even lower. In addition, the transient response time is within 4 ms, proving the feasibility and superiority of the proposed inverter applied to WPT systems. [ABSTRACT FROM AUTHOR]

This paper presents a foreground calibration algorithm combination with a background calibration algorithm for successive approximation register analog-to-digital converters (ADC). The foreground calibration for capacitor mismatch is capacitor recombination algorithm and the background calibration for capacitor mismatch is single-channel least mean square (LMS) algorithm. The capacitor recombination algorithm can initially calibrate the capacitor array mismatch and provide an environment conducive to convergence for LMS algorithm. After running the capacitor recombination algorithm, the convergence speed of LMS algorithm can be improved. The results of 100 times of Monte Carlo simulation show that LMS algorithm can converge within 1500 cycles, the ADC signal-to-noise and distortion ratio is improved from 71.63 to 97.47 dB, the spurious-free dynamic range is improved from 84.98 to 125.28 dB, the effective number of bits is improved from 12.85 to 15.90 bits, the differential nonlinearity is reduced from 2.09 to 0.90 LSBs, and the integer nonlinear is reduced from 7.14 to 0.68 LSBs. [ABSTRACT FROM AUTHOR]

This paper presents a unique five-level inverter consisting of one DC voltage source and one capacitor. Here the capacitor acts like another source and is fed to the inverter along with the DC voltage source. The DC voltage source is also used to charge the capacitor with the help of an additional switch used inside the converter circuit. An inductor is used in the charging path to reduce the peak of the charging current. The in-phase disposition sinusoidal pulse-width modulation technique is used to generate the gate pulse for the devices of the presented converter. The proposed topology operates in two modes. One is energy stored mode and another is energy release mode. By using both modes of operation, the additional switch is triggered to charge the capacitor. The capacitor's charging and discharging mode and inverter power loss have been described thoroughly in this paper. The proposed five-level inverter topology has been developed and verified inside the laboratory. The controller of the converter has been implemented in the FPGA platform. The experimental results are obtained to evaluate the efficacy of the proposed inverter. [ABSTRACT FROM AUTHOR]

This paper presents a novel topology for Z-source inverters (ZSI). The new Z-Source network is based on the coupled-inductors and active switched boost. Features of the topology include high voltage boost ability, single magnetic-core, low voltage stress on the active switch, and capacitors. The principles of operation, analysis, voltage and current equations of each component, and the converter voltage gain in the steady-state are presented. A comparison with other topologies has also been performed to determine the advantages and disadvantages of the proposed ZSI. Finally, experimental results of the laboratory prototype are presented to confirm the performance of the proposed topology. [ABSTRACT FROM AUTHOR]

The paper discusses in detail the inability of a circuit designer to design a single input single element-controlled universal memelement emulator. A Single input Single element-controlled universal memelement emulator would be such a configuration that can provide the realization of any of the three memelements (Memristor/Memcapacitor/Meminductor) by taking a circuit element as inductor (L), Capacitor (C) or Resistor (R) with the same input port. The analysis shows that no such circuit configuration can be built to realize such a highly flexible universal memelement emulator. It is found that by using such structures, only two ideal memelements can be realized at maximum. If these circuit structures are used to realize the remaining third memelement, then, the resulting element comes out to be a non-ideal memelement. Two circuit configurations to demonstrate this theory are also included for both charge-controlled and flux-controlled memelement emulation based on the approaches shown in this paper. [ABSTRACT FROM AUTHOR]

Meminductors are memory-based elements, which are gaining a lot of popularity as a result of their applications in widespread areas. However, due to the non-availability of their off-the-shelf ICs, designers are trying to find alternatives of meminductor emulators. This paper presents a generalized approach to designing a meminductor emulator from an active inductor circuit. An active inductor circuit having a current conveyor (CC), operational transconductance amplifier (OTA), and a grounded capacitor has been utilized. The idea is encouraged by the thought of putting memory in conventional active inductor circuits. In the proposed configuration, one additional block namely a current differencing buffered amplifier (CDBA) and an extra grounded capacitor have been used to modify the active inductor circuit into a meminductor emulator circuit. The goal is to implement a meminductor emulator employing active blocks which can be designed using commercially available ICs. Simulation results of the proposed emulator are obtained using the LTspice tool along with 0.18 µm CMOS technology parameters. The essential testimonials, pinched hysteresis loops, and non-volatility tests, confirm that the suggested circuit works as a meminductor emulator. Furthermore, the pinched hysteresis loops are observed for a large range of frequencies, verifying the wide dynamic frequency range of the suggested circuit. To assess how well the suggested meminductor emulator performs, a chaotic oscillator has been developed. [ABSTRACT FROM AUTHOR]

A new lumped capacitance model that employs fractional order operators is proposed for use on transient heat conduction problems. Details and implications of the fractional lumped capacitance model's development and application are discussed. The model is shown to agree with observed heating and cooling temperature profiles of laser aiming paper being heated by a laser under various conditions. [ABSTRACT FROM AUTHOR]

Tantalum is widely used in capacitor field in modern times. The tantalum shell of capacitor is usually obtained by deep drawing process, and adhesive wear of the shell is the main hidden danger during its deep drawing process. In this paper, ultrasonic vibration–assisted deep drawing technology is proposed to manufacture tantalum capacitor shell, in order to effectively control the adhesive wear of tantalum capacitor with the assistance of ultrasonic vibration energy. Influence of ultrasonic vibration on deep drawing force and surface forming accuracy of tantalum cup deep drawing is discussed by applying different amplitudes of ultrasonic vibration signals at different time periods. The results reveal that in the amplitude range of 3–7 μm, the amplitude of 5 μm has the best inhibition effect on adhesive wear during the deep drawing of tantalum cup, and the effect is especially obvious in the initial stage of the deep drawing process; the reduction of wearing can reach more than 22% comparing with the results without ultrasonic amplitude. [ABSTRACT FROM AUTHOR]

This paper demonstrates the controlling abilities of a large PV-farm as a Solar-PV inverter for mitigating the chaotic electrical, electromechanical, and torsional oscillations including Subsynchronous resonance in a turbogenerator-based power system. The oscillations include deviations in the machine speed, rotor angle, voltage fluctuations (leading to voltage collapse), and torsional modes. During the night with no solar power generation, the PV-plant switches to PV-STATCOM mode and works as a Solar-PV inverter at its full capacity to attenuate the oscillations. During full sun in the daytime, on any fault detection, the PV-plant responds instantly and stops generating power to work as a Solar-PV inverter. The PV-farm operates in the same mode until the oscillations are fully alleviated. This paper manifests the control of the DC-link capacitor voltage of the Solar-PV inverter with a bacterial foraging optimization-based intelligent maximum power point tracking controller for the optimal control of active and reactive power. Kundur's multi-machine model aggregated with PV-plant is modeled in the Matlab/Simulink environment to examine the rotor swing deviations with associated shaft segments. The results for different test cases of interest demonstrate the positive outcomes of deploying large PV-farms as a smart PV-STATCOM for controlling power system oscillations. [ABSTRACT FROM AUTHOR]

For decentralized electrification in remote areas, small-sized wind energy systems (WESs) are considered sustainable and affordable solution when employing an efficient, small-sized component converter integrated with a less-sophisticated, cost-effective MPPT controller. Unfortunately, using a conventional buck DC/DC converter as a MPP tracker suffer from input current discontinuity. The latter results in high ripples in the tracked rectified wind power which reduces the captured power and affects system operation especially in standalone applications which are self-sufficient and independent of grid support. Furthermore, these ripples propagate to the machine side causing vibration and torque stress which impacts turbine performance and safety. To solve this issue, a large electrolytic capacitor is placed at the buck converter input to buffer these ripples, yet at the cost of larger size, losses and reduced reliability. Oppositely, the developed C1, D4 and D6 buck converters have the merit of continuous input current at small component-size. In this paper, dynamic modelling of these three converters is developed to select the one with the least input current ripples to replace the traditional buck converter in the considered WES system. Consequently, fluctuations in the tracked power are minimized and the large buffer capacitor is eliminated. This enhances system lifetime, reduces its cost and increases tracking efficiency. Moreover, mechanical power and torque fluctuations are minimized, thus maintaining machine protection. Furthermore, a sensorless MPPT algorithm, based on converter averaged state-space model, is proposed. Being dependent on variable-step P&O algorithm, the proposed approach features simple structure, ease of control and a compromise between tracking time and accuracy besides reduced cost due to the eliminated current sensor. Simulation results verified the effectiveness of the selected converter applying the proposed MPPT approach to efficiently track the wind power under wind variations with cost-effective realization. [ABSTRACT FROM AUTHOR]

This paper proposes a discrete space vector modulation and optimized switching sequence model predictive controller for three-level neutral-point-clamped inverters in grid-connected applications. The proposed strategy is based on cascaded model predictive control (MPC) for controlling the grid current while maintaining the capacitor voltage balanced without weighting factor. To enhance the closed-loop performance, the external MPC evaluates 19 basic and 138 virtual vectors (VV) of the proposed space vector method. The optimal control voltage is then selected using an extended deadbeat method to reduce the execution time of the proposed control algorithm. By using the discrete space vector modulation principle, the VV are synthesized based on switching sequence (SS) and are divided into negative and positive SSs considering their impact on the neutral point (NP) potential. The inner MPC evaluates both types of SSs and selects the one that keeps the capacitor voltage balanced. Various controllers are evaluated and compared against the proposed control strategy. The results show that the proposed strategy improves performance without weighting factor, while maintaining a total harmonic distortion of current to be less than 2%. Compared to the modulated MPC which provides the same fixed switching frequency, the proposed controller reduces the computational burden by over 50% while also providing better NP voltage balance accuracy. [ABSTRACT FROM AUTHOR]

Various overvoltage mitigation schemes were used in literature in suppression of switching overvoltages in wind farms. However, the evaluation of how the effectiveness of these mitigation techniques would vary with the change of the wind farm topology is still un-explored territory. The main aim of this paper is to study the effectiveness of four mitigation schemes while using SF6 circuit breaker namely; R–L smart choke, R–C snubber circuit, surge capacitor and pre-insertion resistor (PIR) were studied in four different wind farm topologies; radial, single-sided ring, double-sided ring and star topologies. The topologies were based on a real wind farm located in Zaafrana, Egypt. The results showed that R–L choke to be the most effective scheme for all topologies followed by PIR, R–C snubber and surge capacitor schemes respectively. Their percentage of reduction of overvoltage ranged from 62 to 84% for R–L choke, 33–67% for PIR, 8–25% for R–C snubber circuits and 4–15% for surge capacitors. Also, it was shown that the change of the wind farm topology didn't affect the order of effectiveness of the mitigation schemes such that R–L remained the most effective and surge capacitor the least effective for all topologies. [ABSTRACT FROM AUTHOR]

In this paper, a new ultra-low-power double-inverter-based and multi-mode, high-order universal OTA-C filter is presented. The proposed circuit is designed based on the use of subthreshold biased double inverters as OTA blocks which leads to the reduction of power consumption as well as the chip size area. Furthermore, the grounded capacitors are employed in the proposed circuit to properly reduce the noise and parasitic effects of the proposed circuit. Moreover, another advantage of the proposed filter circuit is the low sensitivity of the proposed circuit performance to the values of the active and passive elements in the circuit. However, the proposed design is simulated in CADENCE using 0.18 µm CMOS technology parameters. As simulation results show, the proposed low-power filter has very good performance that can be considered as a proper universal OTA-C filter for ultra-low-power applications. [ABSTRACT FROM AUTHOR]

This paper proposes a new averaged switch model for pulse-width modulated (PWM) single-ended primary-inductor converter (SEPIC) operating in discontinuous conduction mode (DCM). The equivalent series resistance (ESR) of each energy component is considered to achieve a more precise model. The model, which is modification of the conventional averaging equation, accurately reflects both the remaining current and the actual charge on each capacitor in DCM. The proposed model utilizes a new duty ratio constraint and predicts better than previous models at high frequencies. The dependent sources of the switch components are derived from the modified averaged equation, and an implementation of the model in LTspice XVII is provided to facilitate the frequency response analysis. The frequency response of a prototype SEPIC in DCM, with an input voltage of 5 V, an output voltage of 13.5 V, and a switching frequency of 100 kHz, was experimentally measured to verify the proposed model. Simulation and experimental results demonstrate that the proposed averaged switch model solves the discrepancies at high frequencies, which was a limitation of previous models. [ABSTRACT FROM AUTHOR]

This paper proposes a smooth mode-switching method based on state trajectory control to suppress overshoot and to shorten switching time during the mode switching of LLC-C resonant converters. First, the resonant tank trajectories of the LLC and LCCL are analyzed. Second, through a transformation of the resonant tank trajectory, the optimal trajectory of the resonant tank switching is drawn. Then the switching optimization cycle time is calculated by a diagram of the optimal trajectory. Thus, the PWM conversion to the optimization cycle is controlled directly when the switching signal comes. By this control method, a smooth transition of the resonant tank voltage and current between the two modes is achieved. At last, a prototype with a rated power of 500 W is built to check the feasibility and effectiveness of the proposed switching method. Experiment results show that the current surge of the resonant tank is reduced from 12.3 to 8.6 A when the state trajectory control is applied. The voltage surge of the second resonant capacitor in parallel is reduced from 906 to 712 V. Meanwhile, the switching time is shortened by 0.21 ms, which speeds up the switching process. [ABSTRACT FROM AUTHOR]

A compact metastructure (MTS) antenna utilizing zeroth order resonance (ZOR) techniques has been reported in this paper. The proposed coplanar waveguide (CPW) based MTS antenna has made up of interdigital capacitor (IDC), split ring resonator (SRR) and strips (rectangular and U-shaped). ZOR is a magnificent technique by which small dimensions of the antenna is attained. The presented structure exhibits compact size of 0.24λ0 × 0.27λ0 × 0.024λ0, where λ0 is the free space wavelength at ZOR frequency of 4.61 GHz. In the presented paper ZOR frequency is configured by series LC parameters as it follows short-ended boundary condition. The U-shaped strip is basically used to provide capacitance with the SRR which affects the resonance frequency by controlling the series inductance and capacitance of proposed short-ended structure. It is noticed that the presented antenna exhibits working band operation at 4.61 GHz (4.16–4.8 GHz) with input reflection coefficient of − 50.32 dB at ZOR frequency. The proposed antenna achieves properties such as omni-directional and dipolar radiation pattern in xz-plane and yz-plane respectively. Measured peak gain of 2.52 dB and simulated radiation efficiency of 94.27% permits the MTS antenna to be used widely in C-band applications. The designed antenna is fabricated and experimentally verified. [ABSTRACT FROM AUTHOR]

In the paper, the applicability of decomposition products of internal insulation of high-voltage pulse capacitors is considered (aging is the reason for decomposition products of internal insulation). Decomposition products of internal insulation of high-voltage pulse capacitors can be used to evaluate their quality when in operation and in service. There have been three generations of markers of aging of insulation as in the case with power transformers. The area of applicability of markers of aging of insulation for power transformers has been studied and the area can be extended to high-voltage pulse capacitors. The research reveals that there is a correlation between the components and quantities of markers of aging of the first generation (gaseous decomposition products of insulation) dissolved in insulating liquid and the remaining life of high-voltage pulse capacitors. The application of markers of aging to evaluate the remaining service life of high-voltage pulse capacitor is a promising direction of research, because the design of high-voltage pulse capacitors keeps stability of markers of aging of insulation in high-voltage pulse capacitors. It is necessary to continue gathering statistical data concerning development of markers of aging of the first generation. One should also carry out research aimed at estimation of the remaining life of capacitors using markers of the second and the third generation. [ABSTRACT FROM AUTHOR]

In this paper, a special variable MEMS capacitor is offered to application in the telecommunication equipment especially SIW-based structures. The variable MEMS capacitor is designed with special serpentine arms around the membrane. By using these arms, the air damping and the stiffness of the capacitor are decreased. To evaluate the performance of the proposed structure, the mechanical model of it is extracted. Then the mathematical equations relevant to components such as spring constant, resonance (inherent) frequency, and especially the pull-in voltage are expressed. The static linear analysis and energy method is used to obtain the spring constant of the proposed structure. Also, the behavior of the proposed design is analyzed and simulated by applying the Intellsuite MEMS tool. The proposed design is optimized based on the dimension of the transmission line. Thus, the implementation of the MEMS capacitor is done using a gold layer of 6 μm and a 3 μm air gap. The simulation results show that, in zero bias, the natural frequency of the capacitor is 575 Hz. Also, the pull-in voltage is 1.34 V. Finally, the calculated and simulated results are compared and show that the proposed mechanical model for the proposed structure confirms its performance. [ABSTRACT FROM AUTHOR]

This paper introduces an optimized DC–DC converter that employs a modified switched inductor-capacitor technique to achieve ultra-high voltage gain for renewable energy systems. The development is based on adding one cell of modified switched inductor (MSL1) with series diodes interleaved with the main switch in the proposed DC–DC converter. The (MSL1) with capacitor operates in resonant mode to reduce current stress across the main switch when the charge in capacitor becomes zero. This approach also reduces voltage stress across the main switch, all inductors, and diodes. Furthermore, modified switched inductors (MSL2) with an auxiliary switch and a coupled capacitor are incorporated to provide double boosting voltage and to achieve high voltage gain. Additionally, a main and auxiliary switch are integrated with modified switched capacitors (MSC) to provide ultra-high voltage gain and to reduce voltage stress across auxiliary switch. Moreover, the proposed converter exhibits a continuous input current with zero pulsating, even at very low duty cycles. The advantages of the proposed converter are high efficiency, low voltage stress, and low values of inductors and capacitors when utilizing a high switching frequency. A mathematical model for the proposed converter is developed for both continuous conduction mode and discontinuous conduction mode. In addition, the PCB design for the proposed converter is presented, and experimental tests are conducted to verify the simulation and laboratory results. The proposed converter aims to boost the voltage from 20 to 40 V to a variable output voltage between 200 and 400 V, delivering 400 watts of power with an efficiency of 96.2%. [ABSTRACT FROM AUTHOR]

In this paper, a dynamic analysis of a tunable novel triple-electrode variable capacitor is presented. It is subjected to a base excitation that can act as an accelerometer with a wide measurement range. A clamped–clamped porous microbeam connected to a frame and a proof mass in the middle of it form the structure. The sensing section of the accelerometer is in the form of capacitive sensing combs in which the fixed fingers connected to the frame are subjected to a biasing DC voltage ( V S ). In the tuning section of the accelerometer, two fixed fingers (electrodes) connected to the frame are subjected to a DC tuning voltage ( V T ), and two moving free electrical charge fingers connected to the beam act as a sliding connector. A DC tuning voltage applied to the fixed electrodes generates an electrostatic force that works as a tunable voltage-sliding nonlinear spring in the structure. Coupled nonlinear differential equations of the transversal and longitudinal vibration of the structure in the presence of the base excitation are extracted. The steady-state solution of the accelerometer is obtained based on a physically based learning method that makes it possible to obtain its frequency response for the first harmony as well as for the higher harmonies and to predict primary and secondary resonances in different harmonies of the response. The transient response of the accelerometer in exposure to various types of external acceleration fields such as step, single pulse, and repetitive pulse is investigated. The frequency response of the accelerometer for different values of tuning voltage is studied. It is shown that the tuning stiffness of this voltage-sliding spring provides a highly effective solution to realize instrumentation with wide-range measurement. The presented tunability can enable the structure to act as an effective accelerometer, microresonator, energy harvester, and so on. [ABSTRACT FROM AUTHOR]

This paper describes a 10-bit digital-to-time converter (DTC) utilizing the glitch-free dual reset method and switchable supply regulation scheme for high linearity regardless of supply ripple noise and input signal speed. The proposed circuit is designed as a single-ended structure, and a delay control is configured as a thermometer code for high differential nonlinearity (DNL) with 32 × 32 array capacitors. The DTC is optimized with a 200 MHz input signal for utilizing wide bandwidth PLLs to decrease a conversion range and keep a high resolution of a time-to-digital converter to reduce the power dissipation and quantization noise, respectively. Besides, the high linearity is guaranteed in dynamic operation, which is the worst case of DTCs' control. The output jitter is 159.3 fsrms at the maximal delay, while the DTC consumes 0.603 mW with a total area of 0.0085 mm2. The dynamic range is 429 ps with 433 fs resolution with 0.066-LSB DNL and 0.506-LSB integral nonlinearity, comparable to state-of-the-art. [ABSTRACT FROM AUTHOR]

This paper presents an ultra-low-voltage 10-bit successive approximation-register analog-to-digital converter (SAR ADC) based on the binary search algorithm for biomedical applications. An energy-efficient DAC switching scheme for a fully differential SAR ADC is proposed, which achieves a 99.8% reduction in DAC switching energy compared to conventional SAR ADC. In this design, by using a dummy capacitor split technique, an attempt has been made to reduce the capacitor of the most significant bit, resulting in a 92.87% reduction in the total number of capacitors compared to conventional design. In the proposed structure, the common-mode voltage of the comparator is approximately constant. The maximum voltage variation in the proposed switching scheme is Vref/2. Additionally, power consumption has been reduced by implementing the power gating technique in the control logic part. The proposed converter with a sampling frequency of 1 kS/s and a supply voltage of 0.2 V has been designed and simulated in TSMC 65nm CMOS technology. Both analytical calculations and simulation results confirm the effectiveness of the proposed switching scheme. Ultimately, the proposed scheme achieves a power consumption of 2.08 nW and a Figure of Merit (FoM) of 5.39 fJ/conversion-step. In comparison with the state-of-the-art, the proposed design has demonstrated excellent performance in achieving optimal power. [ABSTRACT FROM AUTHOR]

In this study, three different Switched-Capacitor Enhanced boost quasi Z source (SCEq-Zs) DC–DC converters are presented, out of which the converter having a switched capacitor network positioned in series with the enhanced boost q-Zs network (SCEq-Zs-3) provides the common ground path and less output capacitor stress. This converter has a high voltage conversion ratio with low voltage stress on active and passive devices like capacitors, diodes, and the power semiconductor switch in comparison to other converters. This unidirectional hybrid switched-capacitor with a quasi Z source combination provides continuous and ripple-free source current mostly suitable for fuel cell applications. This leads to reduced voltage fluctuations at the input, providing a steady source of power to the converter. The converter is comprehensively analyzed and the operating principle along with waveforms is presented in this paper. A systematic comparison with other DC–DC boost converters is brought to view. A scaled-down 200V/200W prototype for the suggested converter is developed to verify the results of the theoretical study. A maximum efficiency of 95.85 % is measured. To demonstrate the effectiveness of the suggested converter, detailed experimental findings are presented. [ABSTRACT FROM AUTHOR]

Chain-scaling fractional-order memristors (fracmemristors) refers to the concept of implementing them in circuits. Despite its advantages, a few issues that require urgent attention remain, including the effect of input signals on its instantaneous valid frequency range, failure to find the corresponding time-domain electrical characteristic expression of the fracmemristor, and the use of several memristor emulators in circuit schematics. Accordingly, a simple circuit for implementing a chain-scaling fracmemristor (CSF) within a fixed valid frequency range is proposed in this paper. First, a CSF circuit configuration with a fixed valid frequency range is described. Subsequently, a simple circuit schematic of an incremental/decremental CSF is presented, and the corresponding time-domain electrical characteristic expressions of the fracmemristor are obtained. Finally, rich theoretical analysis results are obtained along with the CSF circuit implementation. The accuracy of the theoretical analysis is verified experimentally. In this study, we developed a method to achieve a CSF with a fixed valid frequency range through the replacement of all the capacitors with memcapacitors, which also facilitated the design of circuit schematics. [ABSTRACT FROM AUTHOR]

New energy integration and flexible demand response make smart grid operation scenarios complex and changeable, which bring challenges to network planning. If every possible scenario is considered, the solution to the planning can become extremely time-consuming and difficult. This paper introduces statistical machine learning (SML) techniques to carry out multi-scenario based probabilistic power flow calculations and describes their application to the stochastic planning of distribution networks. The proposed SML includes linear regression, probability distribution, Markov chain, isoprobabilistic transformation, maximum likelihood estimator, stochastic response surface and center point method. Based on the above SML model, capricious weather, photovoltaic power generation, thermal load, power flow and uncertainty programming are simulated. Taking a 33-bus distribution system as an example, this paper compares the stochastic planning model based on SML with the traditional models published in the literature. The results verify that the proposed model greatly improves planning performance while meeting accuracy requirements. The case study also considers a realistic power distribution system operating under stressed conditions. [ABSTRACT FROM AUTHOR]

Nowadays, the utilization of Flexible Alternating Current Transmission System (FACTS) devices remains a better alternative for improving Available Transfer Capability (ATC), and it further minimizes the system loss in aggressive electrical power systems. It could minimize the cost of the new transmission line construction and also enhance the utilization rate. This paper introduces a new optimization-assisted ATC enhancement model by determining the optimal placement and compensation level of a Thyristor Controlled Series Capacitor (TCSC) device. As a novelty, a unique Improved Sea Lion Optimization (I-SLnO) model is established, which is an improved form of the conventional Sea Lion Optimization (SLnO) model. The evaluation is performed in IEEE-14 & IEEE-39 test bus systems to analyze the effectiveness of the suggested approach in terms of convergence analysis, ATC enhancement, and so on. [ABSTRACT FROM AUTHOR]

This paper presents a high-resolution 18-bit SAR ADC with a high 10-bit capacitor DAC and a low 8-bit resistor DAC. The total required number of the unit capacitors is decreased to 512. Foreground digital calibration based on capacitive recombination is introduced to improve linearity. Preamplifiers and output offset storage(OOS) enhance the noise and offset performance of the comparator. As a result, the design under 180 nm process achieves a signal-to-noise and distortion ratio(SNDR) of 105.5dB and a spurious-free dynamic range (SFDR) of 116.3dB under 1 MS/s sampling rate with a single channel. The effective number of bits (ENOB) can reach 17.23 bits with a Nyquist-rate input while consuming 46 mW from a 5 V supply. The resultant Schreier and Walden figures of merit (FoM) are 178.92 dB and 295.34 fJ/conversion-step, respectively. The proposed SAR ADC occupies an actual area of 3850 μ m by 2810 μ m. [ABSTRACT FROM AUTHOR]

Model predictive control (MPC) is recognized as an efficient control method for the modular multilevel converter (MMC), owing to its advantages, such as good robustness, rapid dynamic response, and multi-objective control. However, due to the coupling relationship between the ac-side current and the circulating current, the existing MPC has an impact on the ac-side current while suppressing the circulating current. In this paper, the relationship between the ac-side current performance and circulating current suppression is discussed in detail, and a three-stage MPC (TS-MPC) strategy is proposed to optimize the comprehensive performance. With the ac-side current control, circulating current control, and comprehensive optimization control, the optimum performance of both the ac-side current and circulating current suppression is realized while maintaining a low computational burden. Moreover, a grouping sorting algorithm is designed to reduce the calculation burden and to balance the capacitor voltages. The steady-state and transient performances of the proposed TS-MPC strategy have been verified by experimental results, which validates its correctness and effectiveness. [ABSTRACT FROM AUTHOR]

Modular multilevel converter-based solid-state transformers (MMC-SST) usually use the input series output parallel structure or the dual active bridge (DAB) structure. These two structures suffer from low power supply reliability and high economic costs, respectively. Therefore, based on hybrid frequency modulation, this paper proposes an arm integrated double capacitor submodule (AIDCSM)-type MMC-SST topology. This topology effectively reduces the number of switching devices by integrating the submodule arms, while enabling the topology to possess DC short-circuit fault ride-through capability. When compared to the DAB-type MMC-SST with half-bridge submodules, the proposed AIDCSM-type MMC-SST saves 2/5 switching devices and 1/2 high-frequency transformers, and enables uninterrupted operation under DC short-circuit faults. At the same time, the control strategy of the proposed AIDCSM-type MMC-SST is thoroughly investigated under both normal operating and DC short-circuit conditions. Simulation and experimental results demonstrate the correctness and effectiveness of the proposed topology and control method. [ABSTRACT FROM AUTHOR]

Modular multilevel converters (MMC) have the characteristics of high modularity, good availability and high-power quality. Thus, they are widely used in medium and high-power applications. To meet large capacity application requirements, a large number of capacitors is applied in parallel and series. However, capacitors are one of the most vulnerable components in MMCs. To identify abnormal capacitors, a condition monitoring method for capacitors is proposed in this paper using the cumulative sum detection of the sliding window algorithm. First, the bilateral cumulative sum algorithm of the sliding window is proposed to extract the switch-on time and switch-off time of the submodules (SMs). Second, the capacitance is calculated using the monitored capacitor voltage and arm current during the switch-on status. Finally, the accuracy and effectiveness of the proposed method are verified by an MMC system operating condition simulated experiment platform. The proposed condition monitoring method simplifies the calculation of capacitance with a high accuracy by removing the requirement of measuring the switching signal. In addition, it does not have an adverse influence on the normal operation of MMC systems. [ABSTRACT FROM AUTHOR]

This article presents a novel 3-Φ inverter that operates from a single direct current source and is based on the idea of switched-capacitor (SC) techniques. Each phase leg of the proposed topology (PT) consists of eight switches, two capacitors, and a diode. This configuration enables the generation of seven levels (line-to-line) voltage waveforms. The proposed design has several advantages, such as the capacitors' natural balancing, the ability to boost, minimum voltage stresses on the power switches, and fewer switching components. When compared to the conventional two-stage design, single-stage dc–ac power converters with boost capabilities present an intriguing option. This paper introduces a novel boost-type inverter for use in a wide variety of applications, including rolling mills, fans, pumps, maritime appliances, mining, tractions, and more. The study explains the proposed design, principle, control mechanism, and loss analysis in great depth. The advantages of the PT have been demonstrated through comparison with recently published SC topologies. Finally, a 1550-W downscale prototype is used to experimentally verify its viability and performance, with an estimated efficiency of around 96.6%. [ABSTRACT FROM AUTHOR]

The health management of railway signal equipment in the high-speed railway is a key link between intelligent operation and maintenance. Accurately predicting the health state of compensation capacitors is of great significance to ensure the reliable work of track circuits. This paper proposes an improved deep neural network algorithm focusing on the problem of long-term accurate health forecasts for compensation capacitors. First, establishing a transmission state model for degradation mechanism mining, the difference function that can quantitatively evaluate features is defined by piecewise processing cab signaling receiving voltage. Introducing the degradation model, predictive driving under both model and data is implemented. Then, the convolutional neural networks and bidirectional long–short-term memory are combined and improved to construct a novel artificial intelligence combination strategy, while parameters are optimized based on the sparrow search algorithm. Finally, facing the conditional repair of compensation capacitors, we set a reasonable threshold for the occurrence of hidden dangers to complete fault warning. This novel and practical approach effectively explores the procedure of prognosis and health management, while the refined maintenance will better utilize current monitoring information, helping the intelligence and accuracy of safety control decision-making. [ABSTRACT FROM AUTHOR]

In the realm of medium/high voltage applications, the modular multilevel converter with an active power filter (APF-MMC) emerges as a technology that eliminated the inherent voltage fluctuations of larger sub-module (SM) capacitors. However, the introduced APF circuit in each phase can only deal with power in even frequencies, and the APF-MMC cannot be directly applied in the field of motor drives with low-frequency operation. In this paper, based on the APF-MMC topology, by adding two high-frequency variables as control degrees of freedom, the base frequency power is transferred to high-frequency power, which can considerably minimize the capacitor voltage ripple in the low-frequency region of the topology. In addition, the influence of the injected high-frequency variables on the output characteristics of the topology is eliminated by controlling the APF circuit as hardware degree of freedom. Its equivalent circuit and operating principle are introduced in detail. Concurrently, a control method is proposed for the APF circuit, ensuring seamless operation of the converter. Finally, through a combination of simulation and experimental results, it is demonstrated that the APF-MMC topology surpasses the conventional MMC in its efficacy under low-frequency operation. [ABSTRACT FROM AUTHOR]

Currently, many inverters employ inductors to boost the AC voltage. However, this leads to increased current distortion and limits the voltage boosting capability of the inverter. To address the above issue, a triple two-level inverter is proposed in this paper. The proposed inverter adopts a switched-capacitor boost circuit to boost the AC output voltage and to generate a multi-level voltage. Simultaneously, a three-phase full-bridge circuit is assigned to convert the DC voltage into AC voltage. In addition, a novel space vector modulation strategy is introduced to achieve capacitor voltage self-balance. Finally, simulation and experimental platforms have been established to verify the effectiveness of proposed inverter. The obtained results show that the proposed inverter meets the requirements for the expected inverter. [ABSTRACT FROM AUTHOR]

This paper proposes a unique sensor for detecting total ionizing dose (TID) on metal–oxide–semiconductor (MOS) devices. The proposed capacitive radiation sensor is based on commercial 180 nm complementary metal-oxide semiconductor (CMOS) technology. The sensor parameters of 180 nm length (L) and 20 nm oxide thickness (TOX) have been finalized based on simulation and mathematical analysis. Low and high radiation doses ranging from 100 rad to 1 Mrad are used to characterize it. The sensor's sensitivity for 0–10 krad is 20 mV/krad, 10 krad–100 krad is 3.9 mV/krad, and 100 krad–1 Mrad is 0.6 mV/krad when threshold shift is considered into account. Analysis of fixed oxide charge and interface trap charge generation due to ionizing radiation is done. Because interface traps are crucial to device performance, this device is evaluates using traps between 1 E06 cm−3 and 1 E14 cm−3 for realistic performance. Every interface trap exhibits a threshold voltage (VT) shift. Visual technology computer-aided design (TCAD) simulator was used to build, study, and evaluate a capacitive radiation sensor that might be used as a dosimeter for TID monitoring. [ABSTRACT FROM AUTHOR]

In this paper, we present a new structure of a micromachined tunable capacitor using a combination of piezoelectric and electrostatic parallel-plate actuators. Electrostatic parallel-plate capacitors have a low capacitive tuning ratio due to the "pull-in" instability. Therefore, to increase the capacitive tuning ratio, an electrostatic parallel-plate actuator, as well as a piezoelectric two-directional actuator, was used in this work. To verify the theoretical results, they were compared to the simulation results achieved by COMSOL and HFSS software. According to the analytical and simulation results, the proposed structure has a maximum capacitive tuning range of 2180% by applying 5.6 V for the electrostatic parallel-plate actuator and ± 8 V for the piezoelectric actuator. [ABSTRACT FROM AUTHOR]

This paper presents a scheme to diagnose soft faults in switched-capacitor (SC) filters embedded in the PSoC1 processor from Infineon. The work addresses faults that cause reductions in the values of the filter capacitors due to degradations produced by electrical stress. The diagnosis scheme employs the step response of the pass band output of the filter under test. After simple signal processing steps, the test signal is delivered to a nearest neighbor (1NN) classifier that uses a similarity measure (dynamic time warping) to compare the incoming waveform with patterns stored in a dictionary. The signals in the dictionary are obtained from the filter's step response (using its transfer function) under fault-free and faulty conditions. The diagnosis characterization procedure consists of evaluations at different abstraction levels, including transfer function level simulations in MatLab (over a wide range of faulty conditions), SPICE level simulations, experimental fault injection, and on-chip signal measurements using the internal resources of the processor. All the simulations consider non-ideal effects like noise, jitter, thermal drift, capacitors mismatch, and inter-chip variation in offset voltages at a reasonable computational cost. The evaluations, performed at different abstraction levels, show an excellent performance of the method for diagnosing the addressed faults. [ABSTRACT FROM AUTHOR]

Integrating distributed generations (DGs) into the radial distribution system (RDS) are becoming more crucial to capture the benefits of these DGs. However, the non-optimal integration of renewable DGs and shunt capacitors may lead to several operational challenges in distribution systems, including high energy losses, poor voltage quality, reverse power flow, and lower voltage stability. Therefore, in this paper, the multi-objective optimization problem is expressed with precisely selected three conflicting goals, incorporating the reduction in both power loss and voltage deviation and improvement of voltage stability. A new index for voltage deviation called root mean square voltage is suggested. The proposed multi-objective problems are addressed using two freshly metaheuristic techniques for optimal sitting and sizing multiple SCs and renewable DGs with unity and optimally power factors into RDS, presuming several voltage-dependent load models. These optimization techniques are the multi-objective thermal exchange optimization (MOTEO) and the multi-objective Lichtenberg algorithm (MOLA), which are regarded as being physics-inspired techniques. The MOLA is inspired by the physical phenomena of lightning storms and Lichtenberg figures (LF), while the MOTEO is developed based on the concept of Newtonian cooling law. The MOLA as a hybrid algorithm differs from many in the literature since it combines the population and trajectory-based search approaches. Further, the developed methodology is implemented on the IEEE 69-bus distribution network during several optimization scenarios, such as bi- and tri-objective problems. The fetched simulation outcomes confirmed the superiority of the MOTEO algorithm in achieving accurate non-dominated solutions with fewer outliers and standard deviation among all studied metrics. [ABSTRACT FROM AUTHOR]

Microgrids having renewable energies like wind and solar necessitate competent control and optimization to ensure system frequency stability. The intermittent behavior of the wind and solar influences the system frequency badly. This issue is appearing prominent in case of multi-interconnected microgrids. Hence, in this study, a fractional calculus-based integral tilt derivative with filter (ITDF)-based frequency regulation control strategy is utilized in a multi-microgrid. Here, the two unequal control zones with renewable energy and thermal generating power sources are connected through AC/DC parallel interfaces. A recent Jaya optimization method is exploited to tune the design variables of the controller. The comparative analyses of the dynamic response of the suggested control strategy with some existing control strategies like proportional integral derivative with filter (PIDF)/tilt integral derivative with filter (TIDF)/integral proportional derivative with filter (IPDF) exhibit the effectiveness of the suggested control strategy to suppress the frequency fluctuations. This paper also implements an accurate high-voltage direct current (AHVDC) line model and evaluates the results of the system by replacing conventional HVDC with AHVDC tie-line. Further, to enhance the frequency regulation, the inertia emulation controlling technique is executed which permits the exploitation of the accumulated energy in capacitors of HVDC interface for load frequency control. A comparative analysis shows the better dynamic response with AHVDC link with inertia emulation control strategy in parallel with AC link in comparison to conventional HVDC. [ABSTRACT FROM AUTHOR]

A general topology for realizing nth order voltage-mode universal filter responses with multiple-input and single-output using only plus type differential difference current conveyor (DDCC +) is presented in this paper. The proposed nth order filter circuit is implemented with n number of DDCC + s, n number of capacitors, and n number of resistors. All the five filter responses, namely low-pass, high-pass, band-pass, band-stop, and all-pass, can be realized simultaneously for both odd and even order of filter with the same generalized topology. The proposed circuit offers the following advantages: the circuit uses only plus-type of DDCC, no critical matching constraints on passive and active elements, universality properties, no requirement to change the hardware for the realization of odd and even order of the filter, fully cascadable, components used are canonical in the count, use of all grounded resistors except one, and the use of only grounded capacitors. Simulations are performed for the third and fourth order of the universal filter to check the various results and responses using PSPICE 180 nm CMOS TSMC technology parameters. The simulated results agree well with the theoretical predictions. The third-order and the fourth-order filter circuits consume low power, 143 µW, and 189 µW, respectively. Finally, the paper concludes with the comparison of various parameters with the earlier implementations. [ABSTRACT FROM AUTHOR]

A detailed analysis of the recent developments on the realization of fractance device is presented. A fractance device which is used to exhibit fractional order impedance properties finds applications in many branches of science and engineering. Realization of fractance device is a challenging job for the people working in this area. A term fractional order element, constant phase element, fractor, fractance, fractional order differintegrator, fractional order differentiator can be used interchangeably. In general, a fractance device can be realized in two ways. One is using rational approximations and the other is using capacitor physical realization principle. In this paper, an attempt is made to summarize the recent developments on the realization of fractance device. The various mathematical approximations are studied and a comparative analysis is also performed using MATLAB. Fourth order approximation is selected for the realization. The passive and active networks synthesized are simulated using TINA software. Various physical realizations of fractance device, their advantages and disadvantages are mentioned. Experimental results coincide with simulated results. [ABSTRACT FROM AUTHOR]

In this paper, shunt capacitors are effectively placed in two radial distribution networks with 69 and 85 nodes for the purpose of reducing the sum of capacitor investment cost and energy loss cost by using a novel metaheuristic, called slime mould optimization algorithm (SMOA). The main duty of SMOA is to find the most suitable position of the shunt capacitors and to determine optimal generation of the shunt capacitors over a year with three load levels. In addition to comparison with previous methods in the literature, SMOA is also compared to two other applied methods including bonobo optimization algorithm (BOA) and tunicate swarm algorithm (TSA). The novelty of the paper is to apply three new methods in which SMOA and TSA were developed in early 2020 and BOA was introduced in 2019. The three methods can reach the same success rate of 100%, but SMOA is more powerful. In fact, SMOA can reach better minimum, mean and maximum total costs, faster convergence speed and more effective stability of fifty independent runs. BOA and TSA cannot find one the same good solution as SMOA even they are run 50 times for each study case. Comparison with previous methods in the literature indicates that SMOA can find better position and more suitable generation for shunt capacitors and it can get less total cost, and use smaller population size and a lower number of iterations. The best result from SMOA is also the main contribution of the study and it is recommended that SMOA should be used for placing capacitors in radial distribution networks. [ABSTRACT FROM AUTHOR]

In this paper, we present the circuit configuration that can perform as a dual-mode (i.e., both voltage-mode and current-mode) multifunction filter as well as a dual-mode quadrature oscillator by slightly modifying the design. The presented configuration includes only two voltage differencing transconductance amplifiers and two grounded capacitors, resulting in a resistor-less construction. The dual-mode multifunction filter with one input and three outputs provides three standard biquadratic filter functions: highpass, bandpass, and lowpass, as well as independent electronic adjustment of its quality factor. The circuit can also be used to implement a dual-mode quadrature oscillator with orthogonal electronic control of the oscillation condition and the oscillation frequency. Simulation results based on 0.25-μm level-7 TSMC CMOS technology parameters are used to evaluate the behavior of the proposed dual-mode multifunction biquad and quadrature oscillator circuit. [ABSTRACT FROM AUTHOR]

In this paper, both grounded and floating type novel designs of inductance simulator, capacitance multiplier simulator and frequency-dependent negative conductance (FDNC) simulator are proposed. Current follower differential input transconductance amplifier (CFDITA) is utilized as active building block in the realization of the proposed works. All the proposed ideas employ grounded capacitor(s) as only passive element(s) which make these designs suitable to modern integration technology. The proposed designs are electronically tunable as transconductance of CFDITA can be varied with bias current. Additionally, the proposed designs have no matching constraints. PSPICE with 0.18 µm CMOS technology process parameters is used to perform simulations of the proposed designs. Experimental verification of functionality of the proposed grounded inductance simulator is also done using commercially available ICs, AD844 and LM13700. The applications of the proposed floating inductance simulator as band-pass filter and band-reject filter are explored. Additionally, proposed grounded FDNC simulator is also tested in third-order high-pass filter to demonstrate the applicability aspects. [ABSTRACT FROM AUTHOR]

The fabrication of packaged, flexible, and planar fractional-order capacitors (FOCs) using copper foil electrodes and thin films of PVDF polymer nanocomposite dielectric is presented in this paper. An extensive comparison of FOC properties is made by using two separate conductive fillers, i.e., graphene nanosheets (GNS) and reduced graphene oxide (rGO). Similar fractional-order is observed at a particular filler loading in both types of FOCs; however, differences in the pseudocapacitance values and width of the constant phase (CP) zone exists. Fractional order α (alpha) is reported to vary in the range 0.61–0.87 in impedance measurements made on individual samples of rGO/PVDF and GNS/PVDF FOCs and series/parallel connections of two identical-order FOCs. For series/parallel connection of arbitrary-order FOCs, α varies from 0.61 to 0.83. Phase angle variation ranges from − 56.2° to − 79° for standalone pure FOC samples, whereas, for series/parallel connection of identical or arbitrary order FOCs, phase ranges from − 54.94° to − 77.75°. Phase ripple varies between ± 1.1° and ± 4.8°, and a maximum CP zone of 4 decades (1 kHz to 10 MHz) for the fabricated samples is reported. Industrial manufacturing of large-value capacitors demands materials to be flexible to enable rolling of large-area electrodes into a miniature device. FOCs fabricated in this work match the design specifications of commercial standard thin film capacitors and show high-value capacitances as well as flexibility of materials and structure. [ABSTRACT FROM AUTHOR]

This paper presents an area-efficient split capacitive array architecture for high-resolution successive approximation register (SAR) analog-to-digital converters (ADCs). The equivalent value method is proposed to adjust the bridge capacitance as an integer value so that the bridge capacitance can match well with the unit capacitance. A split capacitive array with redundancy is utilized in a 16-bit SAR ADC and the total required number of the unit capacitors is only 452. Four proposed static pre-amplifiers enhance the noise performance and the offset performance of the comparator and a proposed dynamic latch enhances the speed performance. As a result, the 180 nm design can achieve a 1 MS/s sampling rate with a single channel. The spurious-free dynamic range is 105.85 dB while the effective number of bits can reach 15.78 bits with a Nyquist-rate input while consuming 32 mW from a 5 V supply. The resultant Schreier and Walden figures of merit are 168 dB and 457 fJ/conversion-step respectively. The proposed SAR ADC occupies an active area of 4200 μ m by 2200 μ m . [ABSTRACT FROM AUTHOR]