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A single-inductor multiple-input multiple-output converter is proposed in this paper that can be used in low-power systems due to low output current and voltage. This converter is implemented discretely, and only one microcontroller is employed to control the system. The unique zero-current switching (ZCS) technique considered in this paper is such that only by reading the inductor's left-side voltage the optimal value of the inductor discharge duty cycle is determined. This method can be generalized to low-power and high-power converters, whether implemented and designed as discrete or integrated. This converter works in discontinuous conduction mode. It uses pulse width modulation control and the time-multiplexing control method, which makes the system have high efficiency and makes the cross-regulation problem between the converter's outputs tiny. The control algorithm considered in this converter is digital, which determines the optimal charge and discharge duty cycles. Also, the switching frequency of this converter is constant, relatively low, and equal to 5 kHz. The efficiency of this converter has reached 91.6% by using the ZCS technique and other mentioned control methods. [ABSTRACT FROM AUTHOR]

Nowadays, multilevel inverter (MLI)-based induction heating (IH) technology is the best-suited option in many domestic, commercial and medicinal applications because of its higher efficiency, low cost, fast heating and lower electromagnetic interference (EMI). This paper presents reduced components count high-frequency (HF) single phase five-level (5-L) MLI for IH applications. The working methodology of the proposed system has been analyzed in the multicarrier phase disposition pulse width modulation (MC-PD-PWM) method in high switching frequency i.e., 10 kHz. In addition, the proposed topology can produce output voltage twice of input voltage without any external source. Moreover, the detailed power loss and reliability analysis have been evaluated for the proposed system. In terms of switch count and efficiency, the single-phase 5-L inverter architecture is compared to some conventional and current topologies. Finally, to validate and justify the operation of the proposed system, the simulation and experimental results of five-level inverter are presented. [ABSTRACT FROM AUTHOR]

Cascaded H-bridge inverters, which belong to strongly nonlinear time-varying system with complex dynamics, have been widely used in high-voltage and high-power engineering fields. In this paper, a carrier phase-shifted sinusoidal pulse-width modulation cascaded H-bridge inverter is taken as an example with piecewise analysis to establish the discrete iterative mathematical model. Furthermore, the nonlinear dynamic behavior of this inverter system is investigated using folding diagrams, spectrum diagrams, bifurcation diagrams, Lyapunov exponents, etc. We find that this inverter can exhibit multiperiod bifurcation, tangential bifurcation and paroxysmal chaos within certain ranges of control coefficients and other circuit parameters, which will influence the system's stability seriously. On the basis of this discovery, the sinusoidal time-delay feedback control method is proposed. The difference between the load current of the controlled object and its own delay is used to form a feedback term, which is then fed into the sine function and proportional link to obtain the control term. Moreover, the Jacobian matrix of this feedback inverter system is derived, and the constraints on the feedback control coefficient are obtained based on the Jury criterion. Simulation results have verified the effectiveness of such a sinusoidal time-delay feedback control method, which can improve the stability and anti-interference of the system. The research can be used to provide some reference and guidance for the circuit design, debugging and control of cascaded H-bridge inverters. [ABSTRACT FROM AUTHOR]

This paper presents a novel jitter reduction technique for a voltage-controlled ring oscillator (VCRO). This technique is helpful in employing VCRO-based circuits like Analog to Digital Converter (ADC), Phase Locked Loop (PLL) and time-based circuits whose performance is severely degraded by high jitter. In the proposed technique, the jitter is extracted using Excess Phase Discrimination (EPD) block and is transformed into Pulse Width Modulated (PWM) signal, which is then fed into the Phase Compensator (PC) block. This block reduces the jitter by about half its value after enabling the Single Ended Injection Locking (SEIL). The proposed work is designed in SCL 180 nm CMOS technology at 1.8 V supply. On enabling the proposed circuit, the Root Mean Square (RMS) jitter reduces from 5.94 to 2.58 ps (about 56%) for VCRO running at 58 MHz and consumes a total power of 375.84 μ W. The overall performance of the proposed circuit does not vary much in the post-layout simulations, hence demonstrating the effectiveness of the proposed technique. [ABSTRACT FROM AUTHOR]

Multilevel inverters have emerged as a viable alternative for various power electronic applications. It offers significant features in terms of reduced total harmonic distortion (THD) due to more number of output voltage levels, lower filter size, and voltage stress and reduced switching losses when compared to conventional two-level inverters. The classical topologies such as neutral point clamped, flying capacitor and cascaded H-bridge (CHB) are very popular for industrial applications. All these topologies have limitations in terms of more component count, capacitor voltage balancing for increased number of voltage levels. In this regard, multi-level DC link (MLDCL) inverter has been introduced as an improvement with respect to CHB MLI in terms of reduced switch count and is considered here for the study. This paper presents a single-phase MLDC link inverter with a modified carrier-based level-shifted phase disposition sinusoidal pulse width modulation (LS-PD-SPWM) technique. The proposed novel carrier PWM is compared with the conventional modulation techniques in terms of THD. The performance of the proposed modulation technique is analyzed through simulation studies in MATLAB software. A laboratory prototype model is developed in order to validate the experimental results. [ABSTRACT FROM AUTHOR]

This paper presents the fuzzy-based Space Vector Pulse Width Modulation (SVPWM) for 5-level Neutral Point Clamped inverter with hybrid energy source fed grid connected system. The proposed scheme is energized using Photovoltaic and Wind energy system combination. The Neural Network-(NN) based Maximum Power Point Tracking algorithm (MPPT) has been implemented to track maximum power under different operating conditions. First, we proposed fuzzy-based SVPWM, which is developed for 5-level NPC inverter to provide voltage and current control, reduced THD, predetermined switching pattern, capacitor voltage unbalance minimization and maintain good control under nonlinearities and suspicions of PV-Wind energy connected hybrid system. Second, we proposed the inverter output voltage, which has been synchronized with grid connected system using split inductor (SI). The reference voltages for SVPWM implementation were obtained using feedback current control method. Third, we proposed different solar radiations, the proposed system has attained better performance by trailing maximum power from hybrid energy system. The simulation and experimental responses have been validated using Matlab/simulink and FPGA processor. [ABSTRACT FROM AUTHOR]

This paper introduces a new premium multilevel inverter (MLI) topology with cascaded H-Bridge and series-parallel connected switches to synthesize the fundamental sine wave with various levels of voltage. The component count is decreased by reducing the number of power switching devices, optoisolators, voltage gate drivers, snubber and filter circuits. The combination of two power switches and a separated DC (SDC) source is called an SDC module. Five SDC modules are required for a 63-level MLI and six SDC modules are required for a 127-level MLI. In this paper, both a 63-level and a 127-level filter-less single-phase MLIs are deliberated. The switches are controlled by employing a newer pulse width modulation (PWM) technique called periodic reduced digital carrier level shift PWM (PRDCLSPWM). As the number of levels increases to a greater extent, the total harmonic distortion diminishes without the need of filter circuit and the performance level also increases. Comparative analysis of proposed 63-level and 127-level MLIs topology with the conventional and modern topologies has been presented in terms of power switches, gate driver circuit requirement, DC voltage sources and THD limits. PRDCLSPWM scheme is derived and analyzed for the proposed 63-level and 127-level MLIs to eliminate low-order and high-order harmonics. Moreover, the performance of the proposed modulation scheme is compared with the most commonly used schemes. The modeling and simulation are done with MATLAB/SIMULINK 2016a. [ABSTRACT FROM AUTHOR]

In this paper, the design of a fuzzy rule-based MDPSM controlled buck converter is analyzed. Power factor improvement and harmonic minimization for the buck converter connected through the variable load with a fuzzy rule are discussed and simulated. The MDPSM controlled converter is supplied with 230 V and reaches 15 V as output. The converter output, always connected with nonlinear loads, causes less power factor with more harmonics and gives less power quality. Active PFC with a fuzzy-based voltage controlled power factor controller is designed to reduce total harmonics and to raise the power factor value equal to unity. The fuzzy-based MDPSM controller was designed using MATLAB Simulink. Controller output waveforms are examined and analyzed with other controller performances. The converter is rated with 2 mA, 0.5 mH and 212 μ F values with output power 48 W. The converter is tested for different resistive loads and inductive loads. [ABSTRACT FROM AUTHOR]

A multilevel inverter (MLI) with reduced number of power devices, especially for the higher output levels, is presented in this paper. The generalized topology for (2 n + 1) level MLI is developed with symmetrical isolated dc sources and (n + 3) number of switches. A five-level MLI is developed with five power switches and then by adding each one additional switch two more levels are added in the output voltage waveform. With the help of lookup table, the working principle of the proposed five-level MLI topology is explained. Sinusoidal pulse width modulation–phase disposition control technique has been used to get a minimal total harmonic distortion (THD). The proposed MLI topology is simulated on the MATLAB platform. The laboratory prototype is developed for five-level MLI, and the experimental results obtained validate the simulation studies. The dSPACE 1104 is used for generating gate pulses in case of experimentation. The output voltage and current THDs obtained are 9.20% and 4.60%, respectively; the harmonics are mitigated more with five-level inverter. The proposed topology is compared with the cascaded H-bridge multilevel inverter. [ABSTRACT FROM AUTHOR]

The paper proposed a high efficiency boost converter with constant voltage (CV) and constant current (CC) modes. The selection of CV or CC working mode is based on the requirement, and the transient time from CV to CC mode is 230μs. The boost converter is particularly for the use of Li-ion battery portable devices. High efficiency is obtained by sleep/burst mode under light load and pulse width modulation (PWM) mode under heavy load. The quiescent current of the whole chip can be down to 6μA when the converter enters the standby mode. The converter has been made of 0.35μm complementary metal-oxide semiconductor (CMOS) process. Experimental results show that the peak efficiency is 98.2% at a 1.5A output current and a 4.2V input voltage. [ABSTRACT FROM AUTHOR]

This paper proposes a dual-mode controlled pulse width monostable multivibrator used for analogue signal processing applications that employs two differential voltage current conveyors (DVCCs), four passive components and an analogue switch. Unlike the traditional operational-amplifier-based monostable multivibrators, the proposed circuit contributes a dual-mode controlled scheme for adjusting the output pulse width through a voltage source and a grounded resistor. This paper discusses several previous designs and presents the circuit operations, related governing formulas, non-ideal effect problems, design considerations, and experimental examples of the proposed circuit. A prototype circuit was implemented, and commercially integrated circuits and discrete passive components were used to execute the experimental tests. The features of the proposed circuit are discussed, and the experimental results indicated that the circuit is feasibly used in dual-mode controlled pulse width for the output pulse and were consistent with those of the theoretical analyses. [ABSTRACT FROM AUTHOR]

In order to achieve high efficiency in a wider load range, a PWM/PFM/Power-Saved mode dc–dc buck converter is proposed. The mode switching technique is based on an accurate power loss model consisting of critical components/parameters: The size of the power transistor and the ON/OFF status of power-hungry subcircuits. The circuit of mode switching technique is achieved by the reference, pulse skipped modulation (PSM) comparator and feedback resistors, and its own consumption of quiescent current is extremely low. At ultra-light load, by detecting the ZCD duration and the ripple of the output, the system can switch to the Power-Saved-Mode. The proposed buck converter was implemented by using a 0.18 μ m CMOS process. It achieves a peak efficiency of 97% and > 90% efficiency from 100 μ A to 600 mA. A 360 nA quiescent current is achieved. With a low output ripple of less than 60 mV, the input voltage range and regulated output voltage are 3.6–5 V and 1.2–3.3 V, respectively. [ABSTRACT FROM AUTHOR]

In this paper, a modified sinusoidal pulse width modulation (MSPWM) technique and a modified single-phase H-bridge seven-level inverter is proposed. The switching pulses for the proposed seven-level inverter are generated using a single triangular carrier waveform, a fully rectified sinusoidal signal, and three stepped reference signals (Uref1, Uref2 and Uref3). Using optimization technique, the magnitude of the stepped reference signal is determined so that the total harmonic distortion (THD) of the output voltage waveform is minimum and the fundamental component, RMS value of the voltage is improved for a given modulation index Ma as compared to the sinusoidal pulse width modulation (SPWM). By the implementation of the new scheme, the seven-level of the inverter output voltage level (+Vdc, +2Vdc/3, +Vdc/3, 0, −Vdc, −2Vdc/3, −Vdc) is obtained for any given modulation index. Similarly, if only two stepped reference signals are used then the inverter will act as a five-level inverter for any modulating index Ma. The proposed MSPWM and seven-level inverter are simulated on MATLAB/SIMULINK for R, R-L load and on a single-phase capacitor-start and capacitor-start-run Induction Motor. [ABSTRACT FROM AUTHOR]

This paper presents the analysis, design and implementation of a closed-loop high-gain switched-capacitor-inductor-based inverter (SCII) by combining a sinusoidal pulse-width-modulation (SPWM) controller and phase generator for realizing the step-up inversion and regulation. The power part is composed of two cascaded sub-circuits from source to output voltage : (i) SCI booster (one resonant inductor, 4 pumping capacitors and 7 switches regulated by phase generator) and (ii) DC-link inverter (one filter capacitor and 4 switches controlled by SPWM), in order to provide a wide step-up output range of as: for DC-AC conversion, where () is the ratio cycle of charging the inductor (e.g., the maximum of reaches 13.8 times voltage of while ). Here, by using the phase generator, the maximum of step-up gain can be regulated for fitting the need of AC load. Further, the SPWM controller is employed to enhance regulation capability for the different amplitude and frequency of output, as well as robustness to loading variation. Some theoretical analysis and design are included: formulation, steady-state analysis, conversion ratio, power efficiency, inductance and capacitance selection, circuit stability and control design. Finally, the performance of SCII is simulated, and verified experimentally on the implemented prototype circuit, and the results are illustrated to show the efficacy of this scheme. [ABSTRACT FROM AUTHOR]

In this paper, a DC-link voltage tuning algorithm is introduced to control the shunt active filter (SAF) with sinusoidal and trapezoidal power supplies. The purpose of the proposed optimization algorithm is for tuning the PI controller and reducing the harmonics level. Artificial bee colony (ABC) algorithm is introduced for tuning the gain of the controller and the voltage variation of power converter by using PWM pulses. It regulates the DC-link voltage as per the signal harmonics and the active power loss of the system is reduced. Therefore, the accurate compensation current is injected by the SAF devices. The proposed ABC-PI controller-based harmonic compensation method is implemented in MATLAB/Simulink platform. Then, the Total Harmonic Distortion (THD) and the power factor are evaluated. The results of the proposed method are compared with PI controller and PSO-PI controller. The proposed method has fast DC-link voltage response, low THD and good power factor. [ABSTRACT FROM AUTHOR]

The paper considers a realization of quasi-sliding mode control for DC-DC boost-type converter on ATmega8 microcontroller. The proposed control law represents a combination of discrete-time sliding mode and generalized minimum variance control techniques. The control design is based on input-output converter model and only the sensed output voltage is used for generating control signal. This approach simplifies the practical realization of boost converter since there is no need for current sensors. By introducing an additional discrete-time integrator in control, the converter accuracy in steady-state under load and input voltage variations is enhanced. The experimental prototype is developed and several experiments are conducted to validate the functionalities of the proposed solution. The maximum load and line regulation errors of the proposed converter are 1.55% and 2.9%, respectively. [ABSTRACT FROM AUTHOR]

This paper proposes a high-voltage high-efficiency peak-current-mode asynchronous DC-DC step-down converter operating with dual operation modes. The asynchronous buck converter achieves higher efficiency in light load condition compared to synchronous buck converters. Furthermore, the proposed buck converter switches operation mode automatically from pulse-width modulation (PWM) mode to pulse-skipping mode (PSM). By reducing power MOS on-state resistance and optimizing rise/fall time of switches, the proposed buck converter also obtains high efficiency under heavy load condition. The maximum efficiency of the proposed buck converter is 92.9%, implemented with 0.35m BCDMOS 2P3M process, and the total size is 1.1 1.2mm2. The input range and output range of the converter are 6-30 V, and (-3) V, respectively, with the maximum output current of 3 A. Moreover, its built-in current loop leads to good transient response characteristics. Therefore, it can be used widely in communication system and 12 V/24 V distributed power system. [ABSTRACT FROM AUTHOR]

In this paper, a traditional five-level cascaded H-bridge inverter is studied and regulated by a proportional-resonant (PR) controller. In order to extend the range of the gain of PR controller, for the purpose of achieving a fast response, a time-delayed feedback controller (TDFC) is used. Similar to the pulse width modulation (PWM) current-mode single phase H-bridge inverter that exhibits bifurcation and chaos when parameters vary, we demonstrate for the first time that the cascaded H-bridge inverter also shows similar features. From the perspective of a discontinuous map, the cascaded H-bridge inverter generally displays extraordinary complexity. Moreover, a new virtual ergodic method (VEM) is proposed to establish the mathematical model of the whole system, which helps to understand the observed bifurcation phenomena. Simulation results are given to verify the analysis. [ABSTRACT FROM AUTHOR]

In this paper, the principles, the design, the methodology of low cost implementation and the results of implementation of a shunt active power filter (SAPF) in the embedded system environment are presented. The system for which the SAPF is considered has a combination of linear reactive load and a three-phase-fed diode bridge rectifier that drives an RL load. The generation of the compensating signal or the reference signal is based upon the direct calculations implemented using the linear operational amplifiers. Further, the generation of the pulse width modulation (PWM) pulses is much similar to the conventional sinusoidal PWM but implemented in the embedded system platform. In this work, the built-in PWM and ADC sections of the microcontroller PIC 16F877A have been utilized for generating the PWM pulses without the requirement of an explicit carrier signal. The proposed method has been validated in MATLAB SIMULINK environment and also by an experimental prototype. [ABSTRACT FROM AUTHOR]

Reduction in the overall power devices such as power semi-conductor switches, gate drivers with the associated circuits and DC voltage sources reduces the size, cost, complexity in addition with enhancing the overall performance of the inverter. This paper presents a new and generalized multilevel inverter topology with reduced number of power components. To identify the significance of proposed inverter, the generalized formulae for all the parameters are calculated and a comprehensive comparison of different performance parameters are presented in tabular as well as in graphical form. Multicarrier pulse width modulation strategy is adopted for generating the switching pulses. Simulation of the proposed MLI topology for the 9-level and 17-level inverter have been performed in MATLAB/Simulink and the corresponding experimental results are incorporated for one unit and two units, respectively, experiments are carried out at RL load. Nevertheless, level per switch Ratio (L/S) is introduced and compared with some of the new discussed MLI topologies. Moreover, the switching and the conduction losses of the inverter are also calculated and incorporated in this paper. [ABSTRACT FROM AUTHOR]

In this paper, a novel seven-level Quasi-Z-Source-based T -type inverter (7L qZST 2 I) is proposed. The proposed inverter is an upgrade of Quasi-Z-source (qZs) network and seven-level T -type inverter. The 7L qZST 2 I comprises of three qZs-based impedance networks, two bidirectional switches and an H -bridge inverter. It owns the advantages of reduced switch count, improved output voltage gain, enhanced reliability and better quality of output voltage and current. The performance of the proposed topology is tested for two different pulse width modulation techniques based on shoot-through control. The first technique offers simple control and operated at a fixed shoot-through duty cycle for realizing output voltage level. The second technique facilitates independent control of each qZs network dc-link voltage and they can be operated at different shoot through duty cycle which overcomes the limitation of first technique with better quality in output voltage. The detailed operation of the proposed topology and control schemes have been elaborated for different switching states for each output voltage level generation. Extensive simulation and experimentation are performed for both the switching schemes to verify their performance under steady state and dynamic conditions. Furthermore, a brief comparison is constructed to highlight the merits of the proposed inverter with conventional topologies. [ABSTRACT FROM AUTHOR]

The distributed generation involving multiple photovoltaic sources and synthesizing high-quality ac voltage from those multiple dc sources are nascent research ambits. A host of multilevel inverters (MLIs) has been ascertained for performing above errand diligently, where the component count is obnoxious. The single phase seven-level inverter is an acquiescent compromise between the circuit complexity and the quality of the output. Further enhancement on the performance can be succored through optimizing dc link voltages and switching angles. This paper proposes a component count pruned MLI structure and also a refined genetic algorithm (RGA)-based optimization scheme for the computation of both dc link voltages and switching angles. Previous attempts for this problem have solved the switching angles with the objective of resulting minimum harmonic content in the staircase-shaped output voltage. The dc link voltage of each level is however assumed to be the same and constant. As an extension, RGA-based optimization of both dc link voltages and switching angles is triumphed. The harmonic profile of the proposed switching strategy is simulated and also corroborated by a hardware prototype. In practice, the proposed fundamental switched strategy is apposite, in which each dc voltage can be self-maintained and independently controlled. In addition, a method for designing the passive LC filter is also presented. [ABSTRACT FROM AUTHOR]

In hybridization of energy sources with distinct voltage–current characteristics, power electronic converter plays crucial role for efficient and reliable energy diversification. In this paper nonisolated dual input converter is proposed for integration and diversification of energy from two different sources with distinct voltage–current characteristics. The proposed dual input converter (DIC) is proficient for energy diversification from two sources individually and concurrently with series and parallel combination of connected sources. The proposed topology can be operated in buck, buck-boost and boost modes of operation. It offers compact design, higher degree of reliability in operation, simplicity in control and flexibility in selection of input source voltage magnitude. Comprehensive analysis of the proposed converter and detailed comparison with existing literature has also been presented. The proposed concept has been simulated in MATLAB SIMULINK and validated experimentally using dSPACE 1103 real time digital signal controller. [ABSTRACT FROM AUTHOR]

This paper investigates the various switching sequences on a generalized 60 ∘ distributed coordinate system-based space vector pulse width modulation (SVPWM) algorithm for multilevel inverters. The main focus of this work is to improve the inverter output voltage profile by taking advantage of the redundancy inverter switching states. With the help of SVPWM algorithm, the three nearest vectors have to find out the synthesis of the V ref location and then by applying the various optimum switching sequences, the inverter produces less harmonic content in the output voltage compared to the conventional switching sequence. All the switching sequence designs are developed with the help of minimum change detector (MCD) by using switching redundancies in order to reduce inverter switching loss. Simulation results to analyze various sequences on the general SVPWM algorithm are presented in the seven-level cascaded H-bridge (CHB) inverter. To validate the results, hardware results are presented on the seven-level CHB inverter. [ABSTRACT FROM AUTHOR]

This paper presents an investigation on mitigation of current harmonics, using Cascaded H-bridge Multilevel Converter (CHB-MLC)-based Shunt Active Power Filter (SAPF). Development and analysis of SAPF for harmonic compensation in distribution network for power quality improvement has been discussed. In the proposed work, transformer-less CHB MLC is used which reduces weight and cost of the system. Moreover, a novel controller based on average power method is adopted for generation of compensation active filter current. In order to generate switching signals, multi-carrier Alternate Phase Opposition Disposition (APOD) — Pulse Width Modulation (PWM) schemes are used. The proposed CHB-MLC SAPF reduces the source current THD below 5%. The results are simulated in MATLAB/Simulink and demonstrate the effective mitigation of current harmonics with APOD-PWM schemes. Opal-RT OP4500 real-time digital simulator is used to validate the proposed scheme under different steady state and transient conditions. [ABSTRACT FROM AUTHOR]

This paper presents a systematic process for designing a damping controller for pulse width modulated series compensator (PWMSC) to improve the angular stability of a multi-machine power system. The proposed controller is robust and tuned by satisfying the multiple H∞ performance criteria to stabilize the system at multiple operating conditions. The design problem has been converted into a constrained nonlinear optimization problem with the time domain-based objective function which is solved by an augmented Lagrangian particle swarm optimization (ALPSO) algorithm. The proposed control scheme has been implemented on two nonlinear test systems. The nonlinear simulation results clearly verify that the designed controller with proposed model improves the dynamic stability of the case studies, particularly when the operating loadings changes. [ABSTRACT FROM AUTHOR]

This paper reviews pulse-excitation as a technique for inducing chaos and provides a review of circuits that have been designed based on this technique. A clock-driven chaotic van der Pol oscillator is also presented. Vulnerability of this class of chaos generators to power supply attacks is demonstrated. [ABSTRACT FROM AUTHOR]

In this paper, a compact high-precision digital pulse-width modulation (DPWM) CMOS circuit is proposed. The circuit, with multiple output capability, allows brightness control of red, green, and blue (RGB) light emitting diode (LED) lighting. The PWM technique is used for LED dimming control to avoid the problem of color shifting. In this design, complementary concepts and hardware sharing are utilized to achieve a compact architecture and small chip area. A double-edge triggered technique is adopted to enhance the capability of high-speed operation. An experimental chip has been realized by using TSMC 0.18-μm CMOS technology. Simulation results show that the proposed 5-bit PWM circuit can operate at 200 MHz, 32 duty cycles adjustable, and within only 1-ns time error. The chip's measured results show that the new PWM circuit with three output channels works successfully at a supply voltage of 1.8-V, clock of 50-MHz, and resolution of 32 adjustable per channel. The core area of the chip is only 280 × 52.5 μm2. [ABSTRACT FROM AUTHOR]

In this paper, a CMOS digital pixel sensor (DPS) with pixel-level ADC based on pulse width modulation (PWM) scheme is proposed to overcome the restriction of low supply voltage imposed by device scaling trend. The pixel operates with a dynamic current comparison scheme to avoid using complex in-pixel comparator and achieve a high dynamic range (DR). By adjusting clock frequency for different illumination, DR is further extended due to increasing the maximum detectable photocurrent and lowering the minimum detectable photocurrent. The pixel contains a photodiode (PD), an 11-bit in-pixel SRAM and other 11 transistors, and occupies an area of 7 μm × 7 μm, with a fill factor of 31.3% using a standard 65 nm CMOS technology. Simulation results show that this pixel can work at a supply voltage as low as 0.5 V with 120 dB DR and 80 dB linear DR (LDR). The properties of high DR and logarithmic response make the proposed digital pixel be capable of human eye. Frame rate achieves 246 fps with 640 × 480 pixel array by using in-pixel ADC and SRAM. This makes the digital pixel very suitable for high-speed snap shot digital camera application. [ABSTRACT FROM AUTHOR]

Most existing stand-alone photovoltaic (PV) power systems employ pulse-width-modulated (PWM) DC-DC converters for maximum power point tracking (MPPT) and battery charging control. However, PWM converters experience high switching loss and high electromagnetic interference when operating at high frequency. Therefore, this paper presents an incremental conductance (INC)-based MPPT with constant voltage (CV) charging using LLC resonant converter for stand-alone solar streetlight system. INC MPPT maximizes the PV power generation while CV charging ensures good battery charging characteristics. Both the INC MPPT and CV charging are implemented in an algorithm using an Arduino Uno board. Detailed design procedure as well as extensive design considerations for a 100W prototype LLC resonant converter are presented. Experimental results show good MPPT performance under various environmental conditions such as sudden rise or sudden drop of incident irradiance. Furthermore, the system shows exceptional robustness in toggling between INC MPPT mode and CV charging mode depending on the environmental conditions. The converter displays excellent switching operation by achieving primary-side zero voltage switching and secondary-side zero current switching for the entire design range. [ABSTRACT FROM AUTHOR]

This paper presents a modified pulse width modulation (PWM) readout method for DPS with block-based self-adjusted reference voltage to extend dynamic range (DR). In this scheme, pixel arrays are divided into blocks with the same size, and the exposure process consists of two periods. During the first exposure, block-based reference voltage is generated based on the average photocurrent within the block. In the second exposure, the generated voltage is used as the reference voltage for PWM readout. Then the quantization results are combined together to represent the luminance information. DR and peak signal-to-noise ratio (PSNR) were discussed with different images and integration time. Simulation results show that this scheme can achieve a DR of over 96dB with 8-bit memory and 8-bit ADC and 145dB with 12-bit memory and 12-bit ADC. It also has 28.98dB PSNR on average, better than 20.11dB in fixed reference voltage method and 17.25dB in ramp reference voltage method. Combining the feature of active pixel sensor (APS) and PWM readout, this scheme allows better DR but also obtains less distortion of the image reconstruction. [ABSTRACT FROM AUTHOR]

This paper considers the processes of torus formation and reconstruction through smooth and nonsmooth bifurcations in a pulse-width modulated DC/DC converter with multilevel control. When operating in a regime of high corrector gain, converters of this type can generate structures of stable tori embedded one into the other and with their basins of attraction delineated by intervening repelling tori. The paper illustrates the coexistence of three stable tori with different resonance behaviors and shows how reconstruction of these tori takes place across the borders of different dynamical regimes. The paper also demonstrates how pairs of attracting and repelling tori emerge through border-collision torus-birth and border-collision torus-fold bifurcations. [ABSTRACT FROM AUTHOR]

This paper studies stabilization of low-period unstable periodic orbits (UPOs) in a simplified model of a current mode H-bridge inverter. The switching of the inverter is controlled by pulse-width modulation signal depending on the sampled inductor current. The inverter can exhibit rich nonlinear phenomena including period doubling bifurcation and chaos. Our control method is realized by instantaneous opening of inductor at a zero-crossing moment of an objective UPO and can stabilize the UPO instantaneously as far as the UPO crosses zero in principle. Typical system operations can be confirmed by numerical experiments. [ABSTRACT FROM AUTHOR]

The averaged switch modeling approach is a powerful method for representing the behavior of a wide variety of converters through equivalent circuits. The model is not linear and it is common to perform a small signal linearization about an operating point and design a linear controller. Models obtained with such method involve considerable approximation and produce results that are limited for high performance controller designs. In this paper a piecewise affine approximation technique is introduced for modeling PWM converters. This model is much more precise in predicting the dynamic response of averaged nonlinear model comparing the linear model. This paper also presents a piecewise linear controller synthesis method for PWM converters described by the proposed PWA model. The proposed controller is very efficient and effective. The design method is well suited for converters having a wide range of variation about their operating point. A simulation example on buck-boost converter is presented to demonstrate the performance of the proposed method for modeling the dynamics of the converter and designing the appropriate controller. [ABSTRACT FROM AUTHOR]

The paper presents the analysis, simulation, and experimental methods to eliminate acoustic resonance in high-frequency high-pressure sodium (HPS) lamps and integrate intelligent control strategies in the working device. Based on the pulse-width modulation (PWM) output generated by the microcontroller, the acoustic resonance in the high-frequency lamp can be successfully eliminated by modulating the high-frequency driving current via a low-frequency signal. Particularly, by implementing the pattern recognition, the control system enables the lamp to have the abilities of accurate timing, gradient dimming, automatic protection, and intellisense. The proposed model will provide useful information for designing intelligent lighting system towards smart cities. [ABSTRACT FROM AUTHOR]

The paper is devoted to the problem of uncertainty in the behavior of a pulse energy conversion system (PECS) near the bifurcation boundary. As a result of the investigations, the magnitude of the zone within which a heightened sensitivity of system dynamics varying to external and internal disturbances is revealed. Also the phenomenon of intermittency is confirmed. The validity of the results is based on an analysis of the synchronized data presented by oscillograms, bifurcation diagrams and time series, acquired on the experimental setup of DC motor drive (2 kW) with pulse-width modulation. [ABSTRACT FROM AUTHOR]

This paper introduces the complete bifurcation analysis in a PWM current-controlled H-Bridge inverter in a wide parameter space. First, we briefly explain the behavior of the waveform in the circuit in terms of the switched dynamical system. Then, the consecutive waveform during the duration of the clock interval is exactly discretized, and the return map is defined for the rigorous analysis. Using the map, we derive the one- and two-dimensional bifurcation diagrams, and discuss the specific property of each bifurcation phenomena in the circuit. [ABSTRACT FROM AUTHOR]

The objective is to produce a high-gain DC to DC flyback boost converter integrated with a multi-level converter for inverter applications. It has two stages: the first one is flyback multilevel converter, and another level comprises level controller and H-Bridge Inverter. The addition of voltage multiplier cells enhances the commercial flyback converter with multiple voltage outputs producing high voltage gain. These multiple outputs are fed to an H-bridge inverter for producing a multilevel output in an inverter. This DC-to-DC converter steps up the DC supply, but it also decreases the switches, diodes, and capacitors. This kind of converter not only reduces the switch count but also reduces the voltage stress, and total harmonic distortion. To increase the number of levels in the converter, the number of capacitors and diodes in the DC-to-DC converter without disturbing the main circuit must be increased to achieve the required output voltage. The number of power switches for the proposed topology is compared to comparable topologies in the current literature. The results of the simulation are communicated via the MATLAB/ Simulink domain, and the recommended converter's functionality is demonstrated. [ABSTRACT FROM AUTHOR]

Primary-side controlled pulse-width modulation (PWM) flyback converter has been widely used in low-power and low-voltage products for its simple structure and low cost. This paper presents a novel output voltage sampling circuit which considers the influence of the rectifier diode current on the output voltage sampling. The output voltage sampling circuit samples the output voltage at 85% of the secondary inductance discharge time of last cycle, which improves the accuracy of the output voltage sampling circuit. Besides, the circuit can also sample the secondary inductance discharge time . Finally, a chip has been fabricated in 0.6m complementary metal-oxide semiconductor (CMOS) process, which is used in the presented output voltage sampling circuit in its internal circuit to simple output voltage and achieve constant output voltage. [ABSTRACT FROM AUTHOR]

This paper presents a photovoltaic (PV) system to convert the solar energy into electrical energy. DC power from PV system is converted into AC power using multilevel inverters. Cascaded H-bridge (CHB) inverter and diode clamped inverter (DCI) are used to convert variable DC power into sinusoidal AC power. Harmonic content is the important part to improve the efficiency of the inverter. Harmonics of CHB inverter and DCI are simulated and analyzed with different pulse width modulation (PWM) techniques. [ABSTRACT FROM AUTHOR]

This paper proposed an adaptive neuro-fuzzy model (ANFIS) to multilevel inverter (MLI) for grid connected photovoltaic (PV) system. The purpose of the proposed controller is that it is not requiring any optimal pulse width modulated (PWM) switching-angle generator and proportional-integral controller. The proposed method strictly prohibits the variations present in the output voltage of the cascaded H-bridge MLI. In this method, the ANFIS have the input which is grid voltage, the difference voltage and the output target is control voltage. By using these parameters, the ANFIS makes the rules and has been tuned perfectly. During the testing time, the ANFIS gives the control voltage according to the different inputs. The resultant control voltage equivalent gate pulses are utilized for controlling the insulated gate bi-polar switches (IGBT) of MLI. Then the ANFIS based MLI for grid connected PV system is implemented in the MATLAB/simulink platform and the effectiveness of the proposed control technique is analyzed by comparing with the neural network (NN), fuzzy logic control, etc. The comparison results demonstrate the superiority of the proposed approach and confirm its potential to solve the problem. A prototype of three-phase grid connected cascaded H-bridge inverter has been developed using field-programmable gate array (FPGA) and results are analyzed. [ABSTRACT FROM AUTHOR]

Memristor resembles an artificial synapse and is considered to be basic electronic element for realizing neuromorphic circuits. In this work, a systematic investigation was conducted on memristor-based resistance-programming circuits to write analog data into a memristor utilizing pulse width modulation techniques. The high-frequency sinusoidal signal was utilized to read the data in the form of its electronic resistance. An optimum circuit configuration demonstrated multilevel stable resistive states, which are analogous to the connection weights in the human synapse. In order to modulate these memristive weights for representing the learning activities in human brain synapse, it was identified that the pulse width modulation technique is superior as compared to spike-timing-dependent plasticity. Further, the above analysis was utilized in training the memristor to update its resistive weights in consonance with its learning, analogous to that in a neural network. Further, the memristive crossbar architecture was utilized to implement a real-time application in Econometrics, where an array of memristors were utilized to learn and update the purchase trends of an N × L matrix of customers. The proposed circuits possess the advantages of high packing density, low power consumption and nonvolatility, and also pave the way for developing future neuromorphic circuits. [ABSTRACT FROM AUTHOR]

A study of a DC-DC boost converter fed by a photovoltaic (PV) generator and supplying a constant voltage load is presented. The input port of the converter is controlled using fixed frequency pulse width modulation (PWM) based on the loss-free resistor (LFR) concept whose parameter is selected with the aim to force the PV generator to work at its maximum power point. Under this control strategy, it is shown that the system can exhibit complex nonlinear behaviors for certain ranges of parameter values. First, using the nonlinear models of the converter and the PV source, the dynamics of the system are explored in terms of some of its parameters such as the proportional gain of the controller and the output DC bus voltage. To present a comprehensive approach to the overall system behavior under parameter changes, a series of bifurcation diagrams are computed from the circuit-level switched model and from a simplified model both implemented in PSIM© software showing a remarkable agreement. These diagrams show that the first instability that takes place in the system period-1 orbit when a primary parameter is varied is a smooth period-doubling bifurcation and that the nonlinearity of the PV generator is irrelevant for predicting this phenomenon. Different bifurcation scenarios can take place for the resulting period-2 subharmonic regime depending on a secondary bifurcation parameter. The boundary between the desired period-1 orbit and subharmonic oscillation resulting from period-doubling in the parameter space is obtained by calculating the eigenvalues of the monodromy matrix of the simplified model. The results from this model have been validated with time-domain numerical simulation using the circuit-level switched model and also experimentally from a laboratory prototype. This study can help in selecting the parameter values of the circuit in order to delimit the region of period-1 operation of the converter which is of practical interest in PV systems. [ABSTRACT FROM AUTHOR]

A new structure of Boost Cascaded DC Link H-Bridge Inverter (BCDCLHBI) is proposed for domestic UPS applications. It consists of DC-DC converter, sub-multilevel modules and H-bridge inverter circuits. The proposed sub-multilevel modules synthesize a stepped DC link voltage with reduced voltage stress across the H-bridge inverter. Compared with conventional two-level inverter the proposed stepped DC link inverter configuration has reduced Power Spectral Density (PSD) and reduced voltage stress. Compared with conventional Cascaded Multilevel Inverter (CMLI) configuration, the proposed system has reduced power switches, DC sources and gate driver requirements. To obtain better quality of AC power output, carrier-level shifted Pulse Width Modulation (PWM) schemes are developed for sub-multilevel switching. A simulation and prototype model of 7-level BCDCLHBI is developed and its performance is validated. [ABSTRACT FROM AUTHOR]

A very simple, wide range and programmable pulse width controller or duty cycle corrector (DCC) is presented. Simulating the circuit in 0.35 μm Complementary MOSFET (CMOS) technology shows that the frequency range of the input signal can be within 250 MHz to 1.6 GHz, with a duty cycle of 30-70%. The proposed circuit generates an output signal with programmable duty cycle in the range of 30-70% with steps of 10% which could be extended to more steps by simple variations. The systematic peak-to-peak jitter at center frequency (1 GHz) is 1ps, while adding a random noise source of 5% of the power supply, increases it to 13 ps. the power consumption at maximum speed (1.6 GHz) is 4.9 mW. Monte Carlo simulations show maximum of 3.4% error at the 1.5 GHz input frequency and 70% output duty cycle. [ABSTRACT FROM AUTHOR]

A closed-loop scheme of 2-stage multiphase switched-capacitor (MPSC) converter is proposed by combining variable-phase control (VPC) and pulse-width-modulation (PWM) technique for low-power DC-DC step-up conversion and high-efficiency output regulation. In this MPSC, there are 2 voltage doublers in series for boosting voltage gain up to 4 at most. Here, VPC is suggested to improve power efficiency, especially for the lower output voltage. It realizes a variable multiphase operation by changing MPSC topological path for more suitable level of voltage gain (4x/3x/2x/1x) according to the desired output. Besides, PWM is adopted for better output regulation not only to compensate dynamic error, but also to reinforce robustness against source/loading variation. Further, the theoretical analysis and design include: MPSC model, steady-state analysis, power efficiency, conversion ratio, ripple percentage, capacitance selection, stability, and control design. Finally, the closed-loop MPSC is simulated, and the hardware implementation is realized and tested. All the results are illustrated to show the efficacy of the proposed scheme. [ABSTRACT FROM AUTHOR]