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With the massive expansion of decentralised renewable energy in electricity grid networks, the power supply system has been changed from centralised to decentralised one and from directional to bi-directional one. However, due to the regional energy structure difference in the power imbalance between electricity generation and consumption is becoming more and more serious. A grid-scale energy storage system (ESS) can be one solution to balance the local difference. In this paper, two charging/discharging strategies for the grid-scale ESS were proposed to decide when and with how much power to charge/discharge the ESS. In order to realise the two strategies, this paper focuses on the application of fuzzy logic control system. The proposed strategies aim to reduce the peak power generation, consumption and the grid fluctuation. In particular, this paper analysis the ratio between energy-capacity and rated power of ESS. The performance of the proposed strategies is evaluated from two aspects, the normalised power of ESS itself and the influence on the power grid. Simulation studies were carried out on the rule-based control systems with different energy-to-power (e2p) ratios, and the results show that the proposed charging strategy with combination of extreme situation of power imbalance and the rest capacity of ESS provides a smooth load curve for the regional power grid system while the external power exchange is reduced effectively. [ABSTRACT FROM AUTHOR]

A capacitance multiplier is an active circuit designed specifically to increase the capacitance of a passive capacitor to a significantly higher capacitance level. In this paper, the use of a voltage differencing differential difference amplifier (VDDDA), an electronically controllable active device for designing grounded and floating capacitance multipliers, is proposed. The capacitance multipliers proposed in this study are extremely simple and consist of a VDDDA, a resistor, and a capacitor. The multiplication factor ( K c ) can be electronically controlled by adjusting the external bias current ( I B ). It offers an easy way of controlling it by utilizing a microcontroller for modern analog signal processing systems. The multiplication factor has the potential to be adjusted to a value that is either less than or greater than one, hence widening the variety of uses. The grounded capacitance multiplier can be easily transformed into a floating one by utilizing Zc-VDDDA. PSpice simulation and experimentation with a VDDDA realized from commercially available integrated circuits were used to test the performance of the proposed capacitance multipliers. The multiplication factor is electronically adjustable, ranging in approximation from 0.56 to 13.94. The operating frequency range is approximately three frequency decades. The realization of the lagging and leading phase shifters using the proposed capacitance multiplier is also examined and proven. The results reveal that the lagging and leading phase shifts are electronically tuned via the multiplication factor of the proposed capacitance multipliers. [ABSTRACT FROM AUTHOR]

The modular multilevel converter (MMC) has many advantages of low switching losses, good harmonic performance and high modularity structure in state-of-the-art HVDC applications. The full-bridge submodules (FBSMs) of the hybrid MMC can inherently output negative voltage to absorb fault currents, and consequently the hybrid MMC can ride through severe DC faults without blocking. During the DC fault-ride-through process, the submodule capacitor voltage and arm current of the MMC will be temporarily increased. These characteristics limit the proportion of the FBSMs, which should not be too low and thus increase the cost and operating losses of the hybrid MMC. In this paper, an improved sorting algorithm of SM capacitor voltage is established, and a novel virtual damping control strategy is proposed that can effectively suppress the increase in submodule capacitor voltage and arm current of the hybrid MMC during the DC fault-ride-through process. By adopting this optimization control, the proportion of FBSMs can be reduced significantly without deteriorating the fault-ride-through capability or safety of the MMC. The effectiveness of the proposed control is verified by careful theoretical analysis and detailed simulation results. [ABSTRACT FROM AUTHOR]

Materials offering high energy density are currently desired to meet the increasing demand for energy storage applications, such as pulsed power devices, electric vehicles, high-frequency inverters, and so on. Particularly, ceramic-based dielectric materials have received significant attention for energy storage capacitor applications due to their outstanding properties of high power density, fast charge–discharge capabilities, and excellent temperature stability relative to batteries, electrochemical capacitors, and dielectric polymers. In this paper, we present fundamental concepts for energy storage in dielectrics, key parameters, and influence factors to enhance the energy storage performance, and we also summarize the recent progress of dielectrics, such as bulk ceramics (linear dielectrics, ferroelectrics, relaxor ferroelectrics, and anti-ferroelectrics), ceramic films, and multilayer ceramic capacitors. In addition, various strategies, such as chemical modification, grain refinement/microstructure, defect engineering, phase, local structure, domain evolution, layer thickness, stability, and electrical homogeneity, are focused on the structure–property relationship on the multiscale, which has been thoroughly addressed. Moreover, this review addresses the challenges and opportunities for future dielectric materials in energy storage capacitor applications. Overall, this review provides readers with a deeper understanding of the chemical composition, physical properties, and energy storage performance in this field of energy storage ceramic materials. [ABSTRACT FROM AUTHOR]

Reactive power compensation (RPC) is a big problem during power system operation. Parenthetically, capacitor allocation and sizing may be the only convenient solution for RPC of power systems. The loss sensitivity factor (LSF) is applied here for finding the optimum capacitor position. This paper presents quasi-oppositional fast convergence evolutionary programming (QOFCEP), fast convergence evolutionary programming (FCEP), and evolutionary programming (EP) for the optimum location and sizing of shunt capacitors in the isolated microgrid (MG) for minimizing total real power loss throughout the day with and without the demand response program (DRP). The 33-node, 69-node, and 118- node isolated MGs have been studied to authenticate the efficacy of the suggested approach. Each MG includes small hydro power plants (SHPPs), solar PV plants (SPVPs), wind turbine generators (WTGs), diesel generators (DGs), and plug-in electric vehicles (PEVs). [ABSTRACT FROM AUTHOR]

A 16-bit 125 MS/s pipelined analog-to-digital converter (ADC) implemented in a 0.18 μ m CMOS process is presented in this paper. A sample-and-hold amplifier-less (SHA-less) modified 2.5-bit front-end is adopted, which splits the sampling capacitor in half to eliminate the common-mode voltage buffer. The multiplying-digital-to-analog converter (MDAC) in the first pipeline stage is modified by reusing the sampling capacitor in a foreground digital calibration for improving the ADC linearity. This design can circumvent a dedicated reference buffer to generate the calibration voltages at all comparator thresholds. By calibrating the ADC in the digital domain, the integral non-linearity (INL) is improved from −9.2/10 LSB to −3/2.2 LSB, and the spurious-free dynamic range (SFDR) is optimized by over 8dB. The ADC consumes 154mW (reference buffer and clock included) from a 1.8 V supply. [ABSTRACT FROM AUTHOR]

As electrochemical research undergoes rapid technological progression, the acquisition of substantial amounts of electrochemical impedance spectra (EIS) becomes increasingly feasible. Yet, this advancement introduces intricate challenges in data processing, automation, and interpretation. This paper delves into the sufficiency of unsupervised machine learning (ML) and in particular dimensionality reduction methods in decoding EIS complexities, examining its strengths, limitations, and potential pathways for optimization. As we navigated the intricacies of non‐linear dimensionality reduction, spotlighting t‐distributed stochastic neighbor embedding (t‐SNE) and uniform manifold approximation and projection (UMAP) algorithms, a pattern emerged: these techniques excel at categorizing divergent impedance spectra but show limitations when faced with analogous circuit configurations, especially those substituting a capacitor with a constant phase element. This observation not only underscores a limitation but also accentuates that unsupervised ML approaches, alone, may not fully unravel the nuances of EIS spectra. In the concluding section of our manuscript, we discuss the implications of this finding from a practical standpoint, particularly for electrochemists seeking to apply these methods in their work. [ABSTRACT FROM AUTHOR]

The paper deals with the capacitance of cylindrical two-dimensional capacitor which consists of Cartesian orthotropic dielectric material. The determination of the capacitance of capacitor with orthotropic dielectric material by a suitable coordinate transformation is reduced to the computation of capacitance of an isotropic capacitor. It is proven that the capacitance of a Cartesian orthotropic capacitor can be obtained in terms of an isotropic capacitor whose dielectric constant is the geometric mean of the dielectric constant of the orthotropic capacitor. [ABSTRACT FROM AUTHOR]

The modular multilevel converter (MMC) is a research hotspot in medium-voltage and high-voltage applications. The measurement offset error would cause an increase in the monitoring error of the submodule (SM) capacitance of the MMC, affecting the estimation accuracy of the SM capacitance monitoring. This paper proposes a capacitor monitoring strategy based on the offset error compensation, where two reasonable capacitor monitoring periods are selected in one fundamental period under the proposed voltage-balancing control (VBC) based on the virtual capacitor voltage (VCV) to compensate for the offset error impact on the capacitance monitoring. The proposed strategy can effectively eliminate the offset error impact on the capacitance monitoring, which ensures the accuracy of the SM capacitance monitoring in the MMCs. The effectiveness of the proposed monitoring strategy is confirmed by the simulations and experiments. [ABSTRACT FROM AUTHOR]

Due to the unique properties of room temperature ionic liquids (RTILs), most researchers' interest in RTIL-based electrolytes in electric double-layer capacitors (EDLCs) stems from molecular simulations, which are different from experimental scientific research fields. The knowledge of RTIL-based electrolytes in EDLCs began with a supposition obtained from the results of molecular simulations of molten salts. Furthermore, experiments and simulations were promoted and developed rapidly on this topic. In some instances, the achievements of molecular simulations are ahead of even those obtained from experiments in quantity and quality. Molecular simulations offer more information on the impacts of overscreening, quasicrowding, crowding, and underscreening for RTIL-based electrolytes than experimental studies, which can be helpful in understanding the mechanisms of EDLCs. With the advancement of experimental technology, these effects have been verified by experiments. The simulation prediction of the capacitance curve was in good agreement with the experiment for pure RTILs. For complex systems, such as RTIL–solvent mixtures and RTIL mixture systems, both molecular simulations and experiments have reported that the change in capacitance curves is not monotonous with RTIL concentrations. In addition, there are some phenomena that are difficult to explain in experiments and can be well explained through molecular simulations. Finally, experiments and molecular simulations have maintained synchronous developments in recent years, and this paper discusses their relationship and reflects on their application. [ABSTRACT FROM AUTHOR]

In this paper, a new negative lossless grounded capacitance multiplier (GCM) circuit based on a Current Feedback Operational Amplifier (CFOA) is presented. The proposed circuit includes a single CFOA, four resistors, and a grounded capacitor. In order to reduce the power consumption, the internal structure of the CFOA is realized with dynamic threshold-voltage MOSFET (DTMOS) transistors. The effects of parasitic components on the operating frequency range of the proposed circuit are investigated. The simulation results were obtained with the SPICE program using 0.13 µm IBM CMOS technology parameters. The total power consumption of the circuit was 1.6 mW. The functionality of the circuit is provided by the capacitance cancellation circuit. PVT (Process, Voltage, Temperature) analyses were performed to verify the robustness of the proposed circuit. An experimental study is provided to verify the operability of the proposed negative lossless GCM using commercially available integrated circuits (ICs). [ABSTRACT FROM AUTHOR]

In power engineering, the importance of maintaining a high power factor in low-voltage electrical installations is known. In power substations for industry, the usual method of coupling is to use an automatic power factor controller which connects capacitors banks (with electromagnetic contactors). Sometimes, AC reactors are connected to the phases of the capacitors banks (to reduce transient phenomena and the deforming regime), depending on the desired value of the power factor. This paper presents an analysis (more focused on experimentation) of a low-cost system for automatic regulation of the power factor with a reduction in transients and an increase in the life of contactors (eliminating the electric arc during switching on), with capacitors banks for low-voltage three-phase installations that connect the capacitors banks by means of one three-phase solid-state relay (an expensive device for a quality device; one is used for all capacitors banks) and using several electromagnetic contactors. The automatic power factor adjustment system has a controller with a microprocessor with six outputs, controlled by the phase shift between the current (measured with a current transformer proportional to the current in a bar) and the phase voltage, which is part of a system of distribution bars (L1,2,3, N) from which electrical consumers (e.g., induction motors) are supplied. To reduce transients when connecting capacitors banks, a three-phase solid-state relay and two related electromagnetic contactors are used for each capacitors bank. The automatic power factor controller is connected to two low-capacity PLCs that control the logic of connecting the capacitors banks to reduce transients. By using the proposed regulation system, a cheaper control solution is obtained compared to the use of one solid-state relay for each capacitors banks, under the conditions in which the power factor adjustment is made as in the classic solution. If twelve capacitors banks are used, the proposed installation is 22.57% cheaper than the classical power factor regulation installation. [ABSTRACT FROM AUTHOR]

Today, multilevel inverters are widely utilized in various applications. Reducing the number of components in the design of these converters is one of the crucial goals so that they have less volume and cost. This paper presents a single‐source structure for a multilevel switched‐capacitor inverter with voltage boost capability. The proposed structure can generate 25 sinusoidal‐like step voltage levels with a six times amplitude increase compared to the input. This converter uses only one direct current (DC) power source, 14 switches, and four capacitors. The nearest level control switching method has been used to control the converter, create voltage levels, and select the switching modes. A comprehensive comparison has been made with other recently presented structures to demonstrate the efficiency of the proposed structure. The advantages of the proposed structure include using only one DC voltage source, the ability to increase the output voltage six times compared to the input, the use of fewer power electronics components compared to the number of voltage levels, proper efficiency, self‐balancing of capacitors, and as a result, the lower cost. The performance accuracy of the proposed converter has been simulated in the MATLAB Simulink environment and then evaluated by a laboratory prototype. [ABSTRACT FROM AUTHOR]

Background: The current strategies for making electronic devices are generally time, water, material and energy consuming. Here, the direct writing of composite functional circuits through comprehensive use of GaIn10-based liquid metal inks and matching material is proposed and investigated, which is a rather easy going and cost effective electronics fabrication way compared with the conventional approaches. Methods: Owing to its excellent adhesion and electrical properties, the liquid metal ink was demonstrated as a generalist in directly making various basic electronic components such as planar resistor, inductor and capacitor or their combination and thus composing circuits with expected electrical functions. For a precise control of the geometric sizes of the writing, a mask with a designed pattern was employed and demonstrated. Mechanisms for justifying the chemical components of the inks and the magnitudes of the target electronic elements so as to compose various practical circuits were disclosed. Results: Fundamental tests on the electrical components including capacitor and inductor directly written on paper with working time up to 48 h and elevated temperature demonstrated their good stability and potential widespread adaptability especially when used in some high frequency circuits. As the first proof-of-concept experiment, a typical functional oscillating circuit including an integrated chip of 74HC04 with a supply voltage of 5 V, a capacitor of 10 nF and two resistors of 5 kΩ and 1 kΩ respectively was directly composed on paper through integrating specific electrical elements together, which presented an oscillation frequency of 8.8 kHz. Conclusions: The present method significantly extends the roles of the metal ink in recent works serving as only a single electrical conductor or interconnecting wires. It opens the way for directly writing out complex functional circuits or devices on different substrates. Such circuit composition strategy has generalized purpose and can be extended to more areas, even daily pervasive electronics. [ABSTRACT FROM AUTHOR]

In this paper, an inner ultrathin oxide metal–oxide–semiconductor (MOS) capacitor is fabricated with another outer MOS-gate ring as a coupling controller. Capacitance–voltage characteristics of inner MOS capacitor show that the excess minority carriers supplied from the outer MOS-gate ring can efficiently change the inner capacitance (${C} _{\text {inner}}$). It is observed that outer MOS-gate ring under the conditions at floating and at ground has quite different coupling effects on ${C} _{\text {inner}}$ when the inner MOS is biased at 1 V. Comparing to ${V} _{\text {outer}} = \text {floating}$ , ${C} _{\text {inner}}$ reduces significantly when ${V} _{\text {outer}} = {0}$ V at 1k Hz. The transient behavior of ${C} _{\text {inner}}$ as ${V} _{\text {outer}}$ changes from 0 V to floating is long enough to read, and the difference of two capacitance values can be regarded as two states. As a result, a two capacitance states operation is proposed for possible memory application. Based on the experimental results, the possible memory cell configuration is designed. Comparing to the present emerging memories, since the two states in this paper are in conditions of floating and 0 V, ultralow power is consumed, which is believed a promising concept for future memory application. [ABSTRACT FROM AUTHOR]

This paper proposes unconventional control techniques for a portable power supply consisting of electric double-layer capacitors (EDLCs), a dc–dc converter, and a low-impedance load such a plasma load. Between the EDLCs and the plasma load consuming high power, a dc–dc converter is required to control the output voltage from the rapidly decreasing voltage of EDLCs. In addition, the dc–dc converter should maintain a set point by responding to arcs occurred in plasma process. This paper proposed hybrid analog and digital controls for a nonideal boost converter which was setup by theoretical analysis. The proposed system is verified with experiment and simulation. As a result, the proposed control method can maintain the constant output voltage longer than a traditional analog pulsewidth modulation control. [ABSTRACT FROM AUTHOR]

A new modular pulsed-power source with fast rise time and step-wise arbitrary output waveform generation is currently under development to drive the Gepulste Elektronenstrahlanlage device investigated at the Institute for Pulsed Power and Microwave Technology (IHM). Acknowledging the complex design procedures necessary to set up a modular pulsed-power source for voltages of up to 120 kV, this paper focuses on the circuit design for a single stage and its validation prior to the generator assembly. Using a semiconductor-based Marx generator topology, the stages are designed to have an output voltage of 1 kV with a pulse current of up to 600 A. When connected to an ohmic load, the measured current rise times are in the order of 46 ns resulting in the current rise rates of up to 10 kA/ $\mu \text{s}$ using the commercial devices. The step-wise arbitrary output waveform is created by generating the switching commands on the stage using a microprocessor and a fast optical synchronization unit. Effective stage shielding is verified by operating the stage in a 100-kV, 2.5-kA electromagnetic interference test bed. This paper presents the design considerations and the corresponding measurements. [ABSTRACT FROM AUTHOR]

The paper presents the results of the analysis of the power quality in the point of common coupling of an internal network of an industrial enterprise, following the recording of the energy parameters in the critical load interval. The equivalent load in the point of common coupling (PCC) consists mainly of nonlinear single--phase loads, which makes the phase powers to be strongly unbalanced. The recordings made and their processing highlighted the poor power quality and the need to identify an appropriate solution to improve the power quality. It was proposed to use a four--wire shunt active power filter (SAPF) with split filtering capacitor. [ABSTRACT FROM AUTHOR]

In this paper, the problem of sizing and placement of constant and switching capacitors in electrical distribution systems is modelled considering the load uncertainty. This model is formulated as a multicriteria mathematical problem. The risk of voltage violation is calculated, and the stability index is modelled using fuzzy logic and fuzzy equations. The instability risk is introduced as the deviation of our fuzzy-based stability index with respect to the stability margin. The capacitor placement objectives in our paper include: (i) minimizing investment and installation costs as well as loss cost; (ii) reducing the risk of voltage violation; and (iii) reducing the instability risk. The proposed mathematical model is solved using a multi-objective version of a genetic algorithm. The model is implemented on a distribution network, and the results of the experiment are discussed. The impacts of constant and switching capacitors are assessed separately and concurrently. Moreover, the impact of uncertainty on the multi-objectives is determined based on a sensitivity analysis. It is demonstrated that the more the uncertainty is, the higher the system cost, the voltage risk and the instability risk are. [ABSTRACT FROM AUTHOR]

Virtual synchronous generator (VSG)-based control approaches for AC machine drivers have attracted much attention in recent years. The contradiction between the strong motor loading capacity and the small DC voltage fluctuation is disregarded in previous studies. A larger virtual inertia is required to raise the torque gain and drive the motor with heavier loads, thus resulting in greater DC voltage variations. A systematic method is proposed for the optimal design of the virtual inertia for VSG-based motor starting systems to achieve the maximal motor loading capacity and the low DC voltage fluctuation in this paper. Firstly, the relationship between the virtual inertia and the loading capacity is revealed on the basis of the closed-loop analysis. Considering the DC voltage variation, the constraint on the maximal value of the virtual inertia is proposed from the energy-balance perspective despite the unknown contribution of the DC capacitors to the virtual inertia. To fully exploit the energy storage capacity of the DC capacitors and raise the upper limit of the virtual inertia under the same permitted DC voltage variation, a modified DC voltage reference is introduced. Extensive simulation and experimental results are presented to validate the effectiveness of the proposed methods. [ABSTRACT FROM AUTHOR]

The fourteen papers in this special section focus on high performance light emitting diode (LED) drivers. In recent years, as the fourth generation of light source, light-emitting diodes (LEDs) have been widely used in many applications such as street lighting, automotive, and residential lighting because of their long lifetime, low maintenance requirement, and environment friendliness. As the performance of LEDs will be influenced obviously by the drivers, researchers have shown a growing interest in optimizing the drivers. Although these problems such as current balancing, eliminating electrolytic capacitor, and improving the topologies are not new, the high-frequency high-efficiency trend of LED drivers has given rise to additional challenges. These papers provide an insight on some of the newly emerging challenges and potential solutions to overcome those issues. [ABSTRACT FROM PUBLISHER]

This paper presents a mathematical analysis of how energy return in grid-connected single-phase photovoltaic systems affects the sizing of passive components. Energy return affects the size of the link capacitor, making it larger than reported in the literature. One of the main points of this article is that an inverter connected to the grid using a DC–DC converter with an appropriate link capacitor is analyzed. The energy return is caused by the value (in Henry units) of the L-filter, which is also analyzed in this paper. The analysis shows that there is a link between the value of the L-filter and the voltage of the DC bus. The analysis assumes two conditions: (1) the DC bus voltage is always higher than the peak value of the grid sinusoidal voltage, and (2) there is a unity power factor at the connection point between the grid and the L-filter. To operate in an open loop, a compensation phase angle is calculated and introduced in the single-phase inverter modulation; this phase angle compensates the phase shift caused by the L-filter, avoiding the use of a phase-locked-loop (PLL) control system. The L-filter ripple current is evaluated by Fourier analysis, and the DC bus ripple voltage is evaluated by considering the energy returned to the link capacitor. The results of the analyses are compared with existing methods reported in the literature. The results also show that, to minimize the value of the L-filter, the DC voltage must be almost equal to the maximum voltage of the grid. Equations to assess the value of the DC-link capacitor and the L-filter in function of their ripples are developed. The results were verified with simulations in Simulink and experimentally. [ABSTRACT FROM AUTHOR]

Power distribution systems (PDS) are the infrastructure and equipment used to distribute electricity from the transmission system to end-users, such as homes and businesses. PDS are usually designed to operate in a radial mode, where power flows from one substation to the end user through a series of feeders. The extension of distribution lines to attend new customers along with the growing demand for electricity result in increased energy losses and voltage reductions. Various solutions have been proposed to solve these issues, such as selecting the optimal set of conductors, optimizing the placement of voltage regulators, using capacitor banks, reconfiguring the distribution system, and implementing distributed generation. A well-known approach for reducing energy losses and enhancing voltage profile is the optimal conductor selection (OCS). While this can be beneficial, it may not be sufficient to fully reduce technical losses and improve the system voltage profile; therefore, it must be combined with other strategies. This paper presents a new approach that combines the OCS with the optimal placement of capacitor banks (OPCB) to minimize technical losses and improve the voltage profile in PDS. The main contribution of this paper is the integration of these two problems into a single mixed integer linear programming (MILP) model, therefore guaranteeing the achievement of globally optimal solutions. Three test systems of 27, 69, and 85 buses were used to illustrate the effectiveness of the proposed modeling approach. The results indicate that the combination of OCS and OPCB effectively minimizes energy losses and enhances the voltage profile. In all cases, the solutions obtained by the proposed MILP approach were better than those previously reported through metaheuristics for the combined OCS and OPCB problem. [ABSTRACT FROM AUTHOR]

The paper considers the problem of sub-synchronous resonances (SSR) in doubly fed induction generators connected to the grid through series-compensated lines. The existence of oscillations is observed on a laboratory test-bed in various conditions, with instabilities developing in the worst-case scenario. Despite the limitations of a small-scale test-bed, the ability to investigate problems and solutions in ways that would not be possible on a full-scale system is very valuable. In particular, the paper demonstrates the significant effect of the choice of dq reference frame on the severity of SSR. Stator-aligned algorithms are found to be significantly more resonant than grid-oriented algorithms, as evidenced in experiments as well as using an analysis method proposed in the paper. From this observation, an algorithm is proposed to emulate a grid-alignment using stator voltages and currents, but without measurements of the grid and series-capacitor voltages. Two control laws are then presented to regulate the active and reactive powers generated, resulting in well-damped transient responses. SSR oscillations are found to be eliminated in experime, as well as simulations of a full-scale system and using a frequency response analysis of the closed-loop system. The effectiveness of the proposed control schemes is verified through experiments for different compensation levels and varying speeds. Within the assumptions made in the design, the proposed controllers are global. [ABSTRACT FROM AUTHOR]

Provides instructions and guidelines to prospective authors who wish to submit manuscripts. [ABSTRACT FROM AUTHOR]

This paper proposes an adaptive self-tuned current controller design for an LCL-filtered LC-tuned single-phase shunt hybrid active power filter (HAPF), which offers adaptability and flexibility of the control system to filter parameters changes. System modelling and online identification of parameters are presented. Then, a systematic self-tuned controller (STC) design is proposed to calculate the controller parameters and obtain the final control law adaptively. The exact HAPF parameters design is described and the overall closed-loop stability evaluation with considering digital control delay is discussed in this paper. To confirm the theoretical achievements, simulations and experimental tests on a real prototype system are performed. The results are in good accordance and demonstrate the effectiveness and superior performance of the suggested control technique. Furthermore, a comprehensive comparison between the proposed control technique and other controllers is provided to show the superiority of the proposed system from different aspects. [ABSTRACT FROM AUTHOR]

In renewable energy micro-source applications, a wide range of voltage conversion of the step-up converter is an essential part to equalize the typical low voltage of micro-source with DC-bus voltage of Inverter or motor drives. In order to meet this purpose, an ultra-voltage gain step-up DC-DC converter is proposed in this paper. The proposed converter has made an arrangement of the regenerative-boost fed switched inductor and capacitor configurations. Thereby, due to such an organization of structure, the proposed converter can develop an extremely high voltage-gain even at lower duty ratios. In addition, it has the advantage of lower switching stress across all power semi-conductive diodes. Furthermore, this paper describes the steady-state analysis and comparative features of the converter with existing recent literature. Finally, to validate theoretical analysis and test the feasibility and suitability of the proposed ultra-gain converter, the experimental results were observed by a 500 W fabricated prototype. [ABSTRACT FROM AUTHOR]

Conventional half bridge modular multilevel converter (MMC) system will suffer great over-current when there is a dc side fault. Therefore, topology study in sub-modules with dc side fault blocking capability have become one of the hotspots in MMC field. However, fault blocking topologies using conventional IGBT devices must employ more semiconductors than half bridge topology. The extra semiconductor devices employed in the topology will lead to the increase of cost and conduction loss. To reduce the conduction loss of the fault blocking topology, a novel sub-module topology is proposed in this paper. The proposed topology employs reverse blocking devices to form the low conduction loss path. Conduction loss analysis is conducted in this paper to show the priority of the proposed topology. Simulation and experiment results verified the dc fault blocking capability of the proposed topology. [ABSTRACT FROM AUTHOR]

This paper analyzes the unsymmetrical operation of the dc/dc MMC caused by parametric uncertainty. The unsymmetrical operation is referred to as the condition in which parameters involved in ac power generation are not equal in the phase-legs of the converter. Because existing models in the literature cannot exhibit the unsymmetrical operation of the dc/dc MMC, new detailed and simplified steady-state models are developed in this paper. In the developed models, the connection between the operation of different phase-legs shows itself when the dc-link impedance is considered. Using the developed models, the parameters that can force the converter to operate in unsymmetrical conditions are identified, and the maximum variation that the converter can tolerate is found. It is shown that even a small parameter variation leads to the leakage of the ac circulating current into the dc-link, which is not acceptable. By conducting various case studies, the impacts of the dc-link length, the transmitted power, and the conversion ratio on the unsymmetrical operation of the dc/dc MMC are characterized. The results showed that the converter would be more sensitive to the parameter variation as these parameters increase. Comparative analysis and simulation results confirm the validity and effectiveness of the presented models and analysis method. [ABSTRACT FROM AUTHOR]

A modular multilevel converter control system, based on converter energy storage, is proposed in this paper for two different control modes: active power and dc voltage. The proposed control system decouples the submodule (SM) capacitor voltages from the dc bus voltage. One of the practical applications is the management of active redundant SMs. A practical HVDC system with 401-level MMCs, including 10% redundancy in MMC SMs, is used for validating and demonstrating the advantages of the proposed control system. This paper also presents a novel capacitor voltage balancing control based on \max–\min functions. It is used to drastically reduce the number of switchings for each SM and enhances computational efficiency. [ABSTRACT FROM AUTHOR]

The linear induction launcher consists of two parts: the barrel section and the projectile section. The barrel contains of a long coaxial sectionalized group of coils that are energized by a capacitor bank or generator sets. This paper deals with the design, implementation, and experimental test of a coreless axial-flux permanent magnet (AFPM) pulsed alternator with a flywheel system as an energy source for linear induction coil launchers. The proposed coreless AFPM generator has a low internal inductance and resistance of stator windings without compensation windings when compared with the conventional iron core machines. This paper describes the coreless AFPM generator configuration and shows the simulation findings. [ABSTRACT FROM AUTHOR]

A new lumped capacitance model that employs fractional order operators is proposed for use on transient heat conduction problems. Details and implications of the fractional lumped capacitance model's development and application are discussed. The model is shown to agree with observed heating and cooling temperature profiles of laser aiming paper being heated by a laser under various conditions. [ABSTRACT FROM AUTHOR]

The issue of sub-module (SM) capacitor voltage unbalance is a hot topic in the current research into the modular multilevel converter (MMC). An excellent strategy comprises mitigating the SM capacitor voltage imbalance by adjusting the SM on time. The traditional capacitor voltage balancing control regulates the speed to maintain accuracy. A unique SM capacitor voltage balancing control strategy is presented in this paper and is based on conventional capacitor voltage balance management and neural network prediction. Firstly, the SM capacitor voltage and arm current are speculated by operating the time series forecasting technique in real time, considering the dynamic changes in the SM capacitor voltage and arm current. Secondly, the SM capacitor voltage distinction between the actual and theoretical value is determined, and a deviation's mixed Gaussian distribution is established to estimate its compensation voltage. Thirdly, the SM triggering sequence is anticipated by using the neural network along with the pilot values of the SM capacitor voltage, arm current, and the offset compensation value, and the control is executed. Finally, a three-phase, six-leg, eight-module, nine-level MMC model is built to verify the feasibility of the suggested approach. [ABSTRACT FROM AUTHOR]

The capacitor mismatch among diverse defects caused by variations in the manufacturing process significantly affects the linearity of the capacitor array used to implement the capacitive digital-to-analog converter (CDAC) in the successive-approximation register (SAR) analog-to-digital converter (ADC). Accordingly, the linearity of the SAR ADC is limited by that of capacitor array, resulting in serious yield loss. This paper proposes an efficient foreground self-calibration technique to enhance the linearity of the SAR ADCs by mitigating the capacitor mismatch based on the split ADC architecture along with variable capacitors. In this work, two ADC channels (i.e., ADC1 and ADC2) for the split ADC architecture include their capacitive DACs (CDACs) whose binary-weighted capacitor arrays consist of variable capacitors. A charge-sharing SAR ADC is used for each ADC channel. In the normal operation mode, their digital outputs are averaged to be the final ADC output, as in a conventional split ADC. In the calibration mode, every single binary-weighted capacitor for the two ADCs is sequentially calibrated by making parallel or/and antiparallel connection among two or thee capacitors from the two channels. For instance, because the capacitors of the CDACs ideally exhibit the binary-weighted relation as C n = 2 × C n − 1 , the variable capacitor C n of ADC1 can be updated to be closest to the sum of C n − 1 of ADC1 and C n − 1 of ADC2 for the calibration. For the process, the two capacitor arrays of the two ADCs can be reconfigured to be connected to each other, so that the C n of ADC1 can be connected with two of the C n − 1 of ADC1 and ADC2 in antiparallel. The two voltages at the top and the bottom plates of the CDAC are compared by a comparator of ADC1, and the comparison results are used to update C n . This process is iterated, until C n is in agreement with the sum of two of C n − 1 . Finally, all the capacitors can be calibrated in this way to have the binary-weighted relation. The simulation results based on the proposed work with a split SAR ADC model verified that the proposed technique can be practically used, by showing that the total harmonic distortion and the signal-to-noise-and-distortion ratio were enhanced by 21.8 dB and 6.4 dB, respectively. [ABSTRACT FROM AUTHOR]

The capacitor voltage unbalancing is the common problem in modular multilevel converter. This problem occurs even at the fundamental frequency due to the modulation technique which generates the unequal periods of the gate signals. To reduce this problem, this paper introduced a new submodule (SM)-based modular multilevel converter (MMC). The proposed MMC can generate the 2N + 1 level at the load side. By properly controlling the arm current of the converter, DC capacitor voltage in each submodule is balanced at its base voltage and improves the circulating current during unequal periods of the gate signals without using controller. This paper presents the performance of new submodule-based modular multilevel converter. Finally, the proposed converter is compared with the conventional modular multilevel converter topologies with and without third harmonic injection method. Further the proposed structure and presented techniques have been simulated in the MATLAB/SIMULINK, and the practical implementation has been done using hardware-in-the-loop (HIL) test. [ABSTRACT FROM AUTHOR]

In this paper, a portable low-power low dropout regulator (LDO) with no output capacitance has been designed in 0.18- μ m CMOS technology. In this paper, a PMOS power transistor is used and combined with an overshoot and undershoot suppression circuit to improve the transient response of the circuit. A modified Class-AB operational transconductance amplifier (OTA) is used to reduce power consumption and act as an error amplifier to eliminate low frequency poles. At the same time, a super source follower and a Miller capacitor are used for frequency compensation of the system. Finally, the system can provide a stable voltage for a load step from 0.2 to 25 mA in 500 ns edge-time for 140 pF-load capacitance. The test results show that the circuit achieves a good voltage regulation rate and high transient response. [ABSTRACT FROM AUTHOR]

This paper studies the effect of the number of switching (NOS) per day of capacitor banks on loss reduction in radial distribution systems. To this aim, the daytime (more precisely, 24 h) is divided into different numbers of time segments (equal to the same NOS) for capacitors' size switching. The resulting non‐linear programming with discontinuous derivatives (called DNLP) model is solved subject to related constraints. The results reveal the impact of hourly switching of capacitor banks on further loss reduction (namely 118.4435, 83.7856, and 101.738 MWh for three IEEE systems) and higher net savings (i.e. k$5.6067, k$4.2772, and k$5.3542 for the same systems) of radial distribution systems compared to daily switching. Then, the hyper‐tuned Random Forest model is trained based on the IEEE 69‐bus network, fine‐tuned by the IEEE 10‐bus network, and fitted by the IEEE 33‐bus network to have an intelligent multi‐classification task with the highest accuracy. Numerical simulation, in both classic and intelligent parts, is presented to demonstrate the performance of DeepOptaCap. For the final step, DeepOptaCast is compared to other intelligent models of Light Gradient Boosting Method (LGBM), Decision Tree, and XGBoost, regarding KPIs of mean absolute percentage error, root mean squared percentage error, mean absolute error, root mean squared error, and coefficient of determination to demonstrate the model's superiority. [ABSTRACT FROM AUTHOR]

In this paper, it is proposed that a two-terminal high voltage direct current (HVDC) be integrated into the power system. Line-commutated converter (LCC)-HVDC is used because of its ability to reduce line losses, which improves overall system efficiency. Shunt capacitors also aid in voltage maintenance by compensating for the reactive power demand. In essence, limiting voltage drops in electrical networks promotes a more efficient power transmission and distribution by lowering resistive losses. In power system investigations, it was discovered that the HVDC link and SCB exist separately. So, for the first time, the backtracking search algorithm (BSA) is used to solve the optimal reactive power flow (ORPF) of a power system with a HVDC link and shunt capacitor banks (SCB). Although BSA simulations on a modified IEEE 30 bus yielded successful results, ABC was also utilized for comparing the outcomes of different methods. Overall, three separate cases of the modified IEEE 30 bus system were examined. When the acquired results are compared to other methods, the suggested algorithm is found to be better at concerning effectiveness as well as performance. [ABSTRACT FROM AUTHOR]

This paper introduces a cost-effective control method to enhance the low voltage ride-through (LVRT) capability and smooth the output power of a three-phase multilevel flying capacitor inverter (FCI) in wind turbine-based permanent magnet synchronous generator (PMSG). The proposed approach utilizes the energy storage capability of flying capacitors to mitigate wind power fluctuations and address short-duration outages and deep voltage sags. Additionally, a nonlinear controller based Lyapunov theory is developed to regulate capacitor voltages, improve power factors, and balance DC-link voltage. Numerical simulations are conducted in MATLAB/SimPower systems environment to validate the effectiveness of this comprehensive control strategy across different grid operation scenarios. [ABSTRACT FROM AUTHOR]

In order to improve wireless charging power and reduce heating problems, the optimal design of the high-current wireless charging coil has always been the research focus of wireless charging system research. This paper proposes a multi-branch and multi-capacitance current sharing method for series–series (SS) receiving coils. Firstly, the current sharing model with n branches that are connected parallel to multiple compensation capacitors is established. The current sharing situation of parallel coils with three branches and three capacitors with independently resonant compensation is analyzed. Then, the wireless charging system with the parallel coils of 48 V/100 A receiving coils is simulated. The results show that when one capacitor is used for compensation, the three-coil currents highly differ; when three capacitors are compensated independently, the three-coil currents are basically equal. The simulation results show that the current sharing method can effectively improve the charging power of the system and reduce the maximum temperature of the receiving coil, which proves the effectiveness of this method. Finally, through the experimental comparison, it is verified that the current sharing measure can make the current of each wire basically equal. [ABSTRACT FROM AUTHOR]

Featured Application: The methodology proposed in this article can be employed to improve the capability of the transmitting end of a WPT system to identify and adapt to parameter variations. This paper proposes a novel approach to simultaneously identifying multiple critical parameters in a wireless power transfer (WPT) system, such as the resonant frequency, mutual inductance, and load resistance, solely from the primary side. The key is to adopt a primary-side-switch-controlled capacitor (SCC) to ensure that the imaginary part of the input impedance is only caused by the secondary-side reflected impedance at three predesigned frequencies. The DSP controller then samples and processes the primary voltage and current using a gradient descent algorithm to derive the above parameters. After the identification, the SCC adjusts its equivalent capacitance based on the secondary-side practical resonant frequency to ensure a zero-phase angle (ZPA), thereby significantly improving the compatibility of the WPT system with unknown receivers. Compared to the previous frequency-sweeping method, the proposed approach is simpler and more suitable for deployment on the controller. Finally, experimental results demonstrate that the identification error of mutual inductance and resonant frequency are within 7.5% and 2.68%, respectively. [ABSTRACT FROM AUTHOR]

This paper proposes a 12-bit SAR ADC capable of calibrating a split capacitor using a binary search technique for bio-signal processing applications. The proposed SAR ADC employs a calibration logic circuit to calibrate a split capacitor vulnerable to process variations and mismatches. The proposed foreground calibration process involves four iterations through the binary search algorithm. In this manner, the calibration speed can be increased by up to 3.75 times compared with that of the linear search calibration. The proposed SAR ADC was implemented with a CMOS 28 nm 1-poly 8-metal process. The effective layout, excluding bonding pads, occupied 939 × 450 μ m. Measurement results illustrated a power consumption of 30.7 μ W (analog power: 16.1 μ W and digital power: 14.6 μ W), INL/DNL of −1.8/1.7 LSB, and −0.7/0.7 LSB, respectively, ENoB of 10.3-bit, and a FoM of 53.7 fJ/step. [ABSTRACT FROM AUTHOR]

This study presents an enhanced composite modular DC/DC converter topology designed to address critical technical requirements in wind power full DC systems, including high capacity, high conversion ratio, and fault isolation. The proposed topology combines MMC circuits and module combination circuits, allowing for exceptional modularity and configurability. Through the serial and parallel connection of multiple modules, the voltage or current levels can be further enhanced. Regarding the control strategy, the paper adopts SOGI phase-locked and coordinate transformation technology to precisely measure and control the differential and common-mode voltages within the MMC modules. A mathematical model is established, providing a theoretical foundation for experimental analysis. The research emphasizes the implementation of key strategies such as circulating current suppression, nearest level approximation, and capacitor voltage sorting. To validate the practicality and effectiveness of the proposed converter topology and control strategy, an experiment is conducted using a ±30 kV/±300 kV, 300 MW model constructed within the MATLAB/Simulink simulation environment. [ABSTRACT FROM AUTHOR]

The noise-shaping (NS) successive approximation register (SAR) analog-to-digital converter (ADC) is an innovative hybrid structure that offers performance advantages. The NS-SAR ADC leverages the SAR ADC as its foundation and combines oversampling technology and noise-shaping technology found in Sigma-Delta ADC. This integration effectively combines the strengths of both structures and enhances overall performance. The ADC features a simple circuit structure, compact chip area, and high energy efficiency, which has positioned it as a prominent research area. In this paper, leveraging the TSMC 65 nm GP process, the NS-SAR ADC is designed with a power supply voltage of 1 V. This design adopts an 8-bit differential capacitor structure, operates at a sampling frequency of 16 MS/s, and achieves an oversampling rate of 16 times the desired performance indicators. Through extensive circuit post simulation verification, the SNR obtained reaches 78 dB, providing an effective bit resolution of 12.7 bits. The core chip area of the ADC measures 366 × 333 μm2, while the power consumption is impressively low at 417 μW and FoMs is 168 dB. [ABSTRACT FROM AUTHOR]

This paper proposes an algorithm for determining the optimal capacitance by utilizing a mathematical model of a submodule (SM) capacitor in a modular multilevel converter (MMC) specifically for medium voltage motor drives (MVDs). By approximating the voltage fluctuation of the SM capacitor during low-frequency operation, it is feasible to ascertain the minimum capacitance required for the SM capacitor, ensuring that its voltage fluctuations remain within an acceptable limit that is predefined as a specified value. Moreover, the study considered the injection of both a high-frequency common-mode voltage (CMV) and a circulating current to alleviate the SM voltage fluctuation during the acceleration of motor drives. The effectiveness of the proposed method is validated through verification using time-domain simulation results obtained using the MATLAB/SIMULINK software and real-time simulation results acquired using the OPAL-RT simulator platform. [ABSTRACT FROM AUTHOR]

In the domain of automatic visual inspection for miniature capacitor quality control, the task of accurately detecting defects presents a formidable challenge. This challenge stems primarily from the small size and limited sample availability of defective micro-capacitors, which leads to issues such as reduced detection accuracy and increased false-negative rates in existing inspection methods. To address these challenges, this paper proposes an innovative approach employing an enhanced 'you only look once' version 8 (YOLOv8) architecture specifically tailored for the intricate task of micro-capacitor defect inspection. The merging of the bidirectional feature pyramid network (BiFPN) architecture and the simplified attention module (SimAM), which greatly improves the model's capacity to recognize fine features and feature representation, is at the heart of this methodology. Furthermore, the model's capacity for generalization was significantly improved by the addition of the weighted intersection over union (WISE-IOU) loss function. A micro-capacitor surface defect (MCSD) dataset comprising 1358 images representing four distinct types of micro-capacitor defects was constructed. The experimental results showed that our approach achieved 95.8% effectiveness in the mean average precision (mAP) at a threshold of 0.5. This indicates a notable 9.5% enhancement over the original YOLOv8 architecture and underscores the effectiveness of our approach in the automatic visual inspection of miniature capacitors. [ABSTRACT FROM AUTHOR]

This paper presents an improved switched‐inductor quasi‐Z‐source inverter with a higher boost factor than similar inverters, which integrates a switched‐capacitor and a three‐winding switched‐coupled inductor into a conventional quasi Z‐source inverter (q‐ZSI). The proposed inverter is called a switched‐capacitor trans quasi Z‐source inverter (SCT‐q‐ZSI). In this topology, the input current is continuous, and a high voltage gain is reachable with lowduty cycles (D). In this structure, capacitors are used instead of the side diodes of the switched‐inductor quasi Z‐source inverter. The proposed converter has a low inrush current at the startup which might damage the converter components. The performance of the proposed inverter is investigated at different operating modes and the voltage and current equations of all elements are calculated. The analysis, derivation of boost factor, capacitor voltages, and components, of the proposed inverter, are carried out and are compared with similar inverters. Finally, analytical, simulation, and experimental results are also presented to validate its advantages. [ABSTRACT FROM AUTHOR]

The problem of submodule switching frequency reduction in half‐bridge modular multilevel converters (HB‐MMCs) with capacitor voltage self‐balancing control is considered and explored in this paper. A selection principle of submodule switching state vectors is proposed based on the voltage self‐balancing switching state matrix, aiming to lower submodule switching frequency and device losses. The relationship between system stability and submodule switching signals is revealed according to the capacitor voltage self‐balancing characteristics, and the full‐rank constraints on the voltage self‐balancing switching state matrix are proposed. Considering the tradeoff between switching loss and capacitor voltage fluctuation, the evaluation indexes of voltage self‐balancing control effect are determined. The selection principle of submodule switching state vectors and the optimized construction method of switching state matrix are presented. Voltage self‐balancing HB‐MMC models are built in MATLAB/Simulink, and it is verified that the submodule switching state vector selection principle proposed in this study can effectively reduce switching frequency while meeting the evaluation requirements of practical engineering projects, so as to achieve the balance between switching loss and steady‐state capacitor voltage fluctuation. [ABSTRACT FROM AUTHOR]

This paper presents the design and application of a boost converter operated in continuous conduction mode for 15 W, with a 25 kHz switching frequency using an inductor-capacitor-inductor (LCL), pi, inductor capacitor (LC) with damping, and LC electromagnetic interference filters. Also, modeling and analysis of the boost converter in terms of state space and small signal are given. Furthermore, the effect of each filter on differential mode (DM) noise and control characteristics is presented using root locus and bode diagrams, which are not detailed in the literature for the boost converter. All results obtained from applications and simulations are compared. Moreover, frequency spectrums are given to compare DM noises. As a result, from a control point of view, the LCL filter provides better results, and for reducing DM noise, the LC and pi filters are superior to others. Besides, the LCL filter reduces the inductor value by 30% compared to other filters. [ABSTRACT FROM AUTHOR]

For decentralized electrification in remote areas, small-sized wind energy systems (WESs) are considered sustainable and affordable solution when employing an efficient, small-sized component converter integrated with a less-sophisticated, cost-effective MPPT controller. Unfortunately, using a conventional buck DC/DC converter as a MPP tracker suffer from input current discontinuity. The latter results in high ripples in the tracked rectified wind power which reduces the captured power and affects system operation especially in standalone applications which are self-sufficient and independent of grid support. Furthermore, these ripples propagate to the machine side causing vibration and torque stress which impacts turbine performance and safety. To solve this issue, a large electrolytic capacitor is placed at the buck converter input to buffer these ripples, yet at the cost of larger size, losses and reduced reliability. Oppositely, the developed C1, D4 and D6 buck converters have the merit of continuous input current at small component-size. In this paper, dynamic modelling of these three converters is developed to select the one with the least input current ripples to replace the traditional buck converter in the considered WES system. Consequently, fluctuations in the tracked power are minimized and the large buffer capacitor is eliminated. This enhances system lifetime, reduces its cost and increases tracking efficiency. Moreover, mechanical power and torque fluctuations are minimized, thus maintaining machine protection. Furthermore, a sensorless MPPT algorithm, based on converter averaged state-space model, is proposed. Being dependent on variable-step P&O algorithm, the proposed approach features simple structure, ease of control and a compromise between tracking time and accuracy besides reduced cost due to the eliminated current sensor. Simulation results verified the effectiveness of the selected converter applying the proposed MPPT approach to efficiently track the wind power under wind variations with cost-effective realization. [ABSTRACT FROM AUTHOR]