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On the development of flexible electronics, a highly flexible nonvolatile memory, which is an important circuit component for the portability, is necessary. However, the flexibility of existing nonvolatile memory has been limited, e.g. the smallest radius into which can be bent has been millimeters range, due to the difficulty in maintaining memory properties while bending. Here we propose the ultra flexible resistive nonvolatile memory using Ag-decorated cellulose nanofiber paper (CNP). The Ag-decorated CNP devices showed the stable nonvolatile memory effects with 6 orders of ON/OFF resistance ratio and the small standard deviation of switching voltage distribution. The memory performance of CNP devices can be maintained without any degradation when being bent down to the radius of 350 mm, which is the smallest value compared to those of existing any flexible nonvolatile memories. Thus the present device using abundant and mechanically flexible CNP offers a highly flexible nonvolatile memory for portable flexible electronics. [ABSTRACT FROM AUTHOR]

In this paper, a double-pole double-throw analog switch with n-channel architecture driven by a charge pump is described. The architecture proposed in this paper not only can reduce the on-resistance of the complementary metal oxide semiconductor (CMOS) switch, but also can realize a stable on-resistance within the full swing range of the input signal. This analog switch has the characteristics of high-speed, low-voltage, and high linearity, which is suitable for high-speed USB (Universal Serial Bus) 2.0 applications and meets low-speed and full-speed USB requirements. The test chip using a 0.25 μm BCD (bipolar–CMOS–DMOS) process confirms the characteristics of the switch. It uses + 2.8 to + 5.5 V single power supply, and the normal operating temperature range is − 40 to + 85 °C. This switch has an over-voltage protection function, which can prevent damage to the switch from the high input voltage. Besides, the switch port can realize dual-direction transmission. The analog switch designed in this paper solves some problems of traditional analog switches, such as large on-resistance, large supply current, and large parasitic capacitance. The on-resistance of the analog switch architecture in this paper is 5 Ω and the on-resistance flatness is 0.1 Ω. The supply current is as low as 0.87 μA while the whole chip area is 0.65 mm2. [ABSTRACT FROM AUTHOR]

This paper proposes an array structure with multidirectional remanent magnetization based on hard-magnetic soft materials, which can be used as a soft switch array on planar and curved surfaces. We firstly investigate the displacement response of a hard-magnetic soft switch which is excited by a magnetic field, and related to the magnitude and direction of the magnetic field. When the remanent magnetization direction of the soft switch is opposite to the horizontal component of the magnetic field, the displacement response is greater than that of the driving magnetic field in other directions. The maximum displacement of the soft switch can reach 4.5 mm under a 6 V driving voltage applied to the Helmholtz coil. We further design 2 × 2 and 3 × 3 switch arrays and the circuit structures of the switch arrays. The switch arrays are fabricated, and the displacement responses of the switch arrays under different driving magnetic fields on planar and curved surfaces are finally demonstrated. When the Z-axis displacement of the device reaches more than 3 mm, the LED light can be switched on. The hard-magnetic soft switch array structure designed in this paper can enable the application of soft switches in curved environments, verifying the feasibility of the application of hardmagnetic soft switch arrays. It is expected to provide a guidance for the design and manufacturing of multi-functional hard-magnetic soft switches in the future and the application of hard-magnetic soft switch arrays in planar and curved environments. [ABSTRACT FROM AUTHOR]

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This paper is an extended version of a previously reported conference paper regarding a low-power design for NAND Flash. As the number of bits per NAND Flash die increases with cost scaling, the IO data path speed increases to minimize the page access time with a scaled CMOS in IOs. The power supply for IO buffers, namely, VDDQ, decreases from 3 V to 1.2 V, accordingly. In this paper, the way in which a reduction in VDDQ can contribute to power reduction in the BL path is discussed and validated. Conventionally, a BL voltage of about 0.5 V has been supplied from a supply voltage source (VDD) of 3 V. The BL path power can be reduced by a factor of VDDQ to VDD when the BL voltage is supplied by VDDQ. To maintain a sense margin at the sense amplifiers, the supply source for BLs is switched from VDDQ to VDD before sensing. As a result, power reduction and an equivalent sense margin can be realized at the same time. The overhead of implementing this operation is an increase in the BL access time of about 2% for switching the power supply from VDDQ to VDD and an increase in the die size of about 0.01% for adding the switching circuit, both of which are not significant in comparison to the significant power reduction in the BL path power of the NAND die of about 60%. The BL path is then designed in 180 nm CMOS to validate the design. When the cost for powering the SSD becomes quite significant, especially for data centers, an additional lower voltage supply, such as 0.8 V, dedicated to BL charging for read and program verifying operations may be the best option for future applications. [ABSTRACT FROM AUTHOR]

With the development of the photovoltaic industry; there will be an increasing demand for efficient, high-power density, and low-cost grid interface converters. Compared with two-level inverters, multilevel inverters have the following advantages: (1) lower device voltage ratings; (2) better output filtering spectrum; (3) lower electromagnetic interference (EMI) noise; and (4) higher switching speed capability. However, the complex switching circuit of the multilevel inverter will bring more parasitic inductance, resulting in severe switching overvoltage (ringing). Especially in order to reduce the cost of the inverter, using the long-loop modulation mode, the commutation loop will introduce more parasitic inductance, which will make the overvoltage more serious. Consider that commonly used overvoltage absorption schemes are effective only for overvoltage or suppression of oscillations. Therefore, a new overvoltage absorption circuit is proposed in this paper, which can not only alleviate the overvoltage and ringing phenomena but also suppress the effect of voltage jumps during low-frequency switching on high-frequency input voltage. This overvoltage absorption circuit is characterized by low overvoltage, fast ringing damping, and minimum capacitance. Experiments and simulations are conducted to verify the effectiveness of this overvoltage absorption circuit using a three-level ANPC inverter as a prototype. The results show that the proposed overvoltage absorption circuit can significantly reduce the overvoltage level, shorten the oscillation time, and reduce the voltage difference between the upper and lower DC bus capacitors. [ABSTRACT FROM AUTHOR]

This paper concentrates on the issue of anti-disturbance bumpless transfer (ADBT) control design for switched systems. The ADBT control design problem refers to designing a continuous controller and a switching rule to ensure the switched system satisfies the ADBT property. First, the concept of the ADBT property is introduced. Then, via a switched equivalent-input-disturbance (EID) methodology, a switched EID estimator is formulated to estimate the impact of external disturbances within the switched system. Second, a bumpless transfer control is then constructed via a compensator integrating an EID estimation. Finally, the effectiveness of the presented control scheme is verified by controlling a switching resistor–inductor–capacitor circuit on the Matlab platform. Above all, a new configuration for ADBT control of switched systems is established via a switched EID methodology. [ABSTRACT FROM AUTHOR]

Newly introduced Photovoltaic (PV) devices, featuring a built-in chip with an illuminating Light Emitting Diode (LED), have emerged in the commercial market. These devices are touted for their utility as both low- and high-side power switch drivers and for data acquisition coupling. However, comprehensive knowledge and experimentation regarding the limitations of these Photovoltaic Drivers in both switching and signal processing applications remain underexplored. This paper presents a detailed characterization of a Photovoltaic Driver, focusing on its performance under resistive and capacitive loads. Additionally, it delineates the device's constraints when employed in signal processing. Through the analysis of switching losses across various power switches (Silicon and Silicon Carbide) in both series and parallel driver configurations, this study assesses the driver's efficacy in operating Junction Field-Effect Transistors (JFETs). Findings suggest that Photovoltaic Drivers offer a low-cost, compact solution for specific applications, such as high-voltage, low-bandwidth measurements, and low-speed turn-on with fast turn-off power switching scenarios, including solid-state switches and hot-swap circuits. Moreover, they present a straightforward, cost-effective method for driving JFETs, simplifying the circuit design and eliminating the need for an additional negative power source. [ABSTRACT FROM AUTHOR]

This paper proposes a new high step‐up DC–DC converter with zero input current ripple for renewable energy sources applications, such as fuel cells. In this topology, a coupled inductor and a multiplier cell are used to achieve high voltage gains. The power switch in this proposed circuit turns on under zero voltage switching conditions. An active switch limits the maximum voltage stress across the main power switch. Moreover, all circuit diodes of the converter turn off without a reverse recovery problem. A detailed analysis of a high‐gain step‐up DC–DC converter is studied along with improved efficiency. The ripple cancellation of the input stage of the converter is done by adding an input inductor and capacitor. By including the parasitic elements, an approximate loss analysis was performed in PSIM and found the maximum efficiency of ∼96% in simulation and ∼94% in hardware for 200 W power level design for 30 V input voltage. Later on, the converter laboratory hardware prototype can be developed with selected parameters, and finally, experimental results have been used to validate the properties of the converter. [ABSTRACT FROM AUTHOR]

The traditional light source of projection lamps adopts a halogen lamp, which has the advantages of high brightness, but its luminous efficiency is not good and consumes energy. A light-emitting diode (LED) has the characteristics of high luminous efficiency and energy savings and can be used as a new light source for projection lamps. The conventional two-stage electronic lighting driver circuit for supplying an LED projection lamp is composed of an AC-DC converter with power factor correction (PFC) as the first stage and a DC-DC converter for providing rated lamp voltage and current as the second stage. The conventional LED projection lamp driver circuit has more circuit components, a higher cost and limited efficiency. Therefore, this paper proposes a novel electronic lighting driver circuit for supplying an LED projection lamp with PFC function, which integrates a modified stacked dual boost converter and a half-bridge LLC resonant converter into a single-stage power-conversion circuit. The inductor inside the modified stacked boost converter is designed to operate at discontinuous conduction mode (DCM) for the driver circuit achieving PFC. Wide bandgap semiconductor devices silicon carbide (SiC)-based Schottky diodes are utilized to reduce power diode losses, and soft switching is implemented in the proposed LED projector lamp driver circuit to reduce the switching losses of the power switches and thus improve circuit efficiency. This paper has completed a single-stage prototype driver circuit for an LED projection lamp with PFC function, and the prototype circuit has a high power factor (PF > 0.98), low input current total-harmonic-distortion (THD < 6%) and high efficiency (>89%) in the case of an AC input power supply with an RMS value of 110 volts, and both power switches have the characteristics of soft switching. [ABSTRACT FROM AUTHOR]

This paper reports on the testing and evaluation of a passive autoranging (AR) method designed to dynamically extend the measurement range of a photonic current transducer (PCT) to pave the way toward a realization of a combined metering- and protection-class current sensor. The PCT utilizes a current transformer (CT), a piezoelectric transducer (PZT), and a fiber Bragg grating (FBG) to enable current measurement at multiple points in an electrical power network whereby multiple sensors are deployed and interrogated serially using a single optical fiber. The autoranging technique relies on incorporating static MOSFET switches to instantaneously short individual serially connected CT burdens in response to a measured current magnitude exceeding pre-set thresholds. The AR circuit switching events produce distinctive signal features that are used by the proposed switching algorithm to apply appropriate scaling factors to reconstruct the measured current from the optical signal. It is shown through laboratory experiments that the AR circuit correctly reacts to pre-set burden current thresholds of 130% of the nominal value and 22 times the nominal value, signifying its "metering" and "protection" range boundaries. The circuit reaction time is below 4 ms, rendering it suitable for standard power system protection purposes. Moreover, the operation of the AR circuit is demonstrated for burden currents of up to 100 A for over 1 s, satisfying a test procedure for the secondary CT circuit, as required by some power system operators. It is demonstrated that the proposed switching algorithm allows for a correct reconstruction of the burden currents from the optical signal acquired by the FBG interrogator, offering the potential to realize a dual-class optical current sensor. [ABSTRACT FROM AUTHOR]

This study investigates the asymptotic synchronization in fractional memristive neural networks of the Riemann–Liouville type, considering mixed time delays and jump mismatches. Addressing the challenges associated with discrepancies in the circuit switching speed and the accuracy of the memristor, this paper introduces an enhanced model that effectively navigates these complexities. We propose two novel event-based hybrid impulsive controllers, each characterized by unique triggering conditions. Utilizing advanced techniques in inequality and hybrid impulsive control, we establish the conditions necessary for achieving synchronization through innovative Lyapunov functions. Importantly, the developed controllers are theoretically optimized to minimize control costs, an essential consideration for their practical deployment. Finally, the effectiveness of our proposed approach is demonstrated through two illustrative simulation examples. [ABSTRACT FROM AUTHOR]

Three distinct synchronized switching circuits based on a magnetostrictive actuator are compared in this paper to examine their control mechanisms and circuit characteristics. These circuits include a semi-active shunt circuit, a semi-active current inversion and amplification circuit, and a semi-active automatic current inversion and amplification circuit. Each circuit type employs an additional electronic switch. The synchronized switching method enables the rational control of the circuit current generated by the magnetostrictive actuator to fulfill any desired control strategy. Simulation and experimental results on a 10-bay truss structure reveal that the three circuits can effectively adjust the polarity of the induced current as needed. The three circuits are then compared to thoroughly analyze their unique characteristics and explain their respective advantages and dis-advantages. Using the comparison results, various options available for control circuit design are demonstrated. [ABSTRACT FROM AUTHOR]

This paper proposes a new transformerless buck‐boost converter with an extended voltage conversion ratio. This converter has semi‐quadratic voltage gain, which provides more gain with lower duty cycles. This converter has a simple structure and easy implementation, which reduces the cost and increases efficiency. The proposed converter operates in continuous conduction mode and provides two operation modes by turning on and off the switches. The suggested converter has continuous input current and low input current ripple, which is important when utilizing renewable energy sources. The calculation of the proposed converter includes ideal and practical voltage gain, current calculations, voltage stresses of the switches and diodes, current stress of the switches, parameter design, efficiency, and a brief analysis of discontinuous conduction mode and boundary conditions. The proposed converter provides efficiency of about 93.1% in boost mode and 92.14% in buck mode at 50 W output power. The suggested converter varies the input voltage from 20 to 48 V in boost mode and changes the input voltage from 20 to 10.4 V in buck mode. Finally, a laboratory prototype has been built to prove and evaluate the simulation results and theoretical analysis of the proposed converter. [ABSTRACT FROM AUTHOR]

With the development of high-voltage and high-frequency switching circuits, GaN high-electron-mobility transistor (HEMT) devices with high bandwidth, high electron mobility, and high breakdown voltage have become an important research topic in this field. It has been found that GaN HEMT devices have a drift in threshold voltage under the conditions of temperature and gate stress changes. Under high-temperature conditions, the difference in gate contact also causes the threshold voltage to shift. The variation in the threshold voltage affects the stability of the device as well as the overall circuit performance. Therefore, in this paper, a review of previous work is presented. Temperature variation, gate stress variation, and gate contact variation are investigated to analyze the physical mechanisms that generate the threshold voltage (VTH) drift phenomenon in GaN HEMT devices. Finally, improvement methods suitable for GaN HEMT devices under high-temperature and high-voltage conditions are summarized. [ABSTRACT FROM AUTHOR]

A new modular pulsed-power source with fast rise time and step-wise arbitrary output waveform generation is currently under development to drive the Gepulste Elektronenstrahlanlage device investigated at the Institute for Pulsed Power and Microwave Technology (IHM). Acknowledging the complex design procedures necessary to set up a modular pulsed-power source for voltages of up to 120 kV, this paper focuses on the circuit design for a single stage and its validation prior to the generator assembly. Using a semiconductor-based Marx generator topology, the stages are designed to have an output voltage of 1 kV with a pulse current of up to 600 A. When connected to an ohmic load, the measured current rise times are in the order of 46 ns resulting in the current rise rates of up to 10 kA/ $\mu \text{s}$ using the commercial devices. The step-wise arbitrary output waveform is created by generating the switching commands on the stage using a microprocessor and a fast optical synchronization unit. Effective stage shielding is verified by operating the stage in a 100-kV, 2.5-kA electromagnetic interference test bed. This paper presents the design considerations and the corresponding measurements. [ABSTRACT FROM AUTHOR]

Reliability is a fundamental concept for power systems, and the optimal placement of switchable devices is a valuable tool for improvements in this area. The goal of this paper is to propose an optimal allocation method for circuit breakers and switches that can break the cost–reliability dilemma and simultaneously achieve reliability and economic improvement in terms of the distribution network. Moreover, in view of the fact that variations in the load level can affect the reliability of the distribution network, the variations of different load level scenarios are considered in this paper, where a mixed integer linear programming (MILP) model based on fictitious fault flows is established to derive the optimal allocation scheme that can adapt to the changes of multiple scenarios regarding the load. Meanwhile, due to the constraints of reliability indices, the post-fault reconfiguration scheme of a distribution network under different load level scenarios can also be obtained to enhance its overall reliability. Finally, the applicability and effectiveness of the proposed method are verified by numerical tests on a 54-node test system. [ABSTRACT FROM AUTHOR]

In this paper, a dual-mode step-down DC-DC converter with an automatic mode-switching circuit is implemented in a 28 nm digital CMOS process and embedded in an RF transceiver chip to power the digital part. The proposed automatic mode-switching circuit includes a frequency-voltage conversion circuit that is designed according to the principle of charge redistribution on capacitance. The converter can switch modes according to the load without external intervention. This converter, along with a PMU sequencer, can also provide a solution for low-power design for system-on-chip applications. The IC occupies a total die area of 0.378 mm2. The input voltage of the converter is 3.3 V, the output voltage is 1.05 V, and the maximum load current can reach 1 A. The converter shows a conversion efficiency of not less than 81% at a full load range and can achieve a peak conversion efficiency of 91% when the load current is 100 mA. The load range of the PWM mode is 1 A to 50 mA, and that of the PFM mode is 100 mA to 1 mA. The combination of zero-crossing detection circuitry and freewheel switches can reduce energy loss and eliminate additional electromagnetic interference. [ABSTRACT FROM AUTHOR]

This paper defines a new type of a low-power broadside test, called a reverse low-power broadside test, whose application requires design-for-testability logic. The unique feature of a reverse low-power broadside test is that it duplicates the switching activity during the second functional capture cycle of a given low-power broadside test, except that signal-transitions are reversed. Thus, the switching activity of a reverse low-power broadside test duplicates that of a low-power broadside test in every subcircuit and on every line individually. In addition, the reversed test detects different faults, and can thus increase the fault coverage of a low-power broadside test set. This paper studies the ability of reverse low-power broadside tests to increase the transition fault coverage in benchmark circuits considering functional broadside tests as well as low-power broadside tests that are not functional. [ABSTRACT FROM AUTHOR]

With the increasing adoption of solar Photovoltaic (PV) systems in several applications, reliability and service continuity are important challenges that need to be addressed. Power converters are vital components in solar PV systems and inverters tend to be the most likely devices of equipment to experience faults which usually occur in the switching devices. It is therefore critical to assess the functioning of the inverters and identify these faults in order to lower risks and the resulting financial losses. Open-circuit faults (OCF) are among the most common. This paper suggests a fuzzy-based fault detection approach for the T-Type inverter in grid connected PV system based on the diagnosis variables which are calculated using the average values of positive and the negative parts of the normalized output currents data. After that, these variables are analyzed using a fuzzy logic technique, The single, multiple power switch open circuit faults may all be detected and diagnosed utilizing this fuzzy-based fault diagnostic technique. The results of the simulation in MATLAB show that the proposed method can accurately identify and locate OCF the inverter switches. [ABSTRACT FROM AUTHOR]

This paper investigates the starting current of an AC/DC/DC converter, consisting of a threephase diode bridge rectifier and a synchronous buck converter. The use of microprocessors in such converters increases the total cost and also reduces reliability due to EMI phenomena. For this reason, by removing the microprocessor, a start-up plan including a limiting starting resistor and then soft starting the switching module is proposed in this paper. By modeling the system under different operating modes, a solution is presented to minimize the circuit startup period, which includes minimizing the bypass time of the startup resistor and reducing the switching soft startup period as possible. The proposed method has been implemented on a 15-kW converter feeding from a three-phase 380 V power grid and provides up to 300 Vdc/50 Adc to supply an electroplating pool. The results show that the sequential startup procedure, including using a 50 ohm/1500 w resistor for 3 seconds, and then bypassing it, then soft start switching after half a second and during 1.5 s, can move this circuit to a steady state in 5 seconds, keeping current in all parts below half rated current. [ABSTRACT FROM AUTHOR]

The solid-state Marx pulse generator is widely used in various fields such as biomedical electroporation, food processing, and plasma material modification. In this paper, an inductor is chosen as an isolation device and by adding a switch to the circuit, a solid-state boost-Marx pulse generator (BMPG) is formed. On the one hand, the inductor forms a boost circuit to multiply the output voltage gain, and on the other hand, it solves the shortcomings of conventional Marx pulse generators where the charging speed and total efficiency during high-frequency pulse generation are drastically affected by the isolation resistor. The selection criteria for inductors is well derived. Based on the PSpice simulation verification, a 12-module prototype of BMPG is built. The test results show that the circuit can achieve 10 kV high-voltage pulse output with a pulse width of 200–1000 ns and an adjustable repetition frequency of 0–10 kHz. While the input DC voltage requirement is only 235 V, the pulse voltage boost multiple is up to 42.5 times. Additionally, with the different switching sequences, the proposed BMPG can realize the adjustable change of pulse rising time and falling time. [ABSTRACT FROM AUTHOR]

This paper has introduced two important indexes, turn-off surge voltage (TSV) on power switch and peak positive pole potential (PPPP) of storage batteries, which can be used to evaluate switching transient process of high-voltage energy storage system. Research on them is of great significance to power switch choice and high-voltage isolation design in engineering applications. Power switch response process at the turning off moment and transient process in freewheel stage have been analyzed by the established small-signal model of single power switch; then, a power switch test platform for hybrid energy storage system was built to verify it. Taking pulsed-power supply charging device with a novel inductor of low resistance and high inductance as a research object, this paper has analyzed dynamic process of the TSV and the PPPP at the turning off moment through establishing state space model of the whole system. Comparison shows that the numerical curves match the simulated curves well. Finally, the exactness of the employed model has been further verified in two pulse capacitor charging experiments. [ABSTRACT FROM AUTHOR]

This paper presents a non‐intrusive method for identifying the load state of a distribution network. The method focuses on continuously varying loads. By considering the load on‐off state switching points and the continuous features at on state, a deep convolutional method considering non‐local spatiotemporal features is proposed. The addition of an attention component to the convolutional network enhances the non‐local feature extraction capability of the convolutional network. Ultimately, the effectiveness of the method is demonstrated in an experimental setting. In addition, this paper demonstrates that the proposed method can effectively integrate switching point features as well as persistent features through neural network visualization techniques. [ABSTRACT FROM AUTHOR]

This paper presents an optimization framework for sequential reconfiguration using an assortment of switching devices and repair process in distribution system restoration. Compared to existing studies, this paper considers types, capabilities and operational limits of different switching devices, making it applicable in practice. We develop a novel multi-phase method to find the optimal sequential operation of various switching devices and repair faulted areas. We consider circuit breakers, reclosers, sectionalizers, load breaker switches, and fuses. The switching operation problem is decomposed into two mixed-integer linear programming (MILP) subproblems. The first subproblem determines the optimal network topology and estimates the number of steps to reach that topology, while the second subproblem generates a sequence of switching operations to coordinate the switches. For repairing the faults, we design an MILP model that dispatches repair crews to clear faults and replace melted fuses. After clearing a fault, we update the topology of the network by generating a new sequence of switching operations, and the process continues until all faults are cleared. To improve the computational efficiency, a network reduction algorithm is developed to group line sections, such that only switchable sections are present in the reduced network. The proposed method is validated on the IEEE 123-bus and 8500-bus systems. [ABSTRACT FROM AUTHOR]

A double-pole double-throw analog switch circuit structure with low power consumption, low on-resistance and capable of transmitting negative signals is designed in this paper, which has been developed in 0.18 μm BCD technology. The analog switch circuit is providing about 5 V high swing signal transmission for 2.7–5 V supply voltage in the temperature range of − 40 to 85 °C. The shortcomings of traditional analog switch structure are large on-resistance, large power consumption, etc. In this paper, the charge pump structure of the gate voltage bootstrap switch is designed to overcome the backgate effect, to control the turn-on and turn-off of each switching MOS transistor. A dynamic comparator structure is used to enhance the signal transmission capability, so that the analog switch can transmit negative signal. The measurement results show that under the voltage of 2.7–5 V, the overall designed circuit consumes 92 μW. The on-resistance of the analog switch is 3.9 Ω, and the leakage current is 12 nA. The analog switch has a good signal transmission and shutdown capabilities while occupying an area of 0.67 mm2. [ABSTRACT FROM AUTHOR]

Excessive switching activity in the fault-free circuit can cause a fault-free circuit to fail because of increased delays. For the same reason, excessive switching activity in a faulty circuit can cause a delay fault to escape detection. This paper observes that the switching activity is higher in the presence of multiple delay faults with higher multiplicities (larger numbers of single faults that are present in the circuit together). The challenge in addressing multiple faults is related to their large number. This paper addresses this challenge by an iterative procedure that is applied to transition faults under a low-power broadside test set, and has two subprocedures: 1) the first subprocedure finds multiple transition faults with excessive faulty switching activity and 2) the second subprocedure modifies the test set so as to avoid excessive faulty switching activity for the faults found by the first subprocedure. With every additional iteration there are fewer multiple transition faults that exhibit excessive faulty switching activity. The experimental results for benchmark circuits demonstrate the levels of excessive faulty switching activity in the presence of multiple transition faults, and the possibility of reducing or even eliminating it after a small number of iterations. [ABSTRACT FROM AUTHOR]

This paper extends the analysis of the stability of electromagnetic transient simulation algorithms to non-linear systems with switching elements and non-linear inductor branches. A theoretical analysis based on common quadratic Lyapunov function theory is used to investigate the stability of numerical algorithms for the simulation of lumped strictly passive switched circuits (LSPSC). It is proved that only when certain fundamental physical properties, i.e., passivity and invariance of Lyapunov energy function, are satisfied, the widely used trapezoidal method results in stable simulations of such networks for any time-step size. This is different from the simulation of linear time invariant systems where any real-world stable system has a stable simulation if an A-stable integration method (e.g., trapezoidal rule) is used. Subsequently, it is shown that the problem of simulating a piecewise linear inductor can be equivalent to simulating a LSPSC; and ergo its simulation with the trapezoidal rule is also stable. [ABSTRACT FROM AUTHOR]

The dynamic on‐state resistance instability of a high‐current cascode multi‐GaN‐chip power module under high frequency and voltage switching conditions is demonstrated in this paper. The presented double pulse test topology is utilized to evaluate switching dependencies on voltage, current, and frequency, showing its versatility in investigating the switching instability of the device. The extended defects in the buffer layer resulted in a decrease in dynamic on‐state resistance (RDS‐ON) under hard switching conditions. Despite this, no noticeable RDS‐ON degradation occurs under harsh switching conditions due to electron de‐trapping. This study comprehensively analyzes the dynamic stability of a multi‐GaN‐chip cascode module with devices. [ABSTRACT FROM AUTHOR]

The purpose of the present research endeavor is to propose a novel control strategy for a DC-DC electrical converter realized as a switched circuit. The present endeavor is based on an early work by Leonard and Krishnaprasad where a prototypical DC-DC converter was modeled as a state space dynamical system and controlled by an open-loop strategy based on Lie group theory. In this work, we shall rather introduce a closed-loop control strategy based on maximum convergence rate, study some features of the novel method, and illustrate its behavior by numerical simulations. A numerical comparison of the two methods complements the paper. The numerical comparison shows how the proposed feedback control method outperforms the static one in terms of convergence rate and resiliency against parameters mismatch. [ABSTRACT FROM AUTHOR]

Magnetic tunnel junction (MTJ)-based devices have been studied extensively as a promising candidate to implement hybrid energy-efficient computing circuits due to their nonvolatility, high integration density, and CMOS compatibility. In this paper, MTJs are leveraged to develop a novel full adder (FA) based on 3- and 5-input majority gates. Spin Hall effect (SHE) is utilized for changing the MTJ states resulting in low-energy switching behavior. SHE-MTJ devices are modeled in Verilog-A using precise physical equations. SPICE circuit simulator is used to validate the functionality of 1-bit SHE-based FA. The simulation results show 76% and 32% improvement over previous voltage-mode MTJ-based FA in terms of energy consumption and device count, respectively. The concatanatability of our proposed 1-bit SHE-FA is investigated through developing a 4-bit SHE-FA. Finally, delay and power consumption of an n -bit SHE-based adder has been formulated to provide a basis for developing an energy efficient SHE-based n -bit arithmetic logic unit. [ABSTRACT FROM PUBLISHER]

Scan-based tests that maintain close-to-functional operation conditions are important for avoiding overtesting of delay faults while achieving the fault coverage required for avoiding test escapes. For a measurable proximity to functional operation conditions, partially functional broadside tests have a known Hamming distance between their scan-in states and reachable states. Another parameter that is important for the discussion of overtesting is the switching activity. This paper suggests a combined metric, where a reduced switching activity is taken as a safety margin that allows a higher Hamming distance between the scan-in state and a reachable state. The metric is defined such that a value of 100% or lower is preferred. To demonstrate that the metric is flexible enough to allow tests to be generated, the paper describes a test generation procedure that uses the metric. [ABSTRACT FROM PUBLISHER]

This paper focuses on the design, performance modeling, and evaluation of probabilistic logic using superparamagnetic nanomagnets for which there exists a strong interplay between deterministic dynamics and intrinsic thermal noise. The switching element in the spin domain is chosen as the giant spin-Hall effect (GSHE) device that operates based on the dipolar coupling phenomenon in a two-magnet system to achieve low-energy ( $\approx ~1.3$ fJ/b) and low-power ( $\approx ~0.5~\mu $ W) switching characteristics. The use of spin currents on the order of a few tens of mA/ $\mu $ m2 in the subcritical regime to operate the GSHE device yields nondeterministic switching behavior with probability of correctness less than 100%. Therefore, the proposed technique allows us to trade off circuit accuracy for tremendous reduction in energy and power dissipation. In this paper, we identify the required dimensions and material parameters of the read–write units to ensure robust magnetic dipolar coupling for reliable operation of the GSHE switch. Then, through Monte Carlo simulations, we evaluate the probabilistic switching behavior of the GSHE switch as a function of the input spin current amplitude and pulsewidth for various orientations of the magnetization vectors. The delay of the GSHE switch is quantified using a probability distribution function owing to the randomness imparted to the dynamics by intrinsic thermal noise of the nanomagnets. The relationship between the probability of correctness and the energy dissipation of the GSHE switch is quantified. The results are extended to evaluate the performance and circuit error rate of complex logic gates, such as NAND and NOR, constructed using the GSHE switch. It is shown that unlike the probabilistic CMOS (PCMOS) logic, the circuit error rate in the GSHE logic becomes a function of the input vector combination and the prior state of the switch. These nuances are captured in the compact model of the circuit error rate of multiple-input GSHE logic developed in this paper. The performance of the probabilistic GSHE logic is compared with that of PCMOS logic at the 14 nm technology node. Since the noise generation process in PCMOS logic has a limited bandwidth of tens of megahertz and consumes tens of microwatt power, the peripheral circuitry becomes prohibitive. By utilizing the inherent thermal stochasticity, nanomagnets provide a clear advantage to implement probabilistic computing platform targeted toward error-tolerant applications such as those from the image processing and machine learning domains. [ABSTRACT FROM AUTHOR]

This paper presents the effect of stray capacitances in bipolar (negative and/or positive) pulses generated by the two different topologies of the solid-state Marx modulators. According to the analysis, the stray capacitances influence the energy transfer from the Marx modulator capacitors to the load affecting the bipolar (negative and/or positive) pulse rise time. This paper deals with the structure design to reduce the influence of the stray capacitance and to improve the pulse rise time of these bipolar solid-state Marx modulators. A four-stage laboratory prototype of the two topologies has been assembled using 1200-V insulated gate bipolar transistors and diodes, operating with 1000-V dc input voltage and 1-kHz frequency, producing 4-kV bipolar pulses, with 5- \mu \texts pulse duration and 120-ns rise time, into a resistive load. [ABSTRACT FROM PUBLISHER]

Power grid modernization is often associated with new projects that imply the transmission network expansion, where transient overvoltages related to energization maneuvers must be studied in advance using suitable tools that consider the transmission line characteristics. Switching transient analysis is one of the options to deal with this phenomenon, but statistical switching analysis is the preferred tool to carry out multiple simulations. As opposed to existing works, this paper proposes a comprehensive approach for the statistical switching in double-circuit transmission lines based on existing transmission infrastructure that requires the installation of double-line circuits or resizing the existing ones. The switching sequence of circuit breakers based on distribution functions are discussed in detail, which are generalized using different standard deviations. Pre-insertion resistors and shunt reactors are also considered in this methodology, enabling practical results related to the calculation of the basic insulation level. All these aspects combined permit to establish the minimal requirements for the insulation coordination in double-circuit transmission lines from a practical standpoint. To showcase the method's practicality, the switching analysis of a 300-km double-circuit transmission line is conducted using the EMTP/ATP simulation package. Energization maneuvers with pre-insertion resistors and shunt reactors are studied, considering the transmission line operation at 230 and 400 kV, concluding that the minimal requirement of protection against transient overvoltages must be around 1.35 p.u. [ABSTRACT FROM AUTHOR]

Power Electronics applications for the metal industry deal with high voltage and currents. The heat dissipation of the power losses of the static switches should be the most appropriate in terms of reliability, power density, and cost. This paper discusses an oil immersion heat dissipation application. An explanation of the thermal circuit for static switches and most used cooling methods are presented. A case study aiming to design an immersion tank for heat dissipation is demonstrated. Experimental results of air and oil. [ABSTRACT FROM AUTHOR]

The challenging demands of pulsed electron beam devices (such as the GESA device) with respect to their pulsed power supply have led to the development of a new semiconductor-based Marx generator. At a maximum output voltage of 120 kV and 600-A pulse current for a duration of up to 100 $\mu \text{S}$ , stepwise arbitrary output waveforms are desired. A fast rise time of the generator is achieved by using fast switching circuitry, low inductance capacitors, and a low inductance stage arrangement. For low jitter triggering of all stages and efficient signal transmission, the generator uses an optical bus system for communication. Due to the inherent dynamic load characteristics of the GESA device, the generator features a fast overcurrent protection scheme. This paper presents selected design aspects of the generator and their validation in a small-scale assembly able of delivering up to 8 kV at 600-A load current. [ABSTRACT FROM AUTHOR]

Soft-switching techniques of transformerless photovoltaic grid-connected inverters (TLIs) can significantly reduce switching losses, as well as soften switching processes. Conventional dc–ac soft-switching configurations proposed by Dr. Deepakraj M. Divan are invalid in TLIs because of the leakage current problem. In order to develop soft-switching techniques in TLIs, this paper proposes a new soft-switching configuration and a procedure to guide the invention of soft-switching TLIs. First, this paper proposes two basic resonance tanks related to dc bus polarities, and then, uses these basic tanks to elevate four popular full-bridge-type TLIs according to the proposed guideline. As a result, four soft-switching TLIs are gained. Second, this paper picks obtained soft-switching highly efficient and reliable inverter concept (HERIC) as example to analyze its soft-switching operation principle and performance. As a consequence, all active switches of the gained soft-switching HERIC circuit are switched under both of zero-current turn-on and turn-off conditions; the reverse recovery problem of freewheeling diodes is alleviated owing to the zero-current turn-off of diodes; meanwhile, the common-mode voltage at the switching frequency scale is still constant. Finally, some experimental results from a 3-kW universal prototype at 50-kHz switching frequency are provided to verify the effectiveness of the main contributions of this paper. [ABSTRACT FROM AUTHOR]

In this paper, we demonstrate the linear conductance-change characteristics of a conductive-bridging RAM (CBRAM) to be employed as an artificial synapse device in neuromorphic systems. The CBRAM with a bilayer electrolyte structure (${\mathrm {Cu/Cu}}_{{2}-{x}}\text{S}$ / $\mathrm {WO}_{{3}-{x}}$ /W) exhibits analog switching behavior during the depression process due to the well-controlled dissolution of the conductive filament. To analyze the origin of this motion, we investigate the effective voltage applied to $\mathrm {Cu}_{{2}-{x}}\text{S}$ and $\mathrm {WO}_{{3}-{x}}$. Our findings reveal that $\mathrm {Cu}_{{2}-{x}}\text{S}$ , acting as a voltage divider, helps in suppressing the large voltage drop in $\mathrm {WO}_{{3}-{x}}$ , where the formation/dissolution of filament occurs. Furthermore, due to the diode-like characteristics of $\mathrm {Cu}_{{2}-{x}}\text{S}$ and the division of voltage drop between $\mathrm {WO}_{{3}-{x}}$ and $\mathrm {Cu}_{{2}-{x}}\text{S}$ , an optimum programming energy is applied to $\mathrm {WO}_{{3}-{x}}$ during the depression process. This leads to linear conductance-change characteristics under identical pulses. However, abrupt conductance-change characteristics are observed during the potentiation process. Thus, we use only the device characteristics of the depression part for the neuromorphic system. An excellent classification accuracy is achieved due to the linear conductance-change characteristics and optimized pulse conditions. [ABSTRACT FROM AUTHOR]

A self-biased CMOS analog mixer for ultra-wideband (UWB) applications is presented in this paper. The proposed mixer is complementary and self-biased, and has lower power consumption, superior isolation, and larger bandwidth. The proposed low-power, down conversion mixer is designed and fabricated in UMC 0.18\mu \textm CMOS technology. The measurement results show that it can operate at UWB frequencies that range from 1 to 6 GHz. The proposed mixer provides a maximum conversion gain of 13 dB, −4.5 dBm of third-order input intercept point, and a minimum double sideband noise figure of 12 dB. The maximum values of the measured local oscillator LO-to-RF, RF-to-IF, and LO-to-IF isolations are 50, 45, and 52 dB, respectively. [ABSTRACT FROM PUBLISHER]

This paper presents a wideband 4-bit true time delay IC using a 0.25 μm GaN HEMT (High-Electron-Mobility Transistor) process for the beam-squint-free phased array antennas. The true time delay IC is implemented with a switched path circuit topology using DPDT (Double Pole Double Throw) with no shunt transistor in the inter-stages to improve the bandwidth and SPDT (Single Pole Single Throw) switches at the input and the output ports. The delay lines are implemented with CLC π-networks with the lumped element to ensure a compact chip size. A negative voltage generator and an SPI controller are implemented in the PCB (Printed Circuit Board) due to the lack of digital control logic in GaN technology. A maximum time delay of ~182 ps with a time delay resolution of 10.5 ps is achieved at DC–6 GHz. The RMS (Root Mean Square) time delay and amplitude error are <5 ps and <0.6 dB, respectively. The measured insertion loss is <6.8 dB and the input and output return losses are >10 dB at DC–6 GHz. The current consumption is nearly zero with a 3.3 V supply. The chip size including pads is 2.45 × 1.75 mm2. To the authors' knowledge, this is the first demonstration of a true time delay IC using GaN HEMT technology. [ABSTRACT FROM AUTHOR]

Due to their efficiency and control capabilities, induction motors fed with inverters have become prevalent in various industrial applications. However, ensuring the reliable operation of the motor and diagnosing faults on time are crucial for preventing unexpected failures and minimizing downtime. This paper systematically analyzes condition monitoring and practical diagnostic techniques for inverter-fed motor drive systems. This study encompasses a thorough evaluation of different methods used for condition monitoring and diagnostics of induction motors, with the most crucial faults in their stator, rotor, bearings, eccentricity, shaft currents, and partial discharges. It also includes an assessment of their applicability. The presented analysis includes a focus on the challenges associated with inverter-fed systems, such as high-frequency harmonics, common-mode voltages causing the bearing currents, and high voltage gradients (dv/dt) due to fast switching frequency, which can impact the motor operation, as well as its faults analysis. Furthermore, this research explores the usefulness and efficiency of various available diagnostic methods, such as motor current signature analysis and other useful analyses using advanced signal processing techniques. This study aims to present findings that provide valuable insights for developing comprehensive condition monitoring strategies, and practical diagnostic techniques that enable proactive maintenance, enhanced system performance, and improved operational reliability of inverter-fed motor drive systems. [ABSTRACT FROM AUTHOR]

Layout stitching is a repetitive and tedious task of the radio frequency integrated circuit (RFIC) design process. While academic research on layout splicing algorithms mainly focuses on analog and digital circuits, there is still a lack of well-developed algorithms for RFICs. An RFIC system usually has a symmetrical layout, such as transmitter and receiver components, low-noise amplifier (LNA), an SPDT switch, etc. This paper aims to address this gap by proposing an automated procedure for the layout of RFICs by relying on the basic device/PCell structure based on the interconnection among circuit topologies. This approach makes the in-series generation of layouts and automatic splicing based on circuit logic possible, resulting in superior stitching performance compared with related modules in Advanced Design System. To demonstrate the physical application possibilities, we implemented our algorithm on an LNA and a switch circuit. [ABSTRACT FROM AUTHOR]

This paper proposes an extension of the model predictive control framework for switching continuous‐time linear systems. The switching times follow a stochastic process with limited statistical information. At each switching time, the controller knows the system state, but it is blind with respect to the switching continuous‐time subsystems. In this setting, the paper's main contribution is to show how to compute the model predictive control gain. The paper also illustrates the implications of our approach for applications. The approach was used in practice to control an electric current source that supplied a switching load. The experimental data support the usefulness of our approach. [ABSTRACT FROM AUTHOR]

This paper describes the efficient MPPT tracking for variable wind speed using an artificial neural network. The neural network has been trained using the backpropagation algorithm and Levenberg-Marquardt (LM) based optimization technique to achieve maximum power point. A multilevel inverter having 10 switches has been used to reduce voltage stress, THD and switching losses resulting in improvement in performance and reduction in the driver circuit for the switches. The proposed system has been validated and simulated in SIMULINK/MATLAB. [ABSTRACT FROM AUTHOR]

Hardware Trojan attacks have emerged as a major security issue for hardware at different level of abstractions, which relate to malicious tampering of a hardware during design or fabrication process. In this paper, a new low overhead and high speed design for trust methodology for increasing both full activation and side channel sensitivity of Trojan is proposed. The main idea is that the increase in transition probability of individual nets does not necessarily increase the transition probability of the succeeding nets of the circuit. Accordingly, the rules and conflicts of the propagation of maximum transition probability for individual gates have been presented to ensure that a full transition path is constructed between each low transition probability net and primary inputs of the circuit. The results show that the proposed methodology achieves superior efficiency in Trojan full activation by more than $4 \times $ through logic testing approach besides higher sensitivity averagely around $20 {\times }$ for power-based side channel analysis compared to existing methods. [ABSTRACT FROM AUTHOR]

The purpose of this paper is to investigate a novel flux-switching permanent magnet (FSPM) machine that is amenable for high-speed operation. The low-pole topology of high-speed machine is favorable to minimize fundamental frequency requirement. The lowest possible three-phase topology of the FSPM machine, with six stator slots and four rotor poles (6/4), has unacceptably large second-order harmonic distortion in the flux linkage and severe cogging torque in its conventional single-stator–single-rotor form. To resolve these challenges, a novel dual-stator structure is proposed that eliminates the even-order harmonics in the flux linkage. Harmonic distortion and cogging torque are notably reduced in the proposed machine. The principles of operation and design methods are described in this paper. The properties of the proposed dual-stator 6/4 FSPM machine are compared with a conventional 6/4 FSPM machine and a conventional 12/10 FSPM machine for a 5 kW, 15 000 r/min design. Comparison results gathered from 3-D finite-element analysis demonstrate that the proposed dual-stator 6/4 FSPM machine achieves significantly better flux linkage, back EMF, and cogging torque than the conventional 6/4 design and better efficiency than the conventional 12/10 FSPM machine. [ABSTRACT FROM PUBLISHER]

A comprehensive study on the dielectric modulated (DM) drift region for power devices is presented in this paper. The performance of this drift region structure is theoretically analyzed and compared with other two structures: conventional and superjunction. In this paper, a study is focused on switching performance. The C – V relationships during switching are analytically derived, and the depletion widths predicted by the proposed analytical model agree well with simulation in a wide reverse bias region. The switching energy loss is evaluated based on the analytical model and its accuracy is verified by 2-D simulations. An effective depletion charge QD is defined as E\mathrm {loss} / breakdown voltage (BV), from which a figure of merit (FOM) of R\mathrm{\scriptscriptstyle ON,\mathrm {sp}}{}^\ast QD is proposed to compare the performances of these different drift region structures, considering both the conduction and switching losses. The discussions in part I on Si and silicon carbide device structures are extended in part II to include FOMs. It is found that the DM drift region structures show better R\mathrm{\scriptscriptstyle ON,\mathrm {sp}} -BV tradeoffs compared with the conventional structures, but slighter inferior FOMs. However, DM structures are still attractive for applications, where switching loss is less critical than the conduction loss, such as low frequency or soft switching. [ABSTRACT FROM PUBLISHER]