1. Design and Implementation of a Pipelined Bit-Serial SFQ Microprocessor, CORE11β.
- Author
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Yamanashi, Y., Tanaka, M., Akimoto, A., Park, H., Kamiya, Y., Irie, N., Yoshikawa, N., Fujimaki, A., Terai, H., and Hashimoto, Y.
- Subjects
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DIGITAL electronics , *MICROPROCESSORS , *DATA pipelining , *ELECTRICAL engineering , *ELECTRONIC circuit design , *TRANSISTOR circuits , *ELECTRONIC industries , *ELECTRIC capacity , *ENCODING - Abstract
A pipelined 8-bit-serial single-flux-quantum (SFQ) microprocessor, called CORE1β, was designed and tested. The CORE1β has two cascaded arithmetic logic units (ALUs) based on forwarding architecture, which can perform two register operations from one instruction. Pipelining is also extensively adopted to enhance the performance. A new design method, known as one-hot encoding, has been introduced into the design of the control circuit. The 4-stage-pipelined SFQ microprocessors, CORE1β8, have been implemented using the CONNECT cell library and the SRL 2.5 kA/cm2 Nb process. The frequency for the instruction fetch is 25 GHz, and 20 GHz for the bit-serial data operation. The peak performance and the power consumption of the CORE1β8 are estimated to be 1400 MOPS (million instructions per second) and 3.4 mW, respectively. We have experimentally demonstrated 4-stage pipelining and all functionalities of the CORE1β8 microprocessors by on-chip high-speed tests. [ABSTRACT FROM AUTHOR]
- Published
- 2007
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