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A pipelined 8-bit-serial single-flux-quantum (SFQ) microprocessor, called CORE1β, was designed and tested. The CORE1β has two cascaded arithmetic logic units (ALUs) based on forwarding architecture, which can perform two register operations from one instruction. Pipelining is also extensively adopted to enhance the performance. A new design method, known as one-hot encoding, has been introduced into the design of the control circuit. The 4-stage-pipelined SFQ microprocessors, CORE1β8, have been implemented using the CONNECT cell library and the SRL 2.5 kA/cm2 Nb process. The frequency for the instruction fetch is 25 GHz, and 20 GHz for the bit-serial data operation. The peak performance and the power consumption of the CORE1β8 are estimated to be 1400 MOPS (million instructions per second) and 3.4 mW, respectively. We have experimentally demonstrated 4-stage pipelining and all functionalities of the CORE1β8 microprocessors by on-chip high-speed tests. [ABSTRACT FROM AUTHOR]

We have successfully demonstrated an 8-bit microprocessor using passive transmission lines based on single-flux-quantum LSI technology, in the microprocessor designed here, called CORE1α6, a simple bit-serial architecture with seven instructions was employed. In the CORE1α6, the floor plan was designed with consideration toward integration of a memory, and superconductive passive transmission lines (PTLs) were used to connect circuit blocks. Utilization of PTLs helped us reduce the propagation delay in long interconnections The design flexibility of the floor plan was enhanced and the performance of the microprocessor was improved by 20% compared with our previous design. The CORE1α6 was composed of 6319 Josephson junctions and 15 PTLs with power consumption of 2.1 mW. We have confirmed the complete operations of the CORE1Ξ6 by on-chip high-speed tests. The maximum clock frequencies for bit operation and instruction execution have been found to be 18 GHz and 1.2 GHz, respectively, where the performance corresponds to 240 million instructions per second (MIPS). [ABSTRACT FROM AUTHOR]