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We conducted reliability characterization under reverse-bias stress (i.e., stress at OFF-state with high VDS) on the E-mode GaN metal–insulator–semiconductor field-effect-transistors (MIS-FETs) with various substrate terminations. The MIS-FETs with floating substrate (FS) show worse threshold voltage (VTH) stability than that with a grounded substrate. A non monotonic dependence of VTH shifts and OFF-state time-to-breakdown (tbd) on the positive substrate bias (Vsub) was also observed. The underlying mechanisms are the different impacts of positive Vsub on the drift of electrons and holes during the long-term stress. An important indication is that positive-biased and FS terminations should be restricted at OFF-state in order to obtain good VTH stability in applications of the GaN MIS-FET. [ABSTRACT FROM AUTHOR]

Low-loss reverse-conducting normally- OFF double-channel AlGaN/GaN power transistor with the built-in Schottky barrier diode (SBD) has been systematically studied. This device features the MOS-gate section and SBD-anode section paralleled to an interdigital layout along the gate width direction. A common access region that conducts current at both forward and reverse ON-states is employed, which is beneficial to reduce the conduction loss. With a MOS-HEMT/SBD finger width of ${4}~\mu \text{m}/2~\mu \text{m}$ and a total width ratio of 2:1, the device exhibits a threshold voltage of +0.8 V at a drain current of ${10}~\mu \text{A}$ /mm and a low forward ON-resistance of $12.1~\Omega \cdot \text {mm}$. The Schottky metal contacts 2-DEG directly, which results in a low reverse turn-on voltage of −0.6 V (at −1 mA/mm) and low reverse ON-state voltage of −1.7 V (at −50 mA/mm). A leakage suppression MOS field plate (FP) is applied to shield the Schottky contact from the strong electric field, leading to a low OFF-state leakage current of 14 nA/mm at +100-V drain bias and a high breakdown voltage (BV) of +698 V. The finger width and the number of fingers should be optimized. A narrow finger width benefits the current sharing at the access region, while the increasing number of fingers introduces more Schottky depletion regions along the gate width direction that degrade ${R}_{ \mathrm{\scriptscriptstyle ON}}$. [ABSTRACT FROM AUTHOR]

Under reverse-bias stress (i.e., OFF-state stress with ${V} _{\text {GS}} < {V}_{\text {TH}}$) with high drain voltage, ultraviolet (UV) illumination and larger negative gate bias are found to accelerate the positive shift in threshold voltage (${V}_{\text {TH}}$) of enhancement-mode GaN MIS-FETs with fully recessed gate. These results suggest a hole-induced degradation mechanism. In the absence of UV illumination, holes could be generated by impact ionization in the high electric-field region, which is initiated by electrons injected from the source through the buffer layer. With a larger negative gate bias, more holes will flow to the gate side and pass through the silicon nitride (SiNx) gate dielectric, as SiNx does not present any energy barrier to holes. The enhanced hole transport through the dielectric under large negative gate bias could accelerate new defects generation and therefore result in the larger positive threshold voltage shifts. [ABSTRACT FROM AUTHOR]