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This brief presents a brief tutorial on recent circuit design techniques for high efficiency fully-integrated switched-capacitor (SC) converters. Design challenges for fully-integrated SC converters are highlighted, followed by consideration of tradeoffs among topology generation, parasitic loss reduction, clock generation and distribution, and close-loop regulation. Circuit techniques and design guidelines are suggested. [ABSTRACT FROM AUTHOR]

A fully integrated switched-capacitor (SC) dc–dc converter is designed for powering up an active-matrix light-emitting diode (AMLED) microdisplay system. The stacking-transistor technique with three voltage conversion ratios is utilized to handle the lithium-ion battery range of 2.6–4.2 V and to reduce the switching loss. A 101-phase interleaving scheme is adopted such that, first, output voltage ripple $\Delta V_{{\rm{O}}}$ is significantly reduced; second, no external output capacitor is needed; and, third, SC power-cells are physically cascaded to encircle the LED array and drivers to reduce conduction loss. Two test chips were designed in the 0.18-μm 1P6M CMOS technology. The first chip is a test chip comprising the SC converter only. The output voltage is 4.2 V, and the measured maximum $\Delta V_{{\rm{O}}}$ is 52 mV. The measured power density is 74.4 mW/mm2, peak efficiency is 81%, and maximum output power is 258 mW. The second chip is a system chip integrating the SC converter with the AMLED array and drivers using flip-chip packaging. The converter delivers a maximum power of 216 mW with a 78% peak efficiency in the SC mode and a 91% peak efficiency in the linear regulator mode. [ABSTRACT FROM AUTHOR]

In this letter, subtraction-mode switched-capacitor (SC) converters are proposed and analyzed. When compared to a conventional summation-mode SC converter, some of the flying capacitors of the subtraction-mode SC converters have reduced voltage swings, and hence the switching loss of the corresponding positive- and negative-plate parasitic capacitors is reduced, and efficiency is enhanced. The proposed subtraction-mode topologies use the same number of flying capacitors and switches as the summation-mode topologies, and they are reconfigured without using any auxiliary circuits, so there are no tradeoffs in terms of power density, cost, voltage conversion ratio (VCR), or equivalent output resistance. A test chip with VCRs of 1/3×, 2/3×, 3/4×, and 4/5× was fabricated in a 65-nm CMOS process. Efficiency improvement of more than 10% was achieved when compared to summation-mode designs. [ABSTRACT FROM AUTHOR]