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This paper continues the STACS contribution by Diekert, Ushakov, and the author as well as the IJAC publication by the same authors. We extend the results published there in two ways. First, we show that the data structure of power circuits can be generalized to work with arbitrary bases q≥2. This results in a data structure that can hold huge integers, arising by iteratively forming powers of q. We show that the properties of power circuits known for q=2 translate to the general case. This generalization is non-trivial and additional techniques are required to preserve the time bounds of arithmetic operations that were shown for the case q=2. The extended power circuit model permits us to conduct operations in the Baumslag-Solitar group BS(1, q) as efficiently as in BS(1,2). This allows us to solve the word problem in the generalization H(1, q) of Higman's group in polynomial time. The group H(1, q) is an amalgamated product of four copies of the Baumslag-Solitar group BS(1, q) rather than BS(1,2) in the original group H= H(1,2). As a second result, we allow arbitrary numbers f≥4 of copies of BS(1, q), leading to an even more generalized notion of Higman groups H(1, q). We prove that the word problem of the latter can still be solved within the ${\mathcal {O}}(n^{6})$ time bound that was shown for H(1,2). [ABSTRACT FROM AUTHOR]

Abstract: This paper presents a kind of novel binary code compression algorithm to reduce the size of the signal processing circuit and to realize real time compensation for the modulation error in fiber optic gyroscope (FOG). The disadvantage of general compensation method is figured out firstly. The modulation error is modeled and analyzed with taking the closed-loop characteristics into consideration. The analysis indicates the condition in which the error compensation is effective and real time. Then the compensation algorithm based on binary code compression operation is described. The functional design of the algorithm is realized in a single field programmable gate array (FPGA) by using modular design method, substituting some harewares in signal processing circuit, and system speed is very fast. The simulation and experiment results suggest that the algorithm and implementation is valid. The modulation error is real time compensated in every error detection cycle, and the error compensation resolution is enhanced from 2−10 to 2−16 rad/V. [Copyright &y& Elsevier]