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Optics means a general area of physics that covers a broad range of topics relevant to the study of light. Optics has subfields they are quantum optics, geometrical optics, and physical optics. Photonics refers to a subset of the optics discipline. The simplicity, high efficiency, reliability, transparency, and robust feature of PID controllers were few factors behind the reasons for its acceptance and more popularity for control in processing industries globally. All the conventional techniques for PID controller design and tuning offer early workable values for reaching favorable performances. The manual tuning of the PID controller variables becomes a difficult role that needs comprehensive knowledge and expertise in that field. Certain meta-heuristic techniques are explored to design PID controllers with the main aims of attaining minimum overshoot in lesser settling time and steady state response. For accomplishing enhanced robustness, minimization of disturbance elimination, operating, and physical restraints are treated as multi-optics functions. Therefore, this article presents a modified honey badger optimization (MoHBO) algorithm-based parameter tuning of the PID controller for optics and photonics. The tuning of the PID controller with constraints on the relative delay margin was considered an optimum disturbance rejection issue and summarized the tuning process. The presented MoHBO algorithm is derived by the inclusion of oppositional based learning (OBL) with standard HBO algorithm. In addition, the MoHBO algorithm is tested using the Magnetic Levitation System (MLS) and Phase Locked Loop system (PLL) to assure the enhanced robust nature of the PID controller. A wide ranging comparison study with other metaheuristic optimization algorithms demonstrates the better performance of the MoHBO algorithm over recent algorithms. [ABSTRACT FROM AUTHOR]

The minimal-degree distributed denial-of-service attack takes advantage of flaws in the adaptive mechanisms of network protocols, which could have a big impact on network service quality. It is very hard to find, has a low attack rate, and comes at a set time. Detection methods that have been used before have problems because they only use one type of detection and are not very good at identifying the object. In the end, a way to detect many sorts of minimal DDoS assaults that use deep hybrid learning is suggested. To construct multi-type limited DDoS threat data sets and mimic diverse sorts DDoS assaults and legitimate traffic in varying situations in the 5G setting, collect congestion at the networking entry and extract flow feature info are considered. From a statistical threshold and feature engineering point of view, these data sets show how many sorts of minimal DDoS assaults are there. This study aims to develop a deep hybrid learning-based multi-type low-rate DDoS attack detection solution for 5G networks which is the novel model that is recently deployed, and a hybrid deep learning algorithm was used to train the algorithm offline, and the algorithm's performance was compared to that of the LSTM-Light GBM and LSTM-RF algorithms. The CNN-RF revealing model was then used to detect minimal DDoS assaults at the gateway, so that multiple attacks could be detected at the same time. It can identify 4 sorts of low-rate DDoS assaults like Slow-Headers, Slow-Body, Slow-Read, and Shrew assaults, in a 120-second window. The false intercept rate is 11.03 percent. This means that 96.22 percent of traffic could be found. Using the strategy suggested can help cut down on the traffic concentration of minimal DDoS attacks at the net ingress. It can also be used in real-world situations. [ABSTRACT FROM AUTHOR]

Application-Specific Instruction-set Processors (ASIPs) have gained popularity in production chips as well as in the research community. They offer a viable solution to the tradeoff between efficiency and flexibility for the embedded System-on-a- Chip (SoC). Generally, an ASIP has the capability to extend the base instruction set of a general-purpose processor with a set of customized instructions supported by the specific hardware resources provided on the ASIP. The hardware implementing the specific instructions can be either runtime reconfigurable functional units, or pre-synthesized circuits. In this paper, we propose a framework for prototype application within FPGAs devices using ASIPs and multiprocessors architecture. Firstly, we provide an overview of a method to identify coarse and finite grain instruction set extensions in application code and integration process of ASIP. Second, we split the data input application to get concurrence and the data dependency of the target application in order to process to multiprocessor execution. Finally, we compare the performances levels given by the execution of the application using ASIP architecture and multiprocessor architecture. [ABSTRACT FROM AUTHOR]