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With the vigorous development of industrial automation and the Internet of things, the transmission of data is more dependent on immediacy, so network devices have higher and higher requirements for time synchronization accuracy. The clock source of common network devices is provided by the transistor oscillator in the server, but the oscillator will change with factors such as aging and temperature, and it cannot be guaranteed that the oscillator in the server will work at the same frequency. Time synchronization can be achieved by technologies such as IRIG-B, NTP, or IEEE 1588 (PTP), but the hardware cost of building IRIG-B is high, and NTP has the lowest cost, but it can only provide time accuracy from milliseconds to microseconds. PTP can provide sub-microsecond or even nanosecond time precision. It is a system of time synchronization mechanisms through Ethernet transmission. In this article, we first propose a time synchronization system using the development board and PDP protocol. On the Xilinx Zynq-7000 SOC platform of Petalinux, we implement the hardware solution of Linux PTP. The hardware time stamp is 20 ns. To improve the accuracy, the congenital frequency error between the oscillators must be considered. Therefore, a PTP auxiliary time stamp with dynamic frequency compensation is proposed and designed into a chip. Experimental results show that at 45 nm (TN40G) it can operate at 370 MHz and achieve 2.7 ns resolution, which can be applied to more demands. [ABSTRACT FROM AUTHOR]

The main causes of damage to industrial machinery are aging, corrosion, and the wear of parts, which affect the accuracy of machinery and product precision. Identifying problems early and predicting the life cycle of a machine for early maintenance can avoid costly plant failures. Compared with other sensing and monitoring instruments, sound sensors are inexpensive, portable, and have less computational data. This paper proposed a machine tool life cycle model with noise reduction. The life cycle model uses Mel-Frequency Cepstral Coefficients (MFCC) to extract audio features. A Deep Neural Network (DNN) is used to understand the relationship between audio features and life cycle, and then determine the audio signal corresponding to the aging degree. The noise reduction model simulates the actual environment by adding noise and extracts features by Power Normalized Cepstral Coefficients (PNCC), and designs Mask as the DNN's learning target to eliminate the effect of noise. The effect of the denoising model is improved by 6.8% under Short-Time Objective Intelligibility (STOI). There is a 3.9% improvement under Perceptual Evaluation of Speech Quality (PESQ). The life cycle model accuracy before denoising is 76%. After adding the noise reduction system, the accuracy of the life cycle model is increased to 80%. [ABSTRACT FROM AUTHOR]

In the industrial Internet of Things, the network time protocol (NTP) can be used for time synchronization, allowing machines to run in sync so that machines can take critical actions within 1 ms. However, the commonly used NTP mechanism does not take into account that the network packet travel time over a link is time-varying, which causes the NTP to make incorrect synchronization decisions. Therefore, this paper proposed a low-cost modification to NTP with clock skew compensation and adaptive clock adjustment, so that the clock difference between the NTP client and NTP server can be controlled within 1 ms in the wired network environment. The adaptive clock adjustment skips the clock offset calculation when the NTP packet run trip time (RTT) exceeds a certain threshold. The clock skew compensation addresses the inherent issue that different clocks (or oscillators) naturally drift away from each other. Both adaptive clock adjustment and clock skew compensation are environment dependent and device dependent. The measurement result in our experimental environment shows that the when the RTT threshold is set at 1.7 ms, the best synchronization accuracy is achieved. [ABSTRACT FROM AUTHOR]

This paper presents the design exploration and applications of a spurious-power suppression technique (SPST) which can dramatically reduce the power dissipation of combinational VLSI designs for multimedia/DSP purposes. The proposed SPST separates the target designs into two parts, i.e., the most significant part and least significant part (MSP and LSP), and turns off the MSP when it does not affect the computation results to save power. Furthermore, this paper proposes an original glitch-diminishing technique to filter out useless switching power by asserting the data signals after the data transient period. This paper adopts two multimedia/DSP design examples, i.e., a multitransform design for H.264 and a versatile multimedia functional unit (VMFU), to evaluate the proposed SPST. These two design examples have quite different hardware configurations, thus, the realization issues of the SPST on every design also remarkably differ from each other. The multitransform design can compute three transforms which are required in H.264 encoding while the VMFU possesses six commonly used multimedia/DSP functions, namely, addition, subtraction, multiplication, MAC, interpolation, and sum-of-absolute-difference. After optimizing the design elaborately, we find that the proposed SPST can, respectively, save 27% and 24% power dissipation on average of the H.264 multitransform design and the VMFU at the expense of less than 20% area augmentation. Index Terms--Digital-signal processing chips, image coding, low-power design, video coding.

This paper proposes a low-power ASIC design of pseudonoise code synchronization for wireless code-division multiple access (WCDMA), CDMA2000, and IEEE 802.11 g systems. WCDMA and CDMA 2000 are two major standards in third-generation (3G) communication systems. Since 3G and 802.11 g are based on the same CDMA technology, there are common parts in the code synchronization hardware. We integrate the three systems on one ASIC. In addition, we use three kinds of low-power techniques in the design that include power management, absolute weighted magnitude calculation, and spurious power suppression adder. They can save 57.37% power consumption in WCDMA synchronization, 6.06% power consumption in CDMA2000 synchronization, and 84.69% power consumption in 802.11 g synchronization. The low-power synchronizer is implemented with an operating voltage of 1.2 V, 0.13-[micro]m CMOS technology, and chip area of 2.1 x 2.1 m[m.sup.2]. Index Terms--Code-division multiple access (CDMA), synchronization, wireless communication systems.

This paper proposes a complete cell-search solution for real-world handset operations in the wide-band code-division multiple-access system. Large-frequency and clock errors are induced at initial search due to an inaccuracy of crystal oscillators within handsets and could cause fatal performance degradation. In addition to a primary search algorithm for achieving essential pseudo-noise code acquisitions, an enhanced algorithm combining frequency offset compensation, random sample per frame, and sample point reordering is proposed to achieve fast initial search even while an inaccuracy is up to 12 ppm. After a series of trade-off between performance and complexity, two search bins in the first stage are adopted to mitigate possible errors in each bin and make the enhanced schemes become effective. In final, the complete solution is presented with alternative algorithms: a primary one and an enhanced one. The solution is implemented with the flexibility for switching algorithms in different searches and using low-power methods for the sake of handsets' working time. Its core area is 3.8 x 3.8-[mm.sup.2] in a 3.3-V 0.35-mm CMOS technology, and the power consumption is 35.6 and 67 mW for the primary and enhanced algorithms, respectively. Index Terms--Cell search, clock error, frequency error, frequency offset compensation (FOC), low-power design, random sample per frame (RSPF), sample point reordering (SPR), wide-band code-division multiple-access (WCDMA).

This paper proposes an area-efficient variable length decoder (VLD) IP core design for MPEG-1/2/4 video coding applications. The proposed IP core exploits the parallel numerical matching in the MPEG-1/2/4 entropy decoding to achieve high data throughput rate in terms of limited hardware cost. This feature not only improves the performance of VLD, but also facilitates reducing the power consumption through lowering down the supply voltage while maintaining enough data throughput rate. Moreover, we propose a partial combinational component enabling approach for minimizing the power consumption of the proposed design. Based on 0.18-[micro] technology, the implementation results show that the proposed IP core operates at 125-MHz clock frequency with the cost of 13 105 gates. In addition, the power consumption of the proposed design reaches 163.4 [micro]W operated at 12.5 MHz with 0.9-V supply voltage, which is fast enough for MPEG-1/2/4 real-time decoding on 4CIF video@30 Hz. Compared to the existing designs, the proposed IP core possesses both higher data throughput and less hardware cost. Index Terms--Low-power design, MPEG, variable length decoder (VLD).

Aiming to increase the transmission data rate, the spatial modulation (SM) scheme maps each block of information bits to a digitally modulated symbol and additionally a transmit antenna index in a multiple transmit antenna system. In this brief, we focus on the maximum likelihood detection (MLD) scheme that detects SM signals with low computational complexity. By reformulating the MLD problem, we obtain a new mathematical expression as the MLD solution. To avoid the numerically unstable division operation, we apply the Givens rotation to realize this new expression and obtain a low-complexity MLD algorithm. We also propose a coordinate rotation digital computer-based hardware architecture to detect SM signals with 64-quaternary amplitude modulated (QAM) symbols over the correlated channel with eight transmit antennas and four receive antennas. The VLSI implementation results under the TSMC 90-nm CMOS technology reveal that our division-free architecture requires 70.5K gates and provides detection throughput 432.68 Mb/s, while operating at frequency 384.6 MHz. Our design is the first hardware architecture to achieve the exact MLD performance and is easily modified to detect SM signals with arbitrary ${M}$ -ary QAM symbols and arbitrary numbers of transmit and receive antennas. [ABSTRACT FROM AUTHOR]

This paper presents a systematic method for decreasing the amount of transconductors used by an operational transconductance amplifier–capacitor (OTA–C) filter to decrease the power consumption and the active area. An OTA with a local-feedback linearized technique and a transconductance booster is proposed based on the presented method. The proposed OTA combines current division with source degeneration to enhance linearity and implement low transconductance. This topology enables the proposed OTA to drive multiple integration capacitors without an additional output stage. The OTA-based circuit realizes low power consumption by operating under a weak inversion at a supply voltage of 1 V. Thus, a fifth-order ladder-type low-pass Butterworth OTA–C filter is implemented for the acquisition of electrocardiograph signals. The proposed method is validated using a prototype fabricated through a 1P6M 0.18-μm CMOS process. Results show that in ECG signal acquisition, the proposed filter has a signal bandwidth located within 250 Hz, a dynamic range of 61.2 dB, and a power consumption of 41 nW to achieve a figure-of-merit of 5.4 × 10−13. The active area of the filter is 0.24 mm2. [ABSTRACT FROM AUTHOR]

Compared with the single tree detector, the layered orthogonal lattice detector (LORD), developed by Siti et al., is a well-known soft-output multiple input multiple output detector to exploit M parallel tree traversals to deliver data with M times of detection throughput rate. The preprocessing QR-decomposition (QRD) of the M -by- M channel matrix for the single tree detector is of complexity proportional to M^3 . However, the preprocessing QRD for the LORD needs to compute the M permuted channel matrices that are constructed from the original M -by- M channel matrix through the root conditioning criterion. The original LORD algorithm for this root conditioning QRD (RC-QRD) relies on the Gram-Schmidt orthogonalization and is of complexity proportional to M^4 for large M . In this brief, we apply the Givens rotation and take advantage of the relationships among the M permuted matrices to develop an RC-QRD algorithm with complexity proportional to M^3 . Furthermore, when M is large, our proposed RC-QRD algorithm requires the number of real Givens rotations about 1.8 times necessary for computing a conventional matrix QRD. Also, for M=4 , our proposed RC-QRD hardware architecture requires gate count 2.1 times that required by the conventional triangular systolic array to compute a matrix QRD. Accordingly, with only about two times of complexity for the preprocessing RC-QRD, the LORD is able to perform M tree traversals to deliver data with M times of throughput rate. [ABSTRACT FROM AUTHOR]

This study presents a low‐power energy‐harvesting circuit with error‐correction demodulation for body sensor networks with radio‐frequency identification (RFID) systems. The proposed circuit adopts a new structure that facilitates the demodulation of amplitude‐shift‐keying (ASK) signals, and it includes a power unit consisting of a wake‐up circuit and a power‐on‐reset control circuit. The wireless bio‐signal acquisition system and the digital processor are implemented on a field‐programmable gate array to demonstrate the proposed RFID tag. The proposed energy‐harvesting circuit can substantially decrease the capacitance used by the demodulator circuit and the wake‐up circuit to as low as 14 pF. Moreover, a detection circuit and a correcting circuit are utilised to reduce the bit error rate of decoding. The wireless bio‐signal acquisition scenario is also set up and the communication signal between reader and tag is measured to demonstrate the system that can be employed in body sensor network with the healthcare system. The chip was implemented in complementary metal–oxide–semiconductor 0.18 μm technology. The sensitivity of this work is − 13 dBm. The pulse width error can be reduced to <1% by the error‐correction demodulator to fit the EPC Gen‐2 standard. [ABSTRACT FROM AUTHOR]

The compressed beamforming weights (CBWs) feedback is used in the IEEE 802.11n/ac WLAN, an example of the practical beamforming multiple input multiple output-orthogonal frequency division multiplexing system, to reduce the amount of feedback information so that the beamformee can respond rapidly to the beamformer. The CBW associated with each sub-carrier includes the quantized angles obtained from QR-decomposition (QRD) of the right singular vectors of each corresponding channel matrix. Efficient matrix QRD and singular value decomposition (SVD) together are therefore desirable for computing the CBWs associated with all sub-carriers. Considering the exemplary antenna configuration of 4 beamformer and 2 beamformee antennas, we propose to apply the same matrix triangulation to compute the SVD of a 2-by-4 matrix and to compute the QRD of a 4-by-2 matrix. We can achieve gate count reduction by exploiting only one matrix triangulation module in our architecture. The VLSI implementation results under the TSMC 90-ns CMOS technology reveal that our architecture requires 194.25K gates while operating at frequency 200.75 MHz. Additionally, with better normalized matrix throughput and gate efficiency, our architecture outperforms one earlier architectural design to compute the CBWs. [ABSTRACT FROM PUBLISHER]

Designing a real-time video-streaming system involves the challenges of, network congestion and bandwidth fluctuations, lowering the video quality. In this paper, a realtime video-streaming system is designed and implemented for scalable video coding (SVC) with an adaptive control scheme, containing macro- and micro-control, to resolve the bandwidth fluctuation and network congestion. Under macro-control, the server allocates appropriated video-streaming of SVC for heterogeneous clients based on terminal capacity and network conditions. Under micro-control, the server changes the video frame rate based on video bit rates and network bandwidth. The streaming system with the adaptive control scheme is implemented to improve the peak signal noise ratio (PSNR) by 4.01 % to 10.89 % of the Foreman and Stefan videos. [ABSTRACT FROM AUTHOR]

The main causes of damage to industrial machinery are aging, corrosion, and the wear of parts, which affect the accuracy of machinery and product precision. Identifying problems early and predicting the life cycle of a machine for early maintenance can avoid costly plant failures. Compared with other sensing and monitoring instruments, sound sensors are inexpensive, portable, and have less computational data. This paper proposed a machine tool life cycle model with noise reduction. The life cycle model uses Mel-Frequency Cepstral Coefficients (MFCC) to extract audio features. A Deep Neural Network (DNN) is used to understand the relationship between audio features and life cycle, and then determine the audio signal corresponding to the aging degree. The noise reduction model simulates the actual environment by adding noise and extracts features by Power Normalized Cepstral Coefficients (PNCC), and designs Mask as the DNN's learning target to eliminate the effect of noise. The effect of the denoising model is improved by 6.8% under Short-Time Objective Intelligibility (STOI). There is a 3.9% improvement under Perceptual Evaluation of Speech Quality (PESQ). The life cycle model accuracy before denoising is 76%. After adding the noise reduction system, the accuracy of the life cycle model is increased to 80%.